JPS6010629B2 - Driving method of thin film EL element - Google Patents

Driving method of thin film EL element

Info

Publication number
JPS6010629B2
JPS6010629B2 JP52073522A JP7352277A JPS6010629B2 JP S6010629 B2 JPS6010629 B2 JP S6010629B2 JP 52073522 A JP52073522 A JP 52073522A JP 7352277 A JP7352277 A JP 7352277A JP S6010629 B2 JPS6010629 B2 JP S6010629B2
Authority
JP
Japan
Prior art keywords
pulse
pulse width
amplitude
thin film
luminance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52073522A
Other languages
Japanese (ja)
Other versions
JPS5412227A (en
Inventor
敏弘 大場
修平 安田
忠二 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP52073522A priority Critical patent/JPS6010629B2/en
Publication of JPS5412227A publication Critical patent/JPS5412227A/en
Publication of JPS6010629B2 publication Critical patent/JPS6010629B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は三層構造薄膜EL素子の新しい駆動法に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a new method for driving a three-layer thin film EL device.

特に本発明は電源、トランジスタ等の回路要素の数が少
なく、また調整の容易な駆動回路を提供するものである
。本発に用いられる三層構造薄膜EL素子は第1図に示
すような構造を持つ。
In particular, the present invention provides a drive circuit that has a small number of circuit elements such as a power supply and transistors, and is easy to adjust. The three-layer thin film EL device used in this invention has a structure as shown in FIG.

ガラス基板1の上にIQ03の透明電極2を設ける。A transparent electrode 2 of IQ03 is provided on a glass substrate 1.

この上に例えばY203,Sj3N4,Ti02等の誘
電物質層3を、更にこの上に例えばMmをドープしたZ
船等の蛍光層4を膜厚を500〜10000Aにして、
更にその上に上記と同じ誘電物質3′を蒸着法、スパッ
タ法等により被着して3層構造にし、その上にAI等の
背面電極5を配置して構成される。上記電極2と5は互
いに直交する帯状電極に構成されてマトリックス表示が
行われる。このような構造のELPは輝度や寿命、安定
性の点で従来の分散型EL素子に比して優れた特性を有
しているとともに、このELPはその作成条件を特殊に
することにより新たに輝度と印加電圧の間に第2図bの
如き履歴現象を示す。
On top of this is a dielectric material layer 3 of, for example, Y203, Sj3N4, Ti02, etc., and further on this is a Z layer doped with, for example, Mm.
The fluorescent layer 4 of ships etc. has a film thickness of 500 to 10000A,
Further, the same dielectric material 3' as described above is deposited thereon by vapor deposition, sputtering, etc. to form a three-layer structure, and a back electrode 5 made of AI or the like is disposed on top of this. The electrodes 2 and 5 are formed into strip-shaped electrodes that are perpendicular to each other to perform matrix display. ELPs with this structure have superior characteristics in terms of brightness, lifespan, and stability compared to conventional dispersion-type EL elements. A hysteresis phenomenon as shown in FIG. 2b is shown between the brightness and the applied voltage.

この特性を第2図に従い説明すると、最初第2図aの如
く電圧振幅V,のパルスを印加すると輝度は同図b,c
に示すようにBのレベルにある。ここでV,は発光閥値
電圧VthとするとV,ZVthである。これに書き込
み電圧V2を印加すると輝度は一挙に&まで上昇し、以
後電圧値を再び維持電圧V,に戻しても輝度はB,より
大きいB2に落着く。これに消去電圧V3を印加すると
輝度レベルは急激に減少し、再び維持電圧y,まで戻す
と輝度はBに落着く。これら時間的な関係は第2図aに
附された記号t.・ら・・・ら,が同図cの各同じ記号
の位置に対応させることにより示されている。この履歴
現象は第2図bの細線で示された如く、書込み電圧の振
幅やパルス幅(図示せず)に応じて任意の小ループをと
りうる。即ち中間調の表示も可能である。一度書込み電
圧を与えると、その後維持パルスによってそれぞれ与え
られた階調を失わずに発光し続けるのがELPの他の表
示素子に無い大きな特徴である。上記の各電圧は組成や
膜厚及び印加波形により大分異なるが、因みに試作例で
はV比=200V,V,=210V,V2=210〜2
80V,V3=190Vである。ELPは上記のように
パルス振幅によって書込み、消去が行える他にパルス幅
、パルス数によっても書込み及び消去を行うことができ
る。
To explain this characteristic according to Fig. 2, when a pulse with a voltage amplitude of V is first applied as shown in Fig. 2 a, the luminance increases as shown in Fig. 2 b and c.
It is at level B as shown in . Here, V is V, ZVth, where Vth is the luminous threshold voltage Vth. When the write voltage V2 is applied to this, the brightness increases all at once to &, and even after the voltage value is returned to the sustaining voltage V, the brightness settles to B, which is larger than B2. When the erase voltage V3 is applied to this, the brightness level decreases rapidly, and when it is returned to the sustaining voltage y, the brightness settles to B. These temporal relationships are indicated by the symbol t.・Ra...Ra, are shown by corresponding to the positions of the same symbols in Figure c. This hysteresis phenomenon can take any small loop depending on the amplitude and pulse width (not shown) of the write voltage, as shown by the thin line in FIG. 2b. That is, it is also possible to display halftones. A major feature of the ELP, which other display elements do not have, is that once a write voltage is applied, the ELP continues to emit light without losing the gradation given by the sustain pulse. The above voltages vary greatly depending on the composition, film thickness, and applied waveform, but in the prototype example, V ratio = 200V, V, = 210V, V2 = 210 ~ 2
80V, V3=190V. In ELP, writing and erasing can be performed not only by the pulse amplitude as described above, but also by the pulse width and number of pulses.

更には光による書込み、消去も可能である。次に振幅一
定でパルス幅による書込み、消去について第3図a,b
を用いて説明する。
Furthermore, writing and erasing using light is also possible. Next, regarding writing and erasing using pulse width with constant amplitude, Figure 3 a and b
Explain using.

パルス幅−輝度特性にも第3図aに示すようなヒステリ
シス現象がある。
There is also a hysteresis phenomenon in the pulse width-luminance characteristics as shown in FIG. 3a.

即ち、第3図bに示すように時鷹動2,までの維持パル
スPsの印加状態では薄膜EL素子の発光輝度はBs2
である。次にパルス幅の大きい書込みパルスPwが時間
t欧で加えると、高輝度発光し、次の時間ら3で加えら
れる維持パルスPsのとき発光輝度はBw2に転移する
。輝度Bw2での発光は適当な周期で印加される維持パ
ルスPsがある限り持続する(書込みメモリー状態)、
その後時間らでパルス幅の狭い消去パルスPeを加え、
時間t25で再び維持パルスPsに戻すと発光輝度はB
e2またはBe2近くに転移し、この状態は維持パルス
によって接続される(消去メモリー状態)。この履歴現
象はパルス幅の大きさにより変化し、中間調の表示を行
うことが可能である。以上述べたように、パルスの振幅
及びパルス幅の値を書込み時と消去時に変調することに
よって書込み消去することができる。
That is, as shown in FIG. 3b, in the application state of the sustaining pulse Ps up to the time oscillation 2, the luminance of the thin film EL element is Bs2.
It is. Next, when a write pulse Pw with a large pulse width is applied at time t, high-intensity light is emitted, and when a sustain pulse Ps is applied at the next time, time 3, the emission brightness shifts to Bw2. The light emission at the brightness Bw2 continues as long as there is a sustain pulse Ps applied at an appropriate cycle (write memory state).
After that, an erase pulse Pe with a narrow pulse width is added for a certain period of time,
When the sustain pulse Ps is returned again at time t25, the luminance becomes B.
It transitions to near e2 or Be2, and this state is connected by a sustain pulse (erased memory state). This hysteresis phenomenon changes depending on the magnitude of the pulse width, and it is possible to display halftones. As described above, writing and erasing can be performed by modulating the values of the pulse amplitude and pulse width during writing and erasing.

これは次の理由によるものと考えられる。即ち、書き込
み手段として印加された電界を除去してもZnS・Mn
層と誘電体膜の界面近傍に掃引された伝導電子は界面近
傍の界面準位に補獲されており次の維持パルス印加によ
って界面準位より伝導帯に抜け出しZnS:Nh層を走
行して他方の界面に達する。その際ZnS・Mn層中の
もとの電子トラップ近傍を通過する伝導電子に対しては
もとのトラップ準位に再トラップされる確率よりも他方
の界面に掃引される確率の方が高い。これは維持パルス
による電界によって伝導電子が高速度となっているため
である。このため発光輝度は元の状態に戻らずメモリー
現象を呈することとなる。次に消去電圧を印加すると電
子トラップ準位近傍を通過する伝導電子の橋引速度が低
くなり、印放電界によって他方の界面に線引される確率
よりもZnS:Mn層中のもとの電子トラッブ準位に再
トラップされる確率が高くなる。従ってメモリー消去が
行なわれることになる。ところで、上記パルス振幅によ
る書込み、消去は輝度、コントラスト比を容易に大きく
とれる長所をもつが、電源数、トランジスタ等の回路要
素を多く必要とする短所がある。
This is considered to be due to the following reasons. That is, even if the electric field applied as a writing means is removed, ZnS/Mn
The conduction electrons swept near the interface between the layer and the dielectric film are captured by the interface state near the interface, and when the next sustain pulse is applied, they escape from the interface state to the conduction band and travel through the ZnS:Nh layer to the other side. reaches the interface. At this time, for conduction electrons passing near the original electron trap in the ZnS/Mn layer, the probability of being swept to the other interface is higher than the probability of being re-trapped to the original trap level. This is because the conduction electrons have a high velocity due to the electric field caused by the sustain pulse. For this reason, the luminance does not return to its original state and exhibits a memory phenomenon. Next, when an erase voltage is applied, the bridging speed of conduction electrons passing near the electron trap level becomes lower, and the probability that the original electrons in the ZnS:Mn layer are drawn to the other interface by the applied discharge field is lower. The probability of being re-trapped at the trap level increases. Therefore, memory erasure will be performed. Incidentally, writing and erasing using the pulse amplitude has the advantage of easily increasing brightness and contrast ratio, but has the disadvantage of requiring a large number of power supplies and circuit elements such as transistors.

一方パルス幅による書込み、消去は電源数、回路要素等
が少なくて済むという長所をもつが、マトリックス表示
による絵素数が多い場合には、トランジスタや薄膜EL
素子の電極の線抵抗のバラツキ等の影響を受けやすく調
整が困難であるという短所を持つ。本発明は以上のよう
な点に鑑みて両者を折衷して振幅変調とパルス幅変調を
同時に用い書込み及び消去を行うものである。例えば第
1の実施例では振幅変調によって書込みを行い、パルス
幅変調によって消去を行う。また第2実施例ではパルス
幅変調によって書込みを行い、振幅変調によって消去を
行う。本発明の一実施例として振幅変調によって書込み
、パルス幅変調によって消去する方式について以下に図
面とともに説明する。
On the other hand, writing and erasing using pulse width has the advantage of requiring fewer power supplies and fewer circuit elements, but when the number of picture elements in a matrix display is large, transistors and thin film EL
It has the disadvantage that it is easily affected by variations in the wire resistance of the electrodes of the element and is difficult to adjust. In view of the above points, the present invention is a compromise between the two and uses amplitude modulation and pulse width modulation simultaneously to perform writing and erasing. For example, in the first embodiment, writing is performed by amplitude modulation and erasing is performed by pulse width modulation. Further, in the second embodiment, writing is performed by pulse width modulation, and erasing is performed by amplitude modulation. As an embodiment of the present invention, a method of writing by amplitude modulation and erasing by pulse width modulation will be described below with reference to the drawings.

第4図に示すように時間t3,まで電圧が230V,パ
ルス幅が250仏secの維持パルスPsの印加状態か
ら、時間歌32の維持パルスより大きい良。
As shown in FIG. 4, from the application state of the sustain pulse Ps with a voltage of 230 V and a pulse width of 250 seconds until time t3, the voltage is greater than the sustain pulse of time song 32.

ち電圧が280Vの振幅を持つ書込みパルスPwの印加
後、再び時間t33まで維持パルスPsを印加する。次
に時間t34でパルス幅のみを狭くした、即ち電圧が2
30V,パルス幅が20〃secの消去パルスPeを印
加して消去し、これを維持パルスによって時間t35以
後も持続する。振幅変調によって書込まれたものをパル
ス幅変調によって消去できることを第5図に示す。
After applying the write pulse Pw having an amplitude of 280 V, the sustain pulse Ps is applied again until time t33. Next, at time t34, only the pulse width was narrowed, that is, the voltage was 2
Erasing is performed by applying an erasing pulse Pe of 30 V and a pulse width of 20 seconds, and this is continued after time t35 by a sustain pulse. FIG. 5 shows that what was written by amplitude modulation can be erased by pulse width modulation.

第5図の機軸は電圧、縦軸は輝度を表わし、図中の実線
はパルス幅が250山secの場合、点線はパルス幅が
50仏secの場合、一点鎖線はパルス幅が20仏se
cの場合を示す。この図から分るように、A点の書込み
輝度はパルス幅が20一secのとき消去電圧が170
V以上でも輝度は低くなり消去状態になる。しかし50
一Sec,250rsecのパルスでは200V前後で
消去輝度になり再び230Vでは書込み輝度近くで発光
し、消去状態にすることができない。上記実施例とは逆
にパルス幅を大きくした書込みパルスによって書込み、
振幅を小さくした消去パルスによって消去できることも
我々は実験によって確認している以上のように本発明は
電源数は2個で済み、トランジスタ等の回路数が少なく
なり、またパルス幅の調整も2種類だけであるので簡単
になる。
In Figure 5, the axis represents voltage, and the vertical axis represents brightness.The solid line in the figure represents a pulse width of 250 msec, the dotted line represents a pulse width of 50 msec, and the dashed line represents a pulse width of 20 msec.
The case of c is shown. As can be seen from this figure, when the pulse width is 20 seconds, the write brightness at point A is 170 seconds, and the erase voltage is 170 seconds.
Even if the voltage exceeds V, the brightness becomes low and the erased state is reached. But 50
With a pulse of 1 sec, 250 rsec, the erase brightness is reached at around 200 V, and again at 230 V, light is emitted near the write brightness, and the erased state cannot be achieved. Contrary to the above embodiment, writing is performed using a write pulse with a larger pulse width.
We have also confirmed through experiments that erasing can be done by using an erasing pulse with a reduced amplitude.As mentioned above, the present invention requires only two power supplies, reduces the number of circuits such as transistors, and has two types of pulse width adjustment. It becomes easy because it is only

【図面の簡単な説明】[Brief explanation of drawings]

第1図aは三層構造薄膜EL素子の一部切教斜視図、第
1図bは同素子の側面図、第2図aは印加電圧波形図、
第2図bは電圧対発光輝度特性、第2図cは発光輝度変
化を示す図、第3図aはパルス幅変化に対する発光輝度
特性図、第3図bはパルス幅変調のパルス波形図、第4
図は本発明の一実施例による印加パルス波の波形図、第
5図は本発明の上記実施例による消去特性図を示し、横
軸は電圧、縦軸は発光輝度を表わす。 Psは維持パルス、Pwは書込みパルス、Peは消去パ
ルス。 第1図 第2図 第3図 第4図 第5図
FIG. 1a is a partially cutaway perspective view of a three-layer thin film EL device, FIG. 1b is a side view of the device, and FIG. 2a is an applied voltage waveform diagram.
Fig. 2b is a voltage vs. luminance luminance characteristic, Fig. 2c is a diagram showing luminance luminance changes, Fig. 3a is a luminance luminance characteristic diagram with respect to pulse width changes, Fig. 3b is a pulse waveform diagram of pulse width modulation, Fourth
The figure shows a waveform diagram of an applied pulse wave according to an embodiment of the present invention, and FIG. 5 shows an erasure characteristic diagram according to the above embodiment of the present invention, where the horizontal axis represents voltage and the vertical axis represents luminance. Ps is a sustain pulse, Pw is a write pulse, and Pe is an erase pulse. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】 1 電極間に薄膜誘電層によって挟持される薄膜EL層
を有し、ヒステリシス現象を呈する薄膜EL素子の駆動
方法において、所定電圧値以上の範囲で上記ヒステリシ
ス特性のループにおける振幅増加時の最小発光輝度と振
幅減少時の最大発光輝度との差が充分大きく、かつ所定
パルス幅以下の範囲で上記ヒステリシス特性のループに
おけるパルス幅減少時の最大発光輝度のパルス幅増加時
の最小発光輝度との差が充分大きい、振幅およびパルス
幅を選んで維持パルス列とし、書込みはパルス幅を同じ
くして上記維持パルスより振幅の大きい書込みパルスで
行ない、消去は振幅を同じくして上記維持パルスよりパ
ルス幅の短かい消去パルスで行なうことを特徴とする薄
膜EL素子の駆動方法。 2 電極間に薄膜誘電層によって挟持される薄膜EL層
を有し、ヒステリシス現象を呈する薄膜EL素子の駆動
方法において、所定パルス幅以上の範囲で上記ヒステリ
シス特性のループにおけるパルス幅増加時の最小発光輝
度とパルス幅減少時の最大発光輝度との差が充分大きく
、かつ所定電圧値以下の振幅の範囲で上記ヒステリシス
特性のループにおける振幅減少時の最大発光輝度と振幅
増加時の最小発光輝度との差が充分大きい、パルス幅お
よび振幅を選んで維持パルス列とし、書込みは電圧値を
同じくして上記維持パルスよりパルス幅の長い書込みパ
ルスで行ない、消去はパルス幅を同じくして上記維持パ
ルスより振幅の小さい消去パルスで行なうことを特徴と
する薄膜EL素子の駆動方法。
[Claims] 1. In a method for driving a thin film EL element having a thin film EL layer sandwiched between electrodes by a thin film dielectric layer and exhibiting a hysteresis phenomenon, the amplitude in the loop of the hysteresis characteristic in a range of a predetermined voltage value or higher is provided. If the difference between the minimum luminance when the amplitude increases and the maximum luminance when the amplitude decreases is sufficiently large and is within the predetermined pulse width, the maximum luminance when the pulse width decreases in the loop with the above hysteresis characteristic is the minimum when the pulse width increases. A sustain pulse train is selected by selecting an amplitude and a pulse width that have a sufficiently large difference from the emission brightness. Writing is performed using a write pulse with the same pulse width and a larger amplitude than the above sustain pulse, and erasing is performed using the above sustain pulse with the same amplitude. A method for driving a thin film EL element characterized by using an erase pulse with a shorter pulse width. 2. In a method for driving a thin film EL element having a thin film EL layer sandwiched between electrodes by a thin film dielectric layer and exhibiting a hysteresis phenomenon, the minimum light emission when the pulse width increases in the loop of the hysteresis characteristic in a range of a predetermined pulse width or more. The difference between the maximum luminance when the amplitude decreases and the minimum luminance when the amplitude increases in the loop with the hysteresis characteristic is within the range where the difference between the luminance and the maximum luminance when the pulse width decreases is sufficiently large and the amplitude is less than the predetermined voltage value. A sustain pulse train is selected with a pulse width and amplitude that have a sufficiently large difference.Writing is performed using a write pulse with the same voltage value and a pulse width longer than the above sustain pulse, and erasing is performed using a write pulse with the same voltage value and a pulse width longer than the above sustain pulse. A method for driving a thin film EL element, characterized in that the method is performed using a small erasing pulse.
JP52073522A 1977-06-20 1977-06-20 Driving method of thin film EL element Expired JPS6010629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52073522A JPS6010629B2 (en) 1977-06-20 1977-06-20 Driving method of thin film EL element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52073522A JPS6010629B2 (en) 1977-06-20 1977-06-20 Driving method of thin film EL element

Publications (2)

Publication Number Publication Date
JPS5412227A JPS5412227A (en) 1979-01-29
JPS6010629B2 true JPS6010629B2 (en) 1985-03-19

Family

ID=13520644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52073522A Expired JPS6010629B2 (en) 1977-06-20 1977-06-20 Driving method of thin film EL element

Country Status (1)

Country Link
JP (1) JPS6010629B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100327375B1 (en) * 2000-03-06 2002-03-06 구자홍 apparatus for active driver

Also Published As

Publication number Publication date
JPS5412227A (en) 1979-01-29

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