JPS624913Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention provides a device for counting the number of songs on a tape recorder, a device for finding the beginning of a song, etc.
It is characterized by accurately and automatically switching the circuit time constant used to detect no-signal recording parts for each mode of normal playback (play), fast-forward playback (queue), and rewind playback (review). This is related to the circuit layout.

Conventional no-signal recording part detection circuits detect noise for a relatively long period of time (approximately 10 ^msec to 1 ^sec ) (magnetic recording tapes are susceptible to noise caused by switching noise of the recorder or dust when recording from a record). However, the present invention uses a timer and a latch circuit in combination to separate the no-signal recording part and the signal recording part. This provides a circuit that switches the rise time constant of the detection circuit to prevent malfunction due to relatively long noise.

Next, embodiments of the present invention will be described with reference to the drawings. Fig. 1 shows a block diagram of a no-signal recording portion detection circuit according to the present invention, Fig. 2 shows a circuit diagram showing an embodiment of the invention, and Fig. 3 shows a circuit diagram of an embodiment of the invention. FIG. 3 is a diagram showing time charts of input/output characteristics for various operation modes. In addition, the number of each element in the circuit diagram of Fig. 2 is
Corresponds to the block number in the figure.

The output terminal of the amplification/detection circuit 114 for the reproduced signal applied to the reproduced signal input terminal 101 is connected to the input terminals I and O of the AND circuit elements 1 and 2, which are the first gate circuits of the time constant selection circuit 120. The play signal input terminal 102 is connected to the input terminal A of the circuit element 1, and the play signal input terminal 102 is connected to the input terminal A of the circuit element 1.
A queue signal input terminal 103 and a review signal input terminal 104 are connected to the 11 input terminals M and M, respectively, and the output terminal Y is connected to the input terminal E of the AND circuit element 2. Output terminals C and F are the charging/discharging time constant 1 of the time constant selection circuit 120.
15 and 116, it is connected to input terminals S and C of a circuit element 17, which is a third OR circuit constituting the time constant selection circuit 120. The charge/discharge time constant circuit 115 includes a resistor 9, an element in which a diode 7 and a resistor 8 are connected in series, an AND circuit element 3 which is a second gate circuit, and a portion between its input terminal K and output terminal K. It is constructed by connecting an element in which a resistor 5 and a diode 6 are connected in series in parallel, and the output terminal of the circuit is grounded via a capacitor 15, and at the same time the input terminal of the circuit element 17 is connected to the ground. It is connected. Further, the charge/discharge time constant circuit 116 includes a resistor 10, a diode 11, and a resistor 1.
2 are connected in series, an AND circuit element 4 which is a second gate circuit, a part between its input terminal A and output terminal A, a resistor 13 and a diode 14 are connected in series. They are connected in parallel, and the output terminal of the circuit is grounded via a capacitor 16 and at the same time connected to the input terminal of the circuit element 17. The output terminal of the circuit element 17 is a Schmitt circuit 109.
It is connected to the. The Schmitts circuit 109 consists of an input resistor 26, amplifiers 27 and 28 connected in series, and a circuit connected in series with a feedback resistor 29 connected to its input/output terminal, and one of its output terminals is a latch. The polarity of the output of the circuit 110 is connected to the input terminal N of the AND circuit element 22, and the other circuit element 30 is a fourth OR circuit.
is connected to the input terminal YO. The stop signal input terminal 105 and the pause signal input terminal 106 are connected to the input terminals T and H of the circuit element 112 which is a second OR circuit whose output polarity is inverted, and the output terminal T is connected to the AND terminal of the timer circuit 113. circuit element 2
The input terminal T of 1 is connected via a resistor 19 to an input terminal G connected to a capacitor 20 whose other end is grounded, and its output terminal N is connected to an AND circuit element 22 with the polarity of the output of the latch circuit 110 inverted. , 23 input terminals D and C.

The input and output terminals of the circuit elements 22 and 23 and the OR circuit elements 24 and 25 whose input polarities are inverted are connected to operate as a latch circuit, and have an initial setting circuit 31 whose output terminal H is connected to the circuit. The input terminals of elements 3 and 4 and the circuit element 30
The input terminal Y is connected to the input terminal Y, and the output terminal L is connected to the output terminal 107.

Next, various operation modes will be explained. If the play operation is currently being performed and the operation mode is constant [ ], the input voltage of the play signal input terminal 102 becomes high level, and the time constant selection circuit 120
is applied to the input terminal A of the AND circuit element 1.

Also, since the stop signal input terminal 105 and the pause signal input terminal 106 are at low level, the output terminal 2 of the circuit element 112 is at high level, and the input terminals T and T of the circuit element 21 of the timer circuit 113 are at high level. So, the circuit element 21
Since the output terminal N of the latch circuit 110 and the input terminals N and C of the circuit elements 22 and 23 of the latch circuit 110 are also at a high level, the output terminal H of the latch circuit 110 has the output of the Schmitt circuit 109 in the state of the input terminal N. appears at a low level, and as a result, the input terminals K and S of each of the circuit elements 3 and 4 of the charge/discharge time constant circuits 115 and 116 become at a low level.

Here, when the reproduced signal shown in A of FIG. 3 is applied to the reproduced signal input terminal 101, the amplification and detection circuit 11
4, the waveform is amplified, detected, and waveform shaped as shown in Figure B, and is input to the input terminal A of the circuit element 1 of the time constant selection circuit 120. At the point where the signal recording section changes to the signal recording section, the output terminal C of the circuit element 1 changes from a low level to a high level, and is applied to the input terminal C of the circuit element 3 of the charge/discharge time constant circuit 115. The low level state of the output terminal H of the latch circuit 110 is applied to the input terminal K of the circuit element 3, and as a result, the output terminal K becomes low level, and the diode 6 is turned off. Further, the diode 7 is in an OFF operation because the output terminal U of the circuit element 1 is at a high level. Therefore, as shown in Figure D, the (charging) time constant _t1 set by the resistor 9 and capacitor 15 determines the attack time, that is, the rise time constant, but after this time _t1 , the output of the charge/discharge time constant circuit 115 goes from low level to high level.

Also, in Figure E, at the point where the signal recording portion changes from point b or d in Figure B to a no-signal recording portion, the output terminal U of the circuit element 1 goes from high level to low level.
The diode 7 of the charge/discharge time constant circuit 115 turns on, and as a result, the (discharge) time constant t ₂ set by the parallel connection of the resistors 8 and 9 and the capacitor 15 as shown in diagram F is A recovery time is determined, and after this time _t2 , the output of the charge/discharge time constant circuit 115 changes from high level to low level.

Next, if the operation mode is constant [ ], not during the above-mentioned play operation but during cue or review operation where the tape speed has changed, the cue signal input terminal 1
03 or review signal input terminal 104 becomes high level and is applied to the input terminal M or M of the circuit element 111, the output terminal Y becomes high level and the voltage of the circuit element 2 of the time constant selection circuit 120 becomes high. Applied to input terminal E.

Here, when the reproduced signal shown in figure A of FIG. The signal is input to terminal O, but as with the play operation in case [ ] above, the point where the no-signal recording part changes from point a or c in diagram B to the signal recording part in diagram C is as shown in diagram D. After the (charging) time constant _t3 determined by the resistor 10 and capacitor 16 of the charge/discharge time constant circuit 116, the output of the charge/discharge time constant circuit 116 changes from low level to high level.

Also, in Figure E, at the point where the signal recording portion changes from point b or d in Figure B to a no-signal recording portion, the resistors 10 and 12 of the charge/discharge time constant circuit 116 are connected as shown in Figure F.
After the (discharge) time constant t ₄ determined by the parallel connection of and the capacitor 16, the charge/discharge time constant circuit 116
The output changes from high level to low level.

The outputs of the charge/discharge time constant circuits 115 and 116 are input to the input terminals S and S of the circuit element 17, and appear at the output terminal S of the circuit element 17.
The waveform is shaped at step 09 and applied to the input terminal y of the OR circuit element 30, and appears at the output terminal 107 of the no-signal recording portion detection circuit via its output terminal y.

Incidentally, the time constant t ₁ is set to a long time so as to prevent malfunction due to noise having a long time of several hundreds of ^milliseconds .

Next, the case of the operation mode [ ] in which a stop or pause operation is inserted during a play, review, or queue operation and in the middle of a signal recording portion will be explained.

Considering the case where a stop or pause operation is inserted at points a to b or points c to d in figure B, corresponding to points e to f in figure G, the stop signal input terminal 105 or pause operation is inserted at point e in figure G. Signal input terminal 1
06 changes from low level to high level and is applied to the input terminal T or H of the circuit element 112, and the low level signal appearing at the output terminal T is applied to the input terminal T of the circuit element 21 of the timer circuit 113. The signal is applied to the output terminal N, and is applied to the input terminals D and C of the latch circuit 110.
As a result, the output terminal H of the latch circuit 110 maintains the state of the input terminal N because the input terminals D and C are at the low level, so the output terminal H remains at the high level. , input terminal keys of the circuit elements of the charge/discharge time constant circuits 115 and 116,
is applied to the That is, the output terminal 107
Also in the no-signal recording part of Figure H, the circuit element 3
0 input terminal Y via output terminal A.
A level voltage will be applied. However, G
Since the reproduced signal disappears from point e in the figure, the output terminals C, C, C, and C of the circuit elements 1, 2, 3, and 4 become low level, and the outputs of the time constant circuits 115 and 116 (the output of the Schmitt circuit 109). is the (discharge) time constant t ₂ as shown in diagram H, as in the case of operation mode [ ].
Or it goes from high level to low level after _t4 .

Next, when the stop or pause operation is canceled at a point corresponding to point f in Figure G, the stop signal input terminal 105 or the pause signal input terminal 106 changes from high level to low level, and the input terminal of the circuit element 112 It is applied to the input terminal T or T of the circuit element 21 of the timer circuit 113, and is converted from a low level to a high level and appears at its output terminal T, and is applied to the input terminal T of the circuit element 21 of the timer circuit 113. _H
In the figure, at a point corresponding to point h in Figure G, the output terminal N of the circuit element 21 becomes high level, and the voltage is applied to the input terminals N and C of the latch circuit 110, so that the output terminal H is applied to the output terminal H. A low level state of the Schmitt circuit 109 applied to the input terminal N appears.

Therefore, the delay time corresponding to points f to g in diagram G
After t ₈ , tape feeding starts and playback signal input terminal 10
As a result, a high level state is applied to the input terminals I and O of the circuit elements 1 and 2 of the time constant selection circuit 120. Since the output terminal H of the latch circuit 110 is at a high level up to the point corresponding to the point h in the diagram G, the input terminals K and S of the circuit elements 3 and 4 of the charge/discharge time constant circuits 115 and 116 are at a high level. In the case of play operation, the (charging) time constant t is determined by the parallel connection of resistors 5 and 9 and the capacitor 15 for the same reason as the operation mode in [] ₆ or in the case of queue and review operation, the resistor 10 and 13 in parallel and a (charging) time constant t ₇ determined by the capacitor 16. Here, the time constant _t5 is set so as not to delete the no-signal recording portion. Therefore t ₆ , t ₇ , t ₈
and t ₅ are set in the following relationship: t ₆ + t ₈ < t ₅ , t ₇ + t ₈ < t ₅ .

Also, play after canceling the stop or pause operation,
When the no-signal recording section changes to the signal recording section during the queue or review operation, the playback signal is input to the playback signal input terminal 101 at point i in the figure, which corresponds to point a or c in figure B. When the voltage is applied, the output terminal 107 changes from low level to high level after the (charging) time constant t ₁ or t ₃ as shown in diagram J, as in the case of the operation mode [ ].

As explained above, the present invention incorporates a timer circuit and a latch circuit in addition to the logic circuit and time constant circuit in a device that detects a no-signal recording portion and a signal recording portion, such as a device that locates the beginning of a song on a tape recorder. When used together, it not only switches to a time constant suitable for the same operation mode during play, queue, or review operations, but also cancels the stop or pause operation in the case of an operation mode in which a stop or pause operation is inserted. At this point, the state of the reproduced signal is held for the delay time determined by the timer circuit to compensate for the delay in the rise time of the mechanical operation, and the time constant circuit is switched by the operation of the latch circuit to compensate for the delay in the rise time of the mechanical operation. The delay time of the time constant circuit whose rise time is faster than that in the same operation mode is compensated, and when the state changes from the no-signal recording part to the signal recording part after the stop or pause operation is canceled, the rise time of the time constant circuit is This is slower than in the case of the above-mentioned operation mode, and is allowed to pass while preventing malfunctions due to noise having a relatively long time (approximately 100 ^msec to 1 ^sec ).

Here, in the counter or microprocessor, etc. to which the output of the no-signal recording portion detection circuit is connected, once the output goes to high level, the counter or microprocessor, etc. goes to low level. are waiting. Therefore, when changing from a stop or pause operating state to a play, queue, or review operation, if there is a delay in the output becoming high level, it will be assumed that the output has gone to low level and a malfunction will occur. In other words, the above-mentioned malfunction can be prevented.

[Brief explanation of the drawing]

Fig. 1 shows a block diagram of an embodiment of the present invention, Fig. 2 shows an example of a circuit diagram, and Fig. 3 shows a time chart of input/output characteristics for various operating modes of the embodiment. FIG. 101...Reproduction signal input terminal, 102...Play signal input terminal, 103...Queue signal input terminal, 104...Review signal input terminal, 105...
... Stop signal input terminal, 106 ... Pause signal input terminal, 107 ... Output terminal, 120 ... Time constant selection circuit, 109 ... Schmitt circuit, 110
... Latch circuit, 111 ... First OR circuit,
112...Second OR circuit, 17...Third OR circuit, 30...Fourth OR circuit, 113...
...Timer circuit, 114...Amplification detection circuit, 11
5,116...time constant circuit, 1,2...first gate circuit, 3,4...second gate circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] In a device that detects the non-signal recording portion and the signal recording portion recorded on a tape and counts the number of songs or a device that locates the beginning of a song, a reproduction signal applied to the input terminal. an amplification/detection circuit that amplifies, detects, and shapes the waveform of the reproduced signal; and a first circuit that passes together the signal from the cue signal input terminal that is input during fast forwarding and the signal from the review signal input terminal that is input during rewinding. a second OR circuit that passes together the signals applied to the stop signal input terminal and the pause signal input terminal; and a resistor and a capacitor for the output signal of the second OR circuit. a timer circuit that provides a predetermined delay time using a constant circuit; a latch circuit in which one of the input terminals of the pair is connected to the output terminal of the timer circuit to control the output state thereof; a first gate to which an output signal of the amplification and detection circuit is applied to an input terminal, and a signal from a play signal input terminal and an output signal of the first OR circuit to each other input terminal; a second gate circuit, each of which has one input terminal applied with the output signal of the latch circuit, and each other input terminal applied with each output signal of the first gate circuit; , a time constant circuit that sets a predetermined charging/discharging time constant using a resistor and a capacitor combined with a diode that is switched depending on the state of each output terminal of the first and second gate circuits;
a time constant selection circuit having a third OR circuit for synthesizing the outputs of the time constant circuit; a Schmitt circuit for waveform shaping the output of the time constant selection circuit; and the other of the pair of input terminals of the latch circuit. and a fourth OR circuit that combines the output signal of the Schmitt circuit and the output signal of the latch circuit applied to the output terminal and supplies the combined output to the output terminal, and performs normal playback, fast-forward playback, and rewinding. For any of the same operation modes of playback, the playback signal is passed through with a time constant determined by the time constant circuit suitable for each mode, and the playback signal is passed during normal playback, fast-forward playback, and rewind playback. When a stop or pause operation is inserted, a timer circuit and a latch circuit operate in addition to the circuits that operated in the same operation mode, so that the stop or pause operation is applied to the output terminal even during the stop or pause operation. By holding the state of the reproduced signal portion immediately before the transition to the stop or pause operation, and by holding the state of the reproduced signal for a delay time determined by the timer circuit at the time when the stop or pause operation is canceled, the rise of the mechanical operation is A tape recorder characterized in that the time delay is compensated for, and the delay time of the time constant circuit whose rise time is faster than that in the same operation mode is compensated for by switching the time constant circuit by the operation of the latch circuit. No-signal recording portion detection circuit.