JPS6248898B2 - - Google Patents
Info
- Publication number
- JPS6248898B2 JPS6248898B2 JP818381A JP818381A JPS6248898B2 JP S6248898 B2 JPS6248898 B2 JP S6248898B2 JP 818381 A JP818381 A JP 818381A JP 818381 A JP818381 A JP 818381A JP S6248898 B2 JPS6248898 B2 JP S6248898B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- metal film
- insulating film
- growth
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 24
- 238000010894 electron beam technology Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000001678 irradiating effect Effects 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 239000010410 layer Substances 0.000 description 11
- 239000004020 conductor Substances 0.000 description 8
- 230000010354 integration Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法、特に多層金
属膜を有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a multilayer metal film.
一般に多層配線構造は知られているが、第１層
配線と第２層配線を接続する接続導体は従来、層
間絶縁物に形成された開口（スルーホール）にメ
ツキまたは蒸着にて金属を積上げて形成していた
ため、開口内に金属が完全かつ高密度には満たさ
れず、接続導体の導電性が低下し、半導体装置の
電気的特性を悪化させる一因となつていた。 Multilayer wiring structures are generally known, but the connection conductor that connects the first layer wiring and the second layer wiring has conventionally been made by stacking metal by plating or vapor deposition in an opening (through hole) formed in an interlayer insulator. As a result, the openings were not completely filled with metal at a high density, resulting in a decrease in the conductivity of the connecting conductor, which was a factor in deteriorating the electrical characteristics of the semiconductor device.
また、半導体装置の集積度は益々増大する傾向
があり、ダイナミツクRAMを例にとつても1Mビ
ツトから10Mビツトが要求されることは必至であ
る。斯る高集積度になると平面的、即ち二次元的
な集積が限界に達するため三次元的集積構造が考
えられ、この場合、第１層集積回路と第２層集積
回路とを低抵抗で接続することが要求される。 Furthermore, the degree of integration of semiconductor devices tends to increase more and more, and even in the case of dynamic RAM, it is inevitable that 1M bits to 10M bits will be required. At such a high degree of integration, planar, or two-dimensional, integration reaches its limit, so a three-dimensional integrated structure is considered, and in this case, the first layer integrated circuit and the second layer integrated circuit are connected with low resistance. required to do so.
この発明は多層配線または多層集積回路を有す
る半導体装置に於て、配線間または集積回路間を
接続する導電性が良好な接続導体を形成すること
を目的とするものである。 An object of the present invention is to form a connection conductor having good conductivity between interconnects or integrated circuits in a semiconductor device having multilayer interconnects or multilayer integrated circuits.
この発明は第１の金属膜の上に層間絶縁膜を形
成し、この絶縁膜にスルホールとなる開口を形成
して上記金属膜に露出部を形成し、上記露出部に
レーザビームまたは電子ビームを照射して上記露
出部上の開口内に金属を成長させ接続導体となる
成長突起を形成するようにしたものであり、開口
内に高密度且つ完全に満たされた金属を形成し
得、導電性良好な接続導体を得ることができるも
のである。 In this invention, an interlayer insulating film is formed on a first metal film, an opening serving as a through hole is formed in the insulating film to form an exposed part in the metal film, and a laser beam or an electron beam is applied to the exposed part. The metal is irradiated to grow within the opening above the exposed portion to form a growth protrusion that becomes a connecting conductor, and it is possible to form a high density and completely filled metal in the opening, making it conductive. A good connection conductor can be obtained.
以下、この発明の一実施例について説明する。 An embodiment of the present invention will be described below.
第１図はこの発明を多層配線構造に適用したも
のを示しており、先ず同図ａに示すようにシリコ
ン半導体基板１上に所定形状のパターンを有する
アルミニウム、銅、スズ等の金属からなる第１の
金属膜２を形成する。その上にシリコン窒化膜等
からなる絶縁膜３を形成する。次に図ｂに示すよ
うに写真製版技術によりコンタクトホールとなる
開口４を絶縁膜３に形成して金属膜２に露出部５
を形成する。次に数10〔μＪ〕のエネルギを有し
パルス巾が10〔ms〕程度のレーザビーム６を断
続的に露出部５に照射して金属膜２を加熱（アル
ミニウムの場合300〜400〔℃〕程度に加熱）し、
図ｃに示すように金属膜２の金属を成長して成長
突起７を形成する。上述の条件に於ける成長速度
は10〜数100〔μ／hour〕程度である。この時、
金属膜２の体積は成長突起７が生じる分だけ減少
するが、通常、成長突起７の体積に比べてかなり
大きいため減少率はわずかである。尚、レーザビ
ーム６の代わりに電子ビームを用いてもよい。 FIG. 1 shows the application of the present invention to a multilayer wiring structure. First, as shown in FIG. 1 metal film 2 is formed. An insulating film 3 made of a silicon nitride film or the like is formed thereon. Next, as shown in FIG.
form. Next, the exposed portion 5 is intermittently irradiated with a laser beam 6 having an energy of several 10 μJ and a pulse width of approximately 10 ms to heat the metal film 2 (300 to 400 °C in the case of aluminum). heat to a certain degree),
As shown in FIG. c, the metal of the metal film 2 is grown to form growth protrusions 7. The growth rate under the above conditions is about 10 to several 100 [μ/hour]. At this time,
Although the volume of the metal film 2 is reduced by the amount of the growth protrusion 7, the rate of reduction is small because it is usually considerably larger than the volume of the growth protrusion 7. Note that an electron beam may be used instead of the laser beam 6.
次に、図ｄに示すようにアルミニウム、銅、ス
ズ等からなる第２の金属膜８を蒸着等により形成
する。以上の工程を経て金属膜２，８からなる多
層配線を成長突起７により接続した半導体装置が
製造される。成長突起７は金属膜の溶融状態で成
長するため、金属膜２とのコンタクトは良好であ
り、また開口４内を完全に満たして高密度に生成
するため導電性の良好な接続導体となる。 Next, as shown in FIG. d, a second metal film 8 made of aluminum, copper, tin, etc. is formed by vapor deposition or the like. Through the above steps, a semiconductor device in which multilayer interconnections made of metal films 2 and 8 are connected by growth protrusions 7 is manufactured. Since the growth protrusions 7 grow in a molten state of the metal film, they have good contact with the metal film 2, and since they completely fill the openings 4 and are formed at high density, they serve as connection conductors with good conductivity.
第２図はこの発明を多層集積回路構造に適用し
た例を示す。先ず第１図ａに示すものの絶縁膜３
の上に第２図ａに示すようにシリコンをエピタキ
シヤル成長させアニールして単結晶の半導体層９
を形成し、その上にシリコン窒化物等からなる第
２の絶縁膜１０を形成する。次に図ｂに示すよう
に写真製版技術により各絶縁膜３，１０、半導体
層９にスルーホールとなる開口１１を形成する。
次に半導体層９の開口１１に面した部分をプラズ
マ酸化して絶縁層１２を形成する。次に図ｃに示
すようにレーザビーム６または電子ビームを露出
部５に照射して金属膜２を溶融し成長突起１３を
形成する。次に、図ｄに示すように第２の金属膜
８を蒸着等により形成することにより、半導体基
板１、半導体層９を夫々形成された集積回路の各
配線を接続する接続導体を成長突起１３により形
成する。 FIG. 2 shows an example in which the present invention is applied to a multilayer integrated circuit structure. First, the insulating film 3 shown in FIG.
As shown in FIG. 2a, silicon is epitaxially grown and annealed to form a single crystal semiconductor layer 9.
A second insulating film 10 made of silicon nitride or the like is formed thereon. Next, as shown in FIG. b, openings 11 serving as through holes are formed in each of the insulating films 3 and 10 and the semiconductor layer 9 by photolithography.
Next, a portion of the semiconductor layer 9 facing the opening 11 is plasma oxidized to form an insulating layer 12. Next, as shown in FIG. c, the exposed portion 5 is irradiated with a laser beam 6 or an electron beam to melt the metal film 2 and form a growth protrusion 13. Next, as shown in FIG. d, by forming a second metal film 8 by vapor deposition or the like, a connecting conductor connecting each wiring of the integrated circuit formed on the semiconductor substrate 1 and the semiconductor layer 9 is formed on the growth protrusion 13. Formed by
以上のように、この発明は第１の金属膜に層間
絶縁膜を形成し、この絶縁膜に開口を形成して上
記金属膜に露出部を形成し、この露出部にレーザ
ビームまたは電子ビームを照射して上記金属膜を
成長させるようにしたので、開口に高密度、完全
に満たされた成長突起を形成することができ、こ
の上に形成される第２の金属膜に対する導電性良
好な接続導体を得ることができる。 As described above, the present invention forms an interlayer insulating film in a first metal film, forms an opening in this insulating film to form an exposed part in the metal film, and irradiates the exposed part with a laser beam or an electron beam. Since the metal film is grown by irradiation, it is possible to form growth protrusions with high density and completely filled in the openings, and to have good electrically conductive connection to the second metal film formed on top of the growth protrusions. You can get a conductor.
第１図はこの発明の一実施例を工程順に示す断
面図、第２図はこの発明の他の実施例を工程別に
示す断面図である。
１は半導体基板、２は第１の金属膜、３は第１
の絶縁膜、４，１１は開口、５は露出部、６はレ
ーザビーム、７，１３は成長突起、８は第２の金
属膜、９は半導体層、１０は第２の絶縁膜、１２
は絶縁層を示す。
FIG. 1 is a sectional view showing one embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view showing another embodiment of the invention in each step. 1 is a semiconductor substrate, 2 is a first metal film, 3 is a first
, 4 and 11 are openings, 5 is an exposed portion, 6 is a laser beam, 7 and 13 are growth projections, 8 is a second metal film, 9 is a semiconductor layer, 10 is a second insulating film, 12
indicates an insulating layer.
Claims (1)
金属膜を形成する工程、上記金属膜が形成された
上記半導体基板上に絶縁膜を形成する工程、上記
絶縁膜に開口を形成して上記金属膜に露出部をレ
ーザビームまたは電子ビームを照射して露出部上
に金属を成長させ成長突起を形成する工程、上記
成長突起及び上記絶縁膜上に上記成長突起に接触
して第２の金属膜を形成する工程を含む半導体装
置の製造方法。 ２ 半導体基板の表面上に所定パターンの第１の
金属膜を形成する工程、上記金属膜が形成された
上記半導体基板上に第１の絶縁膜を形成する工
程、上記絶縁膜上に半導体層を形成する工程、上
記半導体層上に第２の絶縁膜を形成する工程、上
記各絶縁膜及び上記半導体層に開口を形成して上
記金属膜にその露出部を形成する工程、上記露出
部にレーザビームまたは電子ビームを照射して上
記露出部上に金属を成長させ成長突起を形成する
工程、上記成長突起及び上記第２の絶縁膜上に上
記成長突起に接触するように第２の金属膜を形成
する工程を含む半導体装置の製造方法。 ３ 開口を形成後、開口に面した半導体層の表面
に絶縁層を形成し、然る後、成長突起を形成する
ことを特徴とする特許請求の範囲第２項記載の半
導体装置の製造方法。[Claims] 1. A step of forming a first metal film in a predetermined pattern on the surface of a semiconductor substrate, a step of forming an insulating film on the semiconductor substrate on which the metal film is formed, and a step of forming an opening in the insulating film. and irradiating the exposed portion of the metal film with a laser beam or electron beam to grow metal on the exposed portion to form a growth protrusion, contacting the growth protrusion on the growth protrusion and the insulating film. A method for manufacturing a semiconductor device, comprising the step of forming a second metal film. 2. A step of forming a first metal film in a predetermined pattern on the surface of a semiconductor substrate, a step of forming a first insulating film on the semiconductor substrate on which the metal film is formed, and a step of forming a semiconductor layer on the insulating film. forming a second insulating film on the semiconductor layer; forming an opening in each of the insulating films and the semiconductor layer to form an exposed portion in the metal film; A step of growing metal on the exposed portion by irradiating a beam or an electron beam to form a growth protrusion, and forming a second metal film on the growth protrusion and the second insulating film so as to be in contact with the growth protrusion. A method for manufacturing a semiconductor device including a step of forming it. 3. The method of manufacturing a semiconductor device according to claim 2, wherein after forming the opening, an insulating layer is formed on the surface of the semiconductor layer facing the opening, and then a growth protrusion is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP818381A JPS57121253A (en) | 1981-01-21 | 1981-01-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP818381A JPS57121253A (en) | 1981-01-21 | 1981-01-21 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57121253A JPS57121253A (en) | 1982-07-28 |
| JPS6248898B2 true JPS6248898B2 (en) | 1987-10-16 |
Family
ID=11686184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP818381A Granted JPS57121253A (en) | 1981-01-21 | 1981-01-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57121253A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054455A (en) * | 1983-09-05 | 1985-03-28 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0612792B2 (en) * | 1987-03-10 | 1994-02-16 | 日本電気株式会社 | Wiring structure of semiconductor device |
-
1981
- 1981-01-21 JP JP818381A patent/JPS57121253A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57121253A (en) | 1982-07-28 |
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