JPS6054455A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To perform a normal connection by providing an insulating film on the side wall of a hole for exposing the connected portion of a lower layer element through an upper layer element by utilizing an anisotropic etching technique, and superposing a wiring metal layer. CONSTITUTION:An insulating film 6 is formed on an upper layer element 2, the connecting portion 4 of a lower layer element 1 is exposed by a normal method on an open portion 10, and the connecting portion 5 of the upper layer element 2 is exposed with an open portion 11. Then, insulating films 13 are formed over the inner walls and the bottoms of the holes 10, 11 from the upper surface of the film 6, the films 13 are allowed to remain only on the inner walls of the holes 10, 11 by reactive ion etching, and holes 14, 15 which are exposed with the portions 4, 5 are formed. Subsequently, wiring metal 16 is covered, a resist mask 17 is covered, a wiring pattern is formed, the mask is removed, and the desired connection is completed. According to this structure, the function of the upper layer element due to the contact of the upper layer with the wiring layer is not failed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a three-dimensional semiconductor integrated circuit device, which has been attracting attention recently, and is formed by stacking a plurality of semiconductor elements with insulating films interposed between the elements. The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for internally connecting elements in different layers.

[Prior art]

When manufacturing semiconductor devices such as those described above, it is essential to make internal connections between upper layer elements and lower layer elements, but an accurate method for this has not yet been developed. In order to explain a possible method, this is a cross-sectional view showing the state at each process step, and as an example of contact between an upper layer, an element, and a lower layer element, a first layer element is connected to the first layer through a first H layer.
] This shows the case of connection with a second layer element that is stacked on top of each other. 1
, (++ is the first N-th element, (2) is the second layer element,
+31 is the first insulating film between the 1st # element + 11 the 2nd layer element (2), (4) and (5) are the 1N element (1), respectively, the 2nd layer element These are the parts that are formed on the top and are to be connected to each other. Based on the above-described structure shown in FIG. 1A, the connecting portion (4
) and 2nd A! In order to connect the connecting portion (5) of the 7th element (2), a second insulating film (6) is formed on the surface of the 2nd N element (2).
) is formed (Fig. 1B), and the connecting portion (4) of the first layer of the photosensitive resin film (7) is formed thereon by ordinary photolithography technology.
An opening (8) on the top and an opening (9) on the connection part (5) of the second layer.
) to form a pattern having a pattern (FIG. 1C), etching is performed using this photosensitive resin film (7) as a mask.
Connect the connecting portion (4) of N to the opening (10) formed thereon.
), and the photosensitive resin film (7) is removed after exposing the connecting portion (6) of the second layer to the opening (11) formed in the - (FIG. 1D).

Thereafter, as shown in FIG. 1E, a wiring metal layer (12) is formed on the second insulating film (6) including the inside of the opening ff1s(+ol, (ui), thereby forming the first layer. The connection part (4) and the connection part (5) of the second layer can be connected.

However, in such a method, as is clear from the figure, the base of the second layer element (2) is exposed on the inner surface of the opening (10) above the connection portion (4) of the first layer. The wiring metal # (+21) is in contact with this base, and the second layer element (2
) may lose its functionality.

[Analysis of the invention C required]

This invention has been made in view of the above points, and uses anisotropic etching technology to form an insulating film that covers the inner surface of the opening formed on the connecting portion of the lower layer element. The present invention provides a method for manufacturing a semiconductor device that enables normal welding by forming a metal layer for wiring.

[Embodiments of the invention]

FIG. 2 is a sectional view showing the state of the scattered dots at each process step according to an embodiment of the present invention. After passing through the opening (1+++) from the upper surface of the second insulating film (6)
, (A third insulating film (+3) is formed over the inner wall surface and bottom surface of the OL (FIG. 2A). Next, an anisotropic etching process in which etching progresses linearly, such as a reactive ion etching method, is performed. The openings (+ol, (
The third insulating film α3) is left only on the inner surface of the ol. As a result, openings 04) and 00 are formed in which the side wall surface is not covered with the third insulating film α3), and the bottom surface is exposed with the first layer connection portion (4) and the second layer connection portion (5), respectively. (Figure 2B). Next, a wiring metal layer (I
φ is formed, and a photosensitive resin film 07) of a desired pattern is formed thereon by ordinary photolithography technology.
), this photosensitive resin film (☆・[oil film 07) is used as a mask to etch the wiring metal layer (1~) and form it into the desired pattern, and then the photosensitive resin film (1η) is removed to form the desired connection. is completed (Fig. 2D).

〔Effect of the invention〕

Based on the above explanation 1-, in this invention, the anisotropic etching technique is used to cover the side wall surface of the opening that penetrates the upper layer element and exposes the connection part of the lower layer element with an insulating film. The connection portion of the lower layer element and the connection portion of the upper layer element can be connected without the wiring metal layer formed through the opening coming into contact with the base of the upper layer element.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the state at each process step to explain a possible manufacturing method using the conventional technology, and FIG. 2 is a cross-sectional view showing the state at each process step of an embodiment of the present invention. FIG. In the figure, (1) is the first layer (lower layer) element, (2) is the second layer (upper layer) element, (3) is the first insulating film, (4) is the connection part of the lower layer element, (5) is the connection part of the upper layer element, (6
) is the second insulating film, (10) is the first opening, (11)
is the second opening, (l(6) is the third insulating film, (16)
is a metal layer for wiring 0 Note that the same reference numerals in the drawings indicate corresponding parts. Agent: Masuo OiwaL Continuation of amendment (spontaneous) January 2211, Showa Tuff, Commissioner of the Japan Patent Office 1, Indication of the case: Patent Application 1982: L64363 No. 2, Title of invention: Method for manufacturing semiconductor devices 3, Amendment 1.1. Address of applicant: 2-112-3g, Marunouchi, 111-ku, Chiyo, Tokyo
Name (601,) Mitsubishi Electric Corporation representative piece 111
Jin8 Department 4, Agent 5, amend Figure 1 6 of the drawing subject to amendment and Figure 1 of the content drawing of the amendment as shown in the attached drawings. 7. One or more drawings showing Figure 1 after the revised list of attached documents 19゛ Kidney

Claims (1)

[Scope of Claims] ill A plurality of semiconductor devices are stacked together with an insulating layer 11 interposed between them. When connecting the connecting portion of the upper layer semiconductor element formed on the element through the first insulating film, in 1-, a second insulating lIφ is formed at -l2 of the two-layer semiconductor element. In the first step, the first and second layers reach the respective connection portions from the surface of the second insulating film “to the soil of the connection portion of the lower layer semiconductor device and the connection portion of the double soil layer semiconductor device”. a second step of forming an opening; a third step of forming a third insulating film covering the upper surface of the second insulating film and the inner surfaces of the @1 and second openings; and a third step of forming the third insulating film. Anisotropy f in the film
1 etching is performed on the second insulating film.
a fourth step of removing the insulating film and simultaneously evaporating the connection parts at the bottoms of the first and second openings, and removing the third insulating film on the top and inner surface of the second insulating film; A method for manufacturing a semiconductor device, characterized in that a fourth step of forming a wiring metal layer in the first and second openings in which the insulating film remains is carried out. (Anisotropic etching in the step of 21M4) 32. The method for manufacturing a semiconductor device JR according to claim 31, characterized in that reactive ion etching is used for the step of etching.