JPS6248881A - Pocketable television receiver - Google Patents

Abstract

PURPOSE:To reduce power consumption by constituting a signal electrode driving circuit with plural LSIs and indicating selectively and in order the plural number of LSIs by a chip enabling means. CONSTITUTION:To a scanning side electrode LSI21e, the data of four bits from an A/D converter and a horizontal and a vertical synchronizing signals from a linear circuit are inputted. The LSI21e generates various kinds of timing pulses, such as a clock pulse, scanning electrode driving signals X1-X60, etc. setting the horizontal and the vertical synchronizing signals as references and also generates four chip enable signals CE1-CE4 respectively at every synchronization having a period of 4H. The LSI21e supplies signals X1-X60 to a liquid crystal panel 181 and selects signal side electrode driving LSI21a-21d in order by the signals CE1-CE4 and gives four bits data and the various kinds of timing pulses. The LSI21a-21d, according to the data and the timing signals, select signal electrode terminals Y1-Y80, Y81-Y160, Y1'-Y80' and Y81'-Y160' on the panel 181 in order, displaying and driving them.

Description

DETAILED DESCRIPTION OF THE INVENTION [Prior art and its problems] In recent years, research has been conducted into portable pocketable television receivers equipped with a four-channel liquid crystal display.

A liquid crystal display panel used in this type of pocketable television receiver has scanning electrodes and signal electrodes arranged in a matrix, and is provided with an LSZ for driving the scanning electrodes and an LSI for driving the signal electrodes in a single body.

The liquid crystal display channel is driven by a known driving method such as a voltage averaging method.

- However, since these portable television receivers are battery-powered, reducing power consumption has become an important issue.

However, liquid crystal displays used in pocket television receivers1? The channel has a large number of display dots, for example 60x320Y dots. Therefore, the scanning electrode driving LSI
The LSI for driving the signal electrode requires a shift register of 60 stages, and the LSI for driving the signal electrode requires a shift register of 320 stages.
The problem is that the power consumption increases because the 0-stage shift register is constantly running at high speed.

[Purpose of the invention] This invention was made in view of the above circumstances.

It is an object of the present invention to reduce power consumption by configuring a signal electrode drive circuit with a plurality of LSIs and sequentially and selectively specifying the plurality of LSIs by a chip enable means.

[Means for solving the problem: For example, as an LSI for driving a 60 x 320 dot liquid crystal display panel, one scan electrode driving LSI for driving 60 scan electrodes and 320 signal electrodes are used. Four signal electrode drive LSIs are provided to drive 80 signal electrodes, and these four signal electrode drive LSIs drive 80 signal electrodes.
are sequentially and selectively designated by a chip enable signal.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the external structure of a liquid crystal television receiver, and numeral 10 in the figure is a receiver case. On the front of this case 10, there is a television image display window J1, a VHF channel display section 12&, a Wm channel display section 12b.
, a sound emitting section 13 is provided. A glass plate 14 is attached to the front surface of the display window 11 and the channel display sections 12m and 12b, and the sound emitting section 13 has a large number of small holes 1 for emitting sound.
5°15 is drilled. Further, on the upper side of the case 1o, there is provided a slide switch operation knob 16 that serves as a power switch and a VHF-UHF changeover switch. There are an external power connection port used when using a DC power source (battery sold as an accessory for this television receiver) and a connection port for an external antenna (for example, an outdoor antenna). Furthermore,
A rod antenna 17 is attached to the upper end of the negative side of the case 1°. This rod antenna 17 has a hinge 1 at its base.
It is rotatably held by the case 8 and is stored in the upper part of the case 10 when not in use.

Next, the internal configuration of the television receiver will be explained.

First, the circuit configuration of the television receiver shown in FIG. 2 will be explained. In this television receiver,
Pinch the circuit board to the antenna board 100° and the board 110. It is divided into a linear board 12o, a power supply circuit board 130, a display drive control circuit board 14o1, and a display drive circuit board 150, and each board ioo to 150 has a circuit described later. In addition to the above boards 100 to 150, a tuner 16o
.

Speaker 170. A? A flannel type double image display device 180 is provided. As the panel type image display device 180, for example, a dot matrix liquid crystal display panel or an electroluminescent display panel is used. In this embodiment, an electroluminescent (EL) panel is provided on the back side of the dot matrix liquid crystal display panel 181 for illumination. The illumination panel 182 is arranged in a @layer arrangement, and the dot matrix liquid crystal display panel 181 is of a double matrix type with a display dot count of 120 x 160, for example, and is driven at a duty of 1/65.6. TN to be
(twisted nematic) type.

The antenna board 100 is connected to a rod antenna 17 provided in the receiver and an external antenna connection jack. The television radio waves received by the external rod antenna 17 are sent to the tuner 160. Additionally, the knob board 110 is provided with a tuning knob 11 for selectively operating television radio waves, and the operating signal is sent to a circuit configured on the linear board 120. The linear board 120 includes a tuner power supply circuit 121, a tuning control circuit 122. A filter circuit 123, a linear circuit 124, and an audio amplification circuit 125 are provided. The tuning control circuit 122 provides tuning signals to the seven tuners 160 in response to operations from the tuning knob 111. This tuner 160 selects television radio waves received by the rod antenna 17 or an external antenna in accordance with a tuning signal from the tuning control circuit 122, converts it to an intermediate frequency, and transmits the signal to the filter circuit 12.
Output to 3. In this filter circuit 123, tuner 1
Only the frequency components of the desired channel selected in 60 are passed through, and the frequency components of adjacent channels are removed. After amplifying the intermediate frequency signal output from the filter circuit 123, the IJ near circuit 124 performs video detection and the like to separate the video No. 1, the audio signal, and the synchronization signal.

The audio signal output from the linear circuit 124 is amplified by the audio amplification circuit 125, then sent to the speaker 17θ, and output as audio. At ε, the synchronization command signal output from the IJ=A circuit 124 is output from the power supply circuit board 1.
The video signal and the synchronization signal are sent to the circuit configured in the display drive control circuit board 140.

The power circuit board 130 includes a power circuit 13'' and a
? 9.1 Source circuit 13 is provided with a channel drive circuit 132.
1 supplies an operating voltage to the tuner power supply circuit 121 and the display driving power supply circuit 144 described in 1 above. In addition, the panel drive circuit 132 turns off a communication circuit 145 formed on the display drive control circuit board 140 in response to a synchronization signal from the S=A circuit 124 to supply a light emitting operating voltage to the EL lighting panel 182, and displays A switching signal is provided to a circuit provided on the drive control circuit board 140. Above EL [
The illumination panel 182 illuminates the liquid crystal display panel 181 from the back side, thereby displaying a bright screen with good contrast and easy-to-see images. The display drive control circuit board 140 includes an analog/digital conversion circuit (hereinafter referred to as a converter) 141.
, an auto level control circuit 1-2, a display drive control circuit 143, and a display drive power supply circuit 144 are provided.

J The display driving power supply circuit 144 has an output voltage of
N, OFF controlled, and its output voltage is [
Display drive control circuit 143 and display drive circuit board
Operating power to the display drive circuit 151 configured in 150:
supplied as a source.

Above O) Level control time Wt1421f'i,
l Detect the level of the video signal from the linear circuit 12a and set the upper limit reference potential vH and lower limit reference potential vL to φ
1 to the converter 141. The A/D:1 converter 141 converts the video signal from the near circuit 124 into 4-bit, 16-gradation digital data using the reference potential vHa ML,
Enter to 3. This display drive circuit 143 operates in synchronization with the synchronization signal from the IJ near circuit 124, and supplies a drive signal to the scanning side electrode of the dot matrix liquid crystal display armpit 181. Outputs 4 pit data from.

The liquid crystal display panel 181 has its signal electrode group divided into four blocks as shown in FIGS. 21 m.

Display is driven for each block by 21b, 21e, and 21d. This is done for the following reasons.

In other words, in this embodiment, a dot matrix liquid crystal display
2-channel 181t - As mentioned above, since it is a double matrix type, the number of signal side electrodes is 320, so this liquid crystal display... To drive the signal-side electrode of the channel, an LSI with a total of at least 320 + α terminals (here α is the number of terminals for inputting control signals, etc.) is required, but such a large multi-terminal LSI is Since it is expensive and has limited versatility, using a large multi-terminal LSI has disadvantages in terms of cost. Therefore, in this example,
Double matrix dot matrix liquid crystal display panel 18
Divide the screen of 1 into 4 blocks a, b, e, d of 174 each as shown in Fig. 3, and each block a, b, c, d
Terminal Y of the signal side electrode of ! ~Y,, #Y,1~Y1.
. ,Y',~Y'8°#Y',,~Y'yo. . 4 above
LSI for driving signal side electrodes 21 m, 2 l
b, 21c.

21d respectively to make the liquid crystal display panel 181 1/
I am trying to drive four screens at a time. In this way, the LSIs 21 m, 2 l b, 21
e.

21d may be a small one with 100 terminals;
Since 0-pin LSIs are highly versatile and inexpensive, costs can be reduced. Further, since the number of scanning side electrodes of the double matrix type dot matrix liquid crystal display panel 181 is 60, the scanning side electrode driving LSI 21 shown in FIG.
e may also be of 100 pins.

FIG. 4 shows the liquid crystal display/signal 181 and LSIs 21 a to 21 (1 and LSIs 21 a to 21 (1) and LSIs 21 for driving the scanning side electrodes).
As described above, 4-bit data is input from the horizontal converter 141 to the scanning side electrode driving LSI 21, which shows the connection state with the SI 21e, and horizontal and vertical synchronizing signals are also input from the linear circuit 124. is entered. The LSI 21 has clocks f/I/s φ1, φ, for example, based on the horizontal and vertical synchronizing signals.
8. Sampling clock φB, latch mother pulse φ1,
Various timing signals such as a frame pulse φ and scanning electrode drive signals X and -X6° are generated, and four chip enable signals CE1 to CE4 are generated for each 4H synchronization as shown in FIG. And the above LSI
21e is a scanning electrode drive signal X, to X, applied to the liquid crystal display panel 181;

and chip enable signals CE1 to CE
4, the signal side electrode driving LSIs 21a to 21d are sequentially selected, and the four pit data and the various timing signals mentioned above are applied. The above LSIs 21a to 21d are LSIs
21 signal electrode terminals Y8 to Y of the liquid crystal display panel 181 according to data and timing signals from @. ,Y,
1-Y1. . , Y', ~Y',. IY'll~Y'1.
. are sequentially selected and displayed.

Next, display drive control circuit board 1401 display drive circuit 15
1. The details of the liquid crystal display panel 181 and the EL illumination panel 182 will be explained with reference to FIG. The display drive control circuit board 140 includes the above! 5, a power converter 141, an auto level control 142, a display drive control circuit 143, and a liquid crystal display drive power supply circuit 144 are provided.

This display drive power supply circuit 144 is a liquid crystal drive power supply 3).
and the switching element 32
It is controlled on/off by a switching signal from the 4-channel drive circuit 132. The liquid crystal driving power source 31 is supplied to the display drive control circuit 143 and the display drive circuit 15 via the switching element 32. The display drive control circuit 143 includes a positive/negative conversion circuit 4 that outputs the data from the Φ converter 141 as is or after inverting the data.
of.

It consists of a switch 42 for specifying the operation of the positive/negative conversion circuit 41, and a scanning side liquid crystal drive circuit 43 which operates in response to the output of the positive/negative conversion circuit 4 and a synchronization signal from the linear circuit 124. The scanning side liquid crystal drive circuit 43 creates the various timing signals described above based on the horizontal and vertical synchronization signals sent from the linear circuit 124, and generates the above-mentioned various timing signals together with the 4-pit data to the signal side display drive circuit 43.
51 and the liquid crystal display panel 181. in this case.

The positive/negative conversion circuit 41 includes an A/D converter 14
The 4-bit output DIA-D4 from 1 is output as is or inverted according to the switching operation of the switch 42, and the video signal can be arbitrarily inverted according to the function of the liquid crystal display A' channel 18. ing. That is, since the liquid crystal display panel 181 is driven with a positive video signal or with a negative video signal depending on the arrangement state of the polarizing plate, by providing the positive/negative inversion circuit 41, it is possible to It was designed to be able to deal with this as well.

Next, the LSIs 21a to 21a forming the display drive circuit 15 are
21d will be explained with reference to FIG. In the figure, 51 is a 4-bit x 80-stage shift register.

This shift register 51 includes the converter 1 shown in FIG.
A 4-bit video signal sent from No. 4 via the scanning side liquid crystal drive circuit 43 is read in synchronization with the sampling clock φS. In this case, the chip enable signals CE1 to CE from the scanning side liquid crystal drive circuit 43 cause the LS
After I21a to I21cl are sequentially selected and specified, and a latch pulse φL having a period of 4H is output as shown in FIG. 8, the first half of 80 dots is Minute data is LSI 21 m
The data for the latter 80 dots is latched to LSI 2.
latch to l b. Then, the video signal of the next second horizontal period is discarded, and the data for the first half of 80 dots is latched into the LSI 21c for the video signal of the M3 water cycle.
The data for the latter 80 dots is latched into the LSI 21d. No latch operation is performed on the video signal of the next fourth horizontal synchronization. That is, the video signal is latched and displayed every other horizontal period. Then, the data held in the shift register 51 is latched into a 4-bit x 80-stage buffer 52 according to the latch pulse φ, and transferred to the gradation signal generation circuit 53. Also, 54
A brightness modulation pulse generation circuit generates brightness modulation signals P□ to P4 using a latch pulse φ and a clock pulse φ, and inputs the generated brightness modulation signals P□ to P4 to the gradation signal generation circuit 53. The luminance modulation pulse generating circuit 53 is reset by a latch pulse φ1 and consists of a counter that divides the frequency of the clock pulse φ2.

The brightness modulation pulse P is sequentially frequency-divided by this counter.
1 to P4 are created. The gradation signal generation circuit 53 generates 16 types of gradation signals 80 to S having different time widths depending on the signal from the buffer 52 and the luminance modulation pulses P1 to P4 from the luminance modulation pulse generation circuit 54. is created and output to the two-channel analog multiplexer 55. This -v/I/frec vsstrz, frame/4'rus φ and U-'f- are driven by the drive signal Y8 by the voltages of V, , V, , V, , y, which have different levels.
~Y. occurs. These drive signals Y1 to Y. The signal electrodes of the liquid crystal display panel 181 are driven by this. In this case, the above voltages v0 to V,
As a predetermined potential, divide it into 9 equal parts from O to 9 levels (
(exactly divided into f19.1 equal parts) L, O level iV, 1 level vl, 2 level v8.6 level v,.

Level 7 is assumed to be tVa, and level 9 is assumed to be V.

Therefore, the liquid crystal display panel 181 is driven with a 1/9.1 bias. The liquid crystal display panel 181 has X□ to X, as shown in FIG. In each line of
The upper left row (80 dots) is LSI! 'Jm, upper right row (
SO dot) is LSI 2 l b, lower left is LS
I 21 e and the lower right row are displayed and driven by LSI 21 d. In this way, the LCD display panel 18
1, the screen is composed of 120 dots in the vertical direction and 160 dots in the horizontal direction. One frame is made up of two fields.

The first field and the second field are displayed on the same line. In the case of the above display method, the duty is determined by the formula: Duty=number of scanning lines/A/B. In addition, in the above formula, the person is 1
r2J is the number of fields constituting a frame, and B is the number of horizontal periods of the video signal allocated to one scanning electrode. In this invention, 4H minutes are displayed with one scanning electrode, so rB=4
It is J. Furthermore, since the number of scanning lines is 525 in Japan, the duty is as follows: Duty=□key-525÷2÷4 65.6.

Next, the details of the shift register 51, buffer 52, gradation signal generation circuit 53, and multiplexer 55 will be explained in the first section.
This will be explained using Figure 0. The figure shows one of the 80 stages in each of the above circuits.
Only the columns are shown. shift register 5
1 consists of a 4-bit register 511 in each stage, and 4-bit data D1 to D4 sent from the scanning side liquid crystal drive circuit 43 is read into the V-) register 511 in synchronization with the sampling clock φ8. be caught. This register 511
The data held in is output to the buffer 52 and also sent to the register 51 of the first stage. The /4 sofa 52 includes a 4-bit buffer register 521 in each stage, reads data from the register 511 in synchronization with the latch pulse φ, and outputs it to the 1st gradation signal generation circuit 53. This gradation signal generation circuit 53 includes OR circuits 531 to 534, AND circuits 535 . It consists of flip-flops 536 to 538, and the data from the buffer register 52 is sent to the brightness modulation noise generation circuit 5.
OR circuit 53 together with brightness modulation pulses P1 to P4 from 4
It is input to the AND circuit 535 via 1 to 53a. The output of this AND circuit 535 is read into a flip-flop 536 in synchronization with a clock pulse φ, and its output is input to a reset terminal R of a flip-flop 537. This flip-flop 537 receives a latch pulse φ.

The flip-flop 536 is reset by the latch pulse φ. The output of the flip-flop 537 is the clock /4/l/y.

The signal is input to the flip-flop sssK+t in synchronization with φ, and is sent to the analog multiplexer 55 as a gradation signal Si. The multiplexer 55 receives the gradation signal Si and frame pulse φf from the flip-flop 538 as well as the decoder 55 and transfer gates 552 to 555. The transfer gates 552 to 555 include v, , v, , v
, ,v, are input to the decoder 5.
f-) control is performed by the output of 5, V, ,
V, ,Vs.

The voltage of vo is selected and output as the signal electrode drive signal Yi.

[Effects of the Invention] As described above, according to the present invention, in a pocketable television receiver equipped with a liquid crystal display panel in which scanning electrodes and signal electrodes are arranged in an IJ box shape, the signal electrodes The drive circuit for driving the LSI is configured with a plurality of LSIs, and the plurality of LSIs are sequentially and selectively designated by the chip enable signal.
The SI and liquid crystal display panel are time-divisionally driven, and power consumption can be significantly reduced.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is a front view showing the external configuration, FIG. 2 is a block diagram showing the overall circuit configuration, FIG. 3 is an enlarged view of the liquid crystal display panel, and FIG. The figure shows the connection relationship between the liquid crystal display panel and the display driving LSI, FIG. 5 shows the generation timing of chip enable signals CH, to CH4, and FIG. 6 shows the display drive control circuit 1. , a diagram showing a liquid crystal display panel and an EL illumination panel part, FIG. 7 is a block diagram showing the configuration of an LSI in a display drive circuit, FIG. 8 is a diagram for explaining a video signal sampling operation in a display drive circuit, and FIG. FIG. 9 is a diagram showing the correspondence between the signal electrode driving LSI and the driving position of the liquid crystal panel, and FIG. 10 is a circuit configuration diagram showing details of the main parts of the signal electrode driving LSI. 10 River case, 11... Television image display window, 1
2m, 12b...Channel display section, 17...Rod antenna, 21h to 21d...L for signal side electrode drive
SI, 2J@... LSI for scanning side electrode drive, 120.
... Linear board, 130 ... Power supply circuit board, 140.
...Display drive control circuit board, 15o...Display drive circuit board, 180...Panel type image display device, 181...
・Liquid crystal display panel. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 Figure 5

Claims (1)

[Claims] In a pocketable television receiver equipped with a liquid crystal display panel in which scanning electrodes and signal electrodes are arranged in a matrix, one scanning electrode driving LSI for driving the scanning electrodes.
A pocketable television comprising: a plurality of signal electrode driving LSIs for driving the signal electrodes; and a chip enable means for selectively specifying the plurality of signal electrode driving LSIs. John receiver.