JPS6256081A - Pocketable television receiver - Google Patents

Abstract

PURPOSE:To display a very satisfactory picture without increasing extremely a duty factor with the minimum required information compression by making display the display data of the first and the second systems in the same backplate period. CONSTITUTION:A video signal of four bits sent from an A/D converter is read in to a shift register 51 synchronizing with a sampling clock phiS. At such a case, LSIs 21a-21d are selected and indicated in order by a chip enable signal from a displaying and driving control circuit, and after a latch pulse phiL having a period od 4H is outputted, share of eighty dots of data in the first half latch the LSI 21a against the video signal in the first horizontal period and share of eighty dots of data in the latter half latch the LSI 21b. And against the video signal in the third horizontal period neglecting the next second horizontal period, share of eighty dots of data in the first half latch the LSI 21c and share of eighty dots of data in the latter half latch the LSI 21d.

Description

[Detailed Description of the Invention] [Prior Art and its Problems] Recently, the display quality of various channels (dot matrix type liquid crystal display) has improved, and with this, plans have been made to put liquid crystal television screens into practical use. ing.

However, Japanese television has a system in which one screen is sent every 1/31), and the number of scanning lines is 525, of which approximately 480 are actually effective.

Furthermore, the current television screen signal is sent by interlace scanning for each IA screen every 1/60 seconds. Therefore, displaying 17 television images on a liquid crystal panel can be realized using 240 scanning electrodes by displaying adjacent interlaced scanning i-lines on the same scanning electrode for each v2 screen. The time during which one scanning electrode is selected is called one backplate period, and in the case of 240 scanning electrodes, it is 1/240 of one field period.

Since the aspect ratio of the TV 217 screen is still 3:4,
The number of signal electrodes required is approximately 320.

However, the number of display dots is limited to 240 on the ultra-compact liquid crystal display panels used in portable televisions.
Using X320 requires driving at 1/240 duty, which is difficult.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object thereof is to provide a pocketable liquid crystal display type television receiver that can display sufficiently satisfactory images and is also practical. purpose.

[Summary of the Invention] This invention is the same as the circuit of the first system that stores and displays digital data by sampling it once every 4H (once every 4H). By providing a second system circuit that samples a period H different from the above sampling period, stores and displays digital data, and displays the display data of the first system and second system in the same back plate period. By compressing information to the minimum necessary, without increasing the 7″ knee-to-weight ratio,
This is a pocketable television receiver with a resolution sufficient for practical use.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the external structure of a liquid crystal television receiver, and numeral 10 in the figure is a receiver case. The front of this case 10 includes a television image display window 11, a dual-use channel display section 12a, and a UHF channel display 2.
b. A sound emitting section 13 is provided. Then, the display window 11
A glass plate 14 is attached to the front surface of the channel display parts 12m and 12b.
5°15 is drilled. (9) On the upper side of the case 1o, there is provided a slide switch operation knob 16 that serves as a power switch and a VHF-UHF changeover switch.Furthermore, although not shown, on the side of the case 10, There is an external power connection port used when using an external DC power source (Battery GEX sold as an accessory for this television receiver) and a connection port for an external antenna (e.g. outdoor antenna). . Further, a rod antenna 17 is attached to the upper end of the negative side of the case 1°. This rod antenna 17 has a hinge 18 at its base.
It is held so that it can rotate nine times, and is stored in the upper part of the case 10 when not in use.

Next, the internal configuration of the TV set will be explained.

First, the circuit configuration of the television receiver shown in FIG. 2 will be explained. In this television receiver,
The circuit board is divided into an antenna board 100, a knob board 110, a linear board 120, a power supply circuit board 130, a display drive control circuit board 140, and a display drive circuit board 150, and the circuits described below are configured on each board 100 to 150. There is. In addition to the above-mentioned boards 100 to 150, a tuner 160
°Speaker 170. An A-flank image display device 180 is provided. As the panel type image display device 180, for example, a dot matrix liquid crystal display panel, an electroluminescent display panel, or the like is used. The dot matrix liquid crystal display panel 181 is of a double matrix type with a display dot count of 120 x 160, and a duty ratio of 1/65 f5. A driven TN (twisted nematic) type is used.

The antenna board 100 is connected to a rod antenna 17 provided in the receiver and an external antenna connection jack. Then, the television radio waves received by the rod antenna 17 or the external antenna are sent to the tuner 160. Further, the knob board 110 is provided with a tuning knob 111 for selectively operating television radio waves, and the operation signal is sent to a circuit configured on the linear board 120. The linear board 120 is provided with a tuner power supply circuit 121, a tuning control circuit 122, a filter circuit 123, a linear circuit 124, and an audio amplification circuit 125. The tuning control circuit 122 is configured as follows.

- Tuner 16 according to the operation from tuning knob 111
0hechi, -ning signal is given. This chi.

-Selector 160 selects the television signal received by rod antenna 17 or external antenna according to the tuning signal from tuning control circuit 122, converts it to an intermediate frequency, and outputs it to filter circuit 123. This filter circuit 123 passes only the frequency components of the desired channel selected by the circuit 160, and removes the frequency components of adjacent channels. After amplifying the intermediate frequency signal output from the filter circuit 123, the IJ near circuit 124 performs video detection and the like to generate a video signal.
Separate audio signals and synchronization signals.

The audio signal output from the IJ near circuit 124 is
After being amplified by the audio amplification circuit 125, the signal is sent to the speaker 170 and output as audio. Furthermore, the synchronization signal output from the IJ near circuit 124 is sent to a circuit configured on the power supply circuit board 130, and the video signal and synchronization signal are sent to a circuit configured on the display drive control circuit board 140.

The power supply circuit board 130 is provided with a power supply circuit 131 and a panel drive circuit 132, and the power supply circuit 131 supplies an operating voltage to the tuner power supply circuit 121 and a display drive power supply circuit 144, which will be described later. Further, the four-channel drive circuit 132 is connected to the communication circuit 1 formed on the display drive control circuit board 140 in response to the synchronization signal from the linear circuit 124.
45t-, it supplies a light emission operating voltage to the EL lighting panel 182, and also gives a switching signal to the circuit configured on the display drive control circuit board 140. The EL lighting panel 182 illuminates the liquid crystal display panel 181 from the back side to display a bright screen with good contrast and easy-to-see images. and,
The display drive control circuit board 140 includes an analog/digital conversion circuit (hereinafter referred to as a converter) 141. An auto level control circuit 142, an N-socket movement control circuit 143, and a display driving power supply circuit 144 are provided. The output voltage of the display drive power supply circuit 144 is turned on and off by the switching signal from the panel drive circuit 132.
The output voltage is supplied as an operating power to a display drive control circuit 143 and a display drive circuit 151 configured on a display drive circuit board 150. The auto level control circuit 142 detects the level of the video signal from the linear circuit 124 and provides an upper limit reference potential Vn and a lower limit reference potential Vx to the ψ converter 141.

This ψ converter 141 converts the video signal from the linear circuit 124 into 4 bits by using the reference potential vH2VL.
Convert to 6-gradation digital data and display drive control circuit 1
43. This display drive circuit 143 operates in synchronization with the synchronization signal from the linear circuit 124, and supplies a drive signal to the scanning side electrode of the dot matrix liquid crystal display channel 181, and also supplies a drive signal to the display drive circuit 151 from the ψ converter 141. Outputs 4-bit data.

However, the liquid crystal display A? The panel 81 has a signal electrode group divided into four blocks as shown in FIG.
Four signal-side electrode driving LSIs of the display driving circuit board 150 21 a - 21 b p 21 c #2
1d, the display is driven for each block. The above FIG. 3 shows the liquid crystal display panel 181, signal side electrode driving LSIs 21a to 21d, scanning side electrodes,
This shows the connection state with the driving LSI 21 a, and the scanning side electrode driving LSI 21 has φ as described above.
4-bit data is input from the converter 141, and horizontal and vertical synchronization signals are input from the linear circuit 124. The LSI 21e has, for example, a clock signal φ1 based on the horizontal and vertical synchronizing signals.
．． φ2, Sunfrink Chronoku φas7 Tsuchiharusu φL
, frame pulse φr, scanning electrode drive signals X1 to Xso
Various timings such as
Generates E4.

The LSI 21 is a liquid crystal display panel 181.
While supplying scanning electric drive signals x1 to Xll0 to
The chip enable signals CE1 to CE sequentially select the number side electrode driving LSIs 21a to 21d and give them 4-bit data and the various timing signals mentioned above. LCD display panel 1 according to data and timing signals
81 signal electrode terminal Y1-YI Os Y81~Yl
ll. Yl, ~Y'8°, Y', and 1%Y'16° are sequentially selected and driven for display. The reason why the liquid crystal display panel 181 is divided into four blocks and driven as described above is as follows.

That is, in this embodiment, a dot matrix liquid crystal display/
? Since the channel 181 is of the double matrix type as described above, the number of signal side electrodes is 320, and therefore the total number of terminals (here, α is the number of terminals for inputting control signals, etc.), but such large multi-terminal LSIs are very expensive and lack versatility, so large multi-terminal LSIs are required. Using this has a disadvantage in terms of cost. Therefore, in this embodiment, the screen of the double matrix dot matrix liquid crystal display panel 181 is divided into four blocks of t-1/4 each, and the terminals Y1 to Y II Oe Y81 of the signal side electrodes of each block are
~Y160 + Y'l ~y/, O+ y/, l
-“18G is LSI 21 for driving the four signal side electrodes.
a, 2lb, 21c.

21d respectively to connect the liquid crystal display panel 1811/
I am trying to drive four screens at a time. In this way, the LSIs 21a, 2lb, 21
c.

21d may be a small one with 100 terminals;
Since 0-pin LSIs are highly versatile and inexpensive, costs can be reduced. Further, since the number of scanning side electrodes of the double matrix type dot matrix liquid crystal display panel 181 is 60, the scanning side electrode driving LSI 21a provided on the display drive control board 140 may also have 100 pins.

Next, the LSIs 21h to 21h constituting the display drive circuit 151 are
21d will be explained with reference to FIG. In the figure, numeral 51 is a 4-bit) x 80-stage shift register.

This shift register 5 has a φ converter 1 shown in FIG.
A 4-bit video signal sent from 41 via display drive control circuit 143 is inputted in synchronization with sampling clock φS. In this case, the display drive control circuit 14
LSIs 21 to 21d are sequentially selected and designated by chip enable signals CE1 to CE4 from 3, and after a latch pulse φL having a period of 4H is output as shown in FIG. For the video signal in
The data for the latter 80 dots is latched to LSI 2.
1 Latch to b. Then, the first-order second horizontal period video signal is discarded, and the first half 8
The data for 0 dots is latched to the LSI 21e, and the data for the latter 80 dots is latched to the LSI 21d. No latch operation is performed on the video signal of the next fourth horizontal synchronization.

That is, the video signal is latched and displayed every other horizontal period. Then, the shift register 51
The data held in is latched into the buffer 52 of 4 pits×80 stages by the latch pulse φL, and transferred to the gradation signal generation circuit 53.

Further, 54 is a brightness modulation pulse generation circuit which generates brightness modulation signals P1 to P4 using the latch pulse φL and the hiclock pulse φ2, and manually outputs the brightness modulation signals P1 to P4 to the gradation signal generation circuit 53. The brightness modulation pulse generation circuit 53 is reset by a latch pulse φ, and a counter 9 for frequency dividing the clock signal φ2 sequentially generates brightness modulation pulses P1 to P4 whose frequency is divided by 1/2. Thus, the gradation 1n generation circuit 53 receives the signal from the buffer 52 and the brightness modulation/! Sixteen types of gradation signals s i "" S, o having different time widths are generated by the brightness modulation seven-arm pulses P1 to P4 from the pulse generating circuit 54 and outputted to the two-channel analog multi-bleph sensor 55. This multi-breather 55 generates frame pulses φf, vo, (2), which have different levels, respectively. v3. Drive signal Y1%Y, by the voltage of v11. occurs. This drive signal Y
1 to yso drive the signal electrodes of the liquid crystal display panel 181. In this case, the voltages vo to V are set between 0 and 0, with vo at the ground level and Vs' at a predetermined potential.
Divided into 9 equal parts up to level 9 (to be exact, divided into 9.1 parts) L, QC Lebel'tVo, level 1 v, level 2 v2.
6 level vs, 7 level ■4.9 level v
It is set as s.

Therefore, the liquid crystal display panel 181 is driven with a 1/9.1 bias. And the above LCD display/? As shown in FIG. 6, in each row of X1 to XSO, the channel 181
The upper left row (SO dot) is an LSI, ? Ja, upper right row (
The lower left side is LSI 21 c, and the lower right side is LSI 21 d.
The display is driven by In this way, the screen of the liquid crystal display panel 18 is composed of 120 dots in the vertical direction and 160 dots in the horizontal direction. One frame is composed of two fields, and the first field and the second field are displayed on the same line. In the case of the above display method, the duty is determined by the following formula. In addition, in the above formula, A is 1
r2J is the number of fields constituting a frame, and B is the number of horizontal periods of the video signal allocated to one scanning electrode. In this invention, display is performed using 11 scanning electrodes for 4H, so rB=4
It is J. Also, since the number of scanning lines is 525 in Japan, the duty is .

becomes.

[Effects of the Invention] As described above, according to the present invention, in a pocketable television receiver equipped with a liquid crystal display panel in which the scanning f: electrodes and signal electrodes are arranged in a matrix,
Same as the first system circuit that samples the TVIL video signal once every 4H to store and display digital data (samples once every 4H, but at a different H period from the above sampling period) A second circuit for storing and displaying digital data is provided, and the display data of the first and second systems are displayed during the same backplate period, reducing the duty cycle by compressing the information to the minimum necessary. The present invention is capable of displaying a sufficiently satisfactory image without extremely increasing the ratio, and furthermore, it is possible to realize a practical liquid crystal display system pock-taple television receiver.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is a front view showing the external configuration, FIG. 2 is a block diagram showing the overall circuit configuration, and FIG. 3 is a liquid crystal display A? channel and display driving LSI
4 is a block diagram showing the configuration of the LSI in the display drive circuit, FIG. 5 is a diagram illustrating the video signal sampling operation in the display drive circuit, and FIG. 6 is a diagram showing the signal electrodes. FIG. 3 is a diagram showing the correspondence between the driving LSI and the driving position of the liquid crystal display/mother panel. DESCRIPTION OF SYMBOLS 10... Case, 11... Television image display window, 12a, 12b... Channel display part, 17...
Rod antenna, 21a to 21d...LSI for driving the signal side electrode 1.2Je...LSI for driving the scanning side electrode, 12
0... Linear board, 130... Electrode circuit board, 14
0-- Display drive control circuit board, 150... Display drive circuit board, 180... Nine-channel image display device, 181
...LCD display panel. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (2)

[Claims] (1) A liquid crystal display panel in which a plurality of scanning electrodes and signal electrodes are arranged in a matrix, and each scanning electrode is scanned every one backplate period, and an A/C display panel that samples television video signals and converts them into digital data. A D converter, a first latch that stores digital data sampled by this A/D converter once every 4H (horizontal scanning period), and a first latch that stores digital data sampled by the A/D converter once every 4H (horizontal scanning period); A second latch stores digital data sampled at a different H from the sampling period, and the digital data stored in the first latch and the digital data stored in the second latch are stored in the same backlog. 1. A pocketable television receiver comprising means for converting and outputting signals to different signal electrodes during plate periods. (2) Scanning electrodes arranged in multiple rows in the row direction (horizontal direction) and signal electrodes arranged in multiple columns in the column direction (vertical direction) so that signals are alternately supplied from the upper side and the lower side. an A/D converter that samples television video signals and converts them into digital data; A first latch stores the first half 1/2H of digital data sampled by the converter once every 4H (horizontal scanning period), and a second latch stores the second half 1/2H of the sampled digital data. a third latch for storing the first half of the digital data sampled by the A/D converter at a different H value than the sampling period once every 4H; a fourth latch that stores the latter half 1/2H of the data; and a fourth latch that converts the digital data stored in the first latch into a signal and supplies it to the left half of the signal electrode group from above and stores it in the second latch. The digital data stored in the third latch is converted into a signal and supplied to the right half of the signal electrode group from above, and during the same back plate period as these signals are supplied, the digital data stored in the third latch is converted into a signal and supplied to the right half of the signal electrode group. A pocketable television comprising means for supplying the left half of the signal electrode group from below, and converting the digital data stored in the fourth latch into a signal and supplying the signal to the right half of the signal electrode group from the bottom. John receiver.