JPS6247990A - Dimmer controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a light control device for controlling the light of a stage or the like.

BACKGROUND TECHNOLOGY For example, when performing lighting effects on a stage, it is effective to periodically and rhythmically turn on and off the lighting load, or to perform dimming control at an arbitrary dimming level, as a means to enhance stage effects and display effects. and the seventh
Prior art is disclosed as shown in the figure. This dimming control device 1 includes a level setting circuit 2 that sets the dimming levels of the lighting loads L1 to L3, and dimming level holding memories 4 and 5 in which the dimming levels set by the level setting circuit 2 are stored. , a periodic control circuit 3 that outputs pulse signals of a constant period to the memories 4 and 5, a circuit connector 6 to which the dimming level signal from the memory 4.5 is input manually, and a circuit 'PA connector 6. When the dimming level signal is input, the lighting load L1
-L3 phase control dimmer 7.8.9.

The level setting circuit 2 is composed of a binary switch, a numeric keypad, etc., and outputs a level signal (0 to 100).
%).

The period control circuit 3 includes a memory 4. ．． A pulse signal of a constant period is applied to the memory 5, and this pulse signal becomes a read/write signal, and the memories 4 and 5 are shifted. As a result, the dimming level data held in the memories 4 and 5 are exchanged. The memory 4 is connected to the input terminal P1 of the circuit connector 6, and the memory 5 is connected to the input terminal P2 of the circuit connector 6. The output terminals Q], Q2 of the circuit connector 6 are connected to the dimmers 7, 8,
Further, the output terminal Q3 is connected to the dimmer 9. Dimmer 7
-9 are constituted by thyristors and the like, and control the phase of the lighting loads L1-L3 so that the dimming level corresponds to the dimming level signal from the circuit connector 6.

For example, if memory 4 holds a dimming level of 100% and memory 5 holds a dimming level of 0%, the lighting load is 1. ,1
．． , L 2 is I, χ lamp (ON) L, lighting load L
3 turns off (o F F >. Then periodic control circuit 3
When the memories 4 and 5 are shifted by the pulse fif, the memory 1 retains the dimming level of 0%, and the memory 5 retains the dimming level of 100%. Therefore, the lighting loads Ll and L2 are turned off (OFF),
The lighting load L3 lights up (ON). In this way, the pulse signals from the periodic control circuit 3 control the lighting loads 1-1 to L.
The lighting and extinguishing operations of 3 can be repeated. Note that the blinking speed of the lighting loads L1 to L3 can be changed by changing the cycle of the pulse signal from the cycle control circuit 3.

In such prior art, in order to change the blinking and dimming patterns of the lighting loads L1-L3, the level setting circuit 2 changes each data held in the memories 4 and 5, or
Alternatively, it is necessary to change the connection mode of the circuit connector 6. For this reason, there is a problem in that during the dimming control operation, it is not possible to easily change the blinking and dimming patterns.

Purpose An object of the present invention is to provide a dimming control device that solves the above-mentioned technical problems and is capable of blinking a lighting load and changing a dimming pattern even during dimming control operation. be.

Embodiment @1 FIG. 1 is a block diagram of an embodiment of the present invention. The light control device 1o according to the present invention basically has a lighting load L
Level setting circuit 1 that sets the dimming level of ll to L15
1, a dimming level signal generating circuit 13 which generates a dimming level signal by updating the dimming level signal set by the level setting circuit 11 at a constant cycle, and updating of the dimming level signal of the dimming level signal generating circuit 13. A cycle control circuit 12 that sets the cycle, dimmers 16 to 2o that perform phase control of the lighting loads Lll to L15 based on the dimming level signal, and a dimming level signal generation circuit 13 that keeps the dimming level signal constant. A switching means 14 that periodically switches and connects the dimmers 16 to 2o;
It also includes a period control circuit 15 for setting the period of switching connection of the switching means 14.

The level setting circuit 11 includes a level setting means 21 and a means 2.
1 is set by a slide volume, binary switch, numeric key, etc. for setting the dimming level of the lighting loads 1, 11 to L15. The level is set via the level setting control circuit 22 in the dimming level signal generating circuit 13, in the dimming level holding memory 28 and in the dimming level updating buffer memories 29 to 31.

The period control circuit 12 includes a period setting means 23 constituted by a slide volume or the like, and an oscillation circuit 24 that outputs a pulse signal with a period set by the period setting means 23.
and a cycle setting control circuit 25. The cycle setting control circuit 25 responds to the pulse output from the oscillation circuit 24 and sends the dimming level signal generation circuit 13 a certain cycle at regular intervals.
Provides a pulse signal for 0N10FF switching. This 0N
The 10FF switching pulse signal becomes a read/write signal for the holding memory 28 and update buffer memories 29 to 31, as described later.

It includes a fi half level M number a M ridge 12++ Zusu soting means 26, 27, a memory 28 for holding the dimming level, and buffer memories 29 to 31 for updating the i shoulder level. The switching means 26 consists of a switch 81a=S1d. Each contact point Pla-P of switch 5la-3ld
ld is commonly connected to the level setting control circuit 22, and the other contacts Q1a to Qld are connected to the dimming level holding m.
Memory 28 and V dimming level update buffer memory 29
~31 individually. Switch 5la-6ld
are selectively controlled by control signals from the level setting control circuit 22, whereby the initial dimming level set by the level setting means 21 is written into the holding memory 28 and the updating buffer memories 29 to 31, respectively. I can do it.

The switching means 27 extends from the switches 52a-32d. Each contact of one of the switches 52a-82d, ξ',
The circuits P 2 a - P 2 d are commonly connected to the control circuit 25 for setting the same period in hv, and each of the other connections, ;':Qla
-Ql"d is individually connected to the holding memory 28 and the updating buffer memories 29 to 31. The switch 52
a-82d is selectively controlled by the pulse FA number from the cycle 1 role 11 control circuit 25, and the memory 28 and buffer are controlled by the ON/○r"l" switching pulse signal from this control circuit 25. Memory 29-31
A shift operation is performed between them, and the 1 μm light level data held in each memory 28 to 31 is exchanged. Therefore, the dimming level signal generation circuit 13 outputs the dimming level signals (0% to 100%) held or updated in the holding memory 28 and the updating buffer memories 29 to 31, respectively.
%) are derived to line No. 1 sequentially and while being updated.

The period control circuit 15 has the same configuration as the period control circuit 12, and outputs a pulse signal having a period set by the period setting means 32, which is constituted by an input ride volume, etc., and the period setting means 32. It includes an oscillation circuit 33 and a period setting control circuit 34. Cycle setting control circuit 3
4 provides a switching connection layer signal to the switching means 14 in response to the pulse output from the oscillator circuit 33.

Switching hand j, i14 is switch 53a-33c
including. Each contact of the switches 53a-33c, 1.
', i: P 3 a - P 3 c are connected to the holding memory 28 of the dimming level signal generation circuit 13 via line 1.
commonly connected to Switch S3a external force contact Q3
a is connected to the dimmer 16.17, a contact Q:3b of the switch j7 of the switch S3b is branch-connected to the dimmer 1'7.18, and the other contact Q3c of the switch S3c is connected to the dimmer Branch connection will be made at 19.20. Switch 53a=S
3c switches and connects the dimming level signal generation circuit 13 and the dimmers 16; 17, 18; 19, and 20 in response to a constant cycle switching connection signal from the cycle setting control circuit 34.

The dimmers 16 to 20 perform a phase control method using a thyristor or the like, and control the lighting load L11 of the group in response to the dimming level signal (0% to 100%) from the switching means 14.
~■ Performs dimming control of the blinking upper V dimming pattern of 515.

With reference to FIGS. 2 and 3, lighting load L11; Ll
2. Ll 3; Ll 4. By flashing Ll 5 alternately, initialize the holding memo') 2 il to 3!4 range level and set the le signal 10()%, and update the buffer memory 2.
9, initialize the dimming level signal ()% in the update buffer/memory 30, initialize the dimming level signal 1()0% in the update buffer memory 3], and set the dimming level No. 114 0% in the update buffer memory 3].
Set up the first JTA. Holding memory 28 and update buffer memory 29 to 3 by period Ill lπ circuit 12
By the shift operation of 1, the data held in the buffer memory 31 is written to the buffer 7 memory 30.

The data held in buffer memory 30 is stored in buffer memory 2.
The data held in the two buffer memories is written to the memory 28, and the data held in the holding memory 28 is written to the memory 28.
The data is written to the buffer memory 31. In this way, based on the switching cycles of the switches 82a to 32d set by the cycle control circuit 25, the data held in each of the memories 28 to 3 is shifted, so that the dimming level signal generation circuit 13 changes the line! The dimming level signal derived at 1 has an output waveform shown in FIG. 2 (1).

The switches S3u to 831- of the switching means 14 are
0'S2 by the pulse signal from the periodic control circuit 15
As shown in Figures (2), (4), and (6), sequential 1
This ON/OFF has a preload of 1. r, that is, switch S38 is turned ON at time +, l -C3, C7-C9, and switch S31] is turned ON at time t3-1.5, C9.
-t, I I TON, and the switch S 3 c is
Time t5-t? , Ll 1-113 turns ON. Therefore, in the dimmers 16 to 20, as shown in FIG.
The dimming level signals Ij shown in (5) and (7) are obtained. That is, the I dimming level signal C7 sent to the dimmer 16 is transmitted from time t1 to t2. It is 100% from t7 to t8, and the dimming level signal given to the dimmer 17.18 is 100% from time t3 to t4. t9 to t10''c100%, and the dimming level signal given to the dimmer 19.20 is at time t5.
~t6. It is 100% from tl 1 to t12. Therefore, the lighting load L11 is increased from time L1 to t2. It lights up during the period from t7 to t8, and the lighting load L12. Ll3 is from time t3 to
t4, lights up in the period from C9 to t10, and the lighting load L14
, 15 is the time [5 to t6. It lights up during the period from tll to t12.

In this way, the switches 83a to 33c are sequentially switched according to the period set by the periodic control circuit 15, and the lighting loads L11 to I-1, 5 shown in FIG.
3), (,5), (7) ノ,'',1: It is possible to obtain the zero pattern.

Next, when changing the cycle of the pulse signal from the cycle control circuit 15 and changing the switching operation of the switches 53a to 83c, as shown in FIG. 3 (2), (4), and (6), Assume that Here, the switch S3a is operated from time t1 to t4.
．． The switch S3b is turned on at times t4-17.jlO to t13. Ll 3-tl 6t' is ON, and the switch S3c is turned ON at time t7-tlo. Therefore, the dimmers 16 to 20 have fjS3IN(3), (
Dimming level signals shown as 5) and (7') are given. That is, the dimming level signal given to the dimmer 16 is
Time L1-t2, C3-t4. io from tll to t12
o%, and the dimming level signal given to the dimmer 17.18 is from time t5 to t6. t13~tl 4. tl 5
~t16 is 100%, and the dimming level signal given to the dimmer 19.20 is at time t7~t8, C9~tl
o is 100%. Therefore, the lighting load Lll is set during the period from time t'' to t2, from C3 to E4, from 11 to 112,
l,',i: Lights on, lighting loads L12 and Ll3 at time t
5 +・C6, t ] 3 to t14. The lighting loads L14 and 15 are turned on during the period from t15 to t16, and the lighting loads L14 and 15 are turned on during the period from t7 to t16.
8. Lights up during the period from t9 to []0.

Even if the light control level signal generation circuit 13 generates signal 1) as shown in 2 above, even if it is a simple 0N (0%) 10FF (100%) signal, the switches 53a-33c periodically control the lighting load Lll~ By making a switching connection with L15, it becomes possible to realize various blinking patterns with a small-scale circuit configuration. Furthermore, by changing the update cycle of each of the memories 28 to 31 of the cycle control circuit 12 for the dimming level signal generation circuit 13, it is possible to continuously change different flashing patterns even during dimming operation.

FIG. 4 is a block diagram of another embodiment of the invention. FIG. 4 is similar to the structure of FIG. 1, and corresponding parts are given the same reference numerals. In this example, the level IL te
Ch “Seedling nk 1 1 L
1st day! 1 eJI dynamic rl 0k
4 Q L 414 j A single dimming control unit is constructed from the dimming level signal generating circuit 13, and a plurality of the dimming control units are connected to the switching means 14 via the switching means 35. be. The switching means 35 is a switch 54
One of the contacts P4a to P4n of the switches 54a to 84n are respectively connected to the dimming control unit, and the other contacts αQ4a to Q4n are commonly connected to the switching means 14. These switches 84
a-34n is controlled by a pulse signal from a period control circuit 36 having the same configuration as the period control circuit 12.15.
They are connected sequentially at a constant switching cycle. By switching and connecting a plurality of dimming control units by the switching means 35 in this way, it becomes possible to generate other types of blinking patterns.

FIG. 5 is a block diagram of an embodiment of the pond of the present invention, and FIG.
The figure is a waveform diagram related to FIG. Figure 5 is similar to the configuration of Figure 1, and the corresponding parts are the same 4111.
Add a mark. In this embodiment, one switching stage] = 1
There are two types, in which dimming level holding memories 40a-4On are interposed between the dimmers 16a-10o and the dimmers 16a-10o. Once the memories 40a to 40 were connected to the dimming level level 3, the memory 40a
~40n maintains the Wl likelihood level 15''i, so its output 1 skin form becomes as shown in 6th fA (1) to (7). That is, the adjustment from the dimming level signal generation circuit 13 The optical level signal has the output waveform shown in Figure 6 (1).
In some cases, the switches 53a-83c are sequentially turned on as shown in FIG. 6 (2>, (4), and (6))
/ OFF operation is assumed. Here, the switch S3n is activated at time tl - t4. tl 0-tl, 3
The switch S3b is turned ON from time t4 to t7.
N, and the switch S3c is turned ON at time t7-NO. Therefore, the dimming level signals shown in FIG. 6 (3), (5), and (7) are held in the holding memories 40a to 40c. That is, the dimming level signal held in the memory 40a is from time t1 to L2 and from t3 to t10yt12.
The dimming level signal is 100% from time to t12, and the dimming level signal held in the memory 40b is 100% from time 5 to t6. tl, 3-t14
The light control level signal held in the memory 40c is 100% at time 7 to t8. 100% from t9 to t, 14
It is. Therefore, the lighting load Lll is from time E1 to t2.
．． Lights up during the period t3~L10゜tll~t12,
The lighting load, L12°L13, is calculated from time t5 to t6. t13
-t14, the lighting load L14. ,15 is
It lights up during the period from time t7 to time t8 and from time t9 to time 114. In this way, the memories 40a to 40c can be connected to the dimmers 16a to 1.6n.
By providing on the simple side of the switching means 14
Even when turned off, a given dimming level can be maintained, and a wide variety of changes in dimming patterns can be obtained.

In the embodiment described above, the blinking pattern of the lighting loads Lll to I, 15 was explained by setting the dimming level signal to either 0% or 100%, but the blinking pattern is not limited to this, and any dimming level from 0% to Lighting load L 11 which is 100%
The same applies to the dimming patterns of ~L15.

The timing of updating the dimming level data of the dimming level signal generation circuit 13 and the switch 5 of the switching means 27
The timing of switching la-8ld may not be synchronized as in the above embodiment, or may be synchronized.

Effects As described above, according to the present invention, a plurality of set dimming levels are individually stored by the dimming level setting means for setting the dimming level of the lighting load and the setting T=stage. a plurality of memories; means for sequentially shifting and updating each dimming level stored in these memories at a predetermined cycle; and means for setting an update cycle of the update means;
a switching means that receives a dimming level signal from one of the plurality of memories, sequentially switches it at a predetermined period and outputs it to a dimmer, and sets a switching period of the switching means. By providing the means, it is possible to realize a wide variety of blinking and dimming patterns with a small-scale circuit configuration even during dimming control operation.

[Brief explanation of the drawing]

1 is a block diagram of an embodiment of the present invention, FIGS. 2 and 3 are output waveform diagrams related to 1 and 1, and FIG. 4 is a block diagram of an embodiment of the present invention. 1 and 5 are block diagrams of still another embodiment of the present invention, FIG. 6 is an output waveform diagram related to FIG. 5, and 7L4 is a block diagram for explaining the prior art. 1.10...Dimmer control device, 2,11...Level setting circuit, 3,12,15.36...Periodic control circuit, 4
, 528-3140a-40n...Memory, 7-9
, 16~20...lT! Optical device, 13... Dimming level signal light 'l-1 circuit, 14.26, 27.35... Switching f+ stage agent Patent attorney Keiichi Nishikyo Figure 2 Figure 3 Figure 6 Figure 7 figure

Claims (1)

[Scope of Claims] Dimming level setting means for setting a dimming level of a lighting load; a plurality of memories that individually store a plurality of dimming levels set by the setting means; and the memory. means for sequentially shifting and updating each dimming level stored in the plurality of memories at a predetermined cycle; means for setting an update cycle of the update means; A dimming control characterized by comprising: a switching unit that receives a dimming level signal, sequentially switches the signal at a predetermined cycle, and outputs the signal to a dimmer; and a unit that sets a switching cycle of the switching unit. Device.