SU1548862A1 - Device for shaping phase-manipulated signals - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to reduce the level of out-of-band emissions while simultaneously expanding carrier frequency ranges and wiring speeds. The device contains a source 1 of carrier frequency signals, a phase manipulator 2, an amplitude modulator 3, a source of 4 clock pulses, a controlled frequency divider 5, a manipulating signal code generation unit 6, a memory block 7, a source of 8 information signals, a driver 9 of manipulating signals . This device generates a phase-shift keyed signal with an amplitude rounding of the fronts, approximated by any law of a step envelope. The number of stages is determined by the counting module of the shaping unit 6, and the duration of each step is determined by the frequency of the pulse sequence received from the divider 5 at the clock input of the shaping unit 6. 2 Il.

Description

315

The invention relates to radio engineering and can be used in building transmitters of phase-shift keyed signals.

The purpose of the invention is to reduce the damage of out-of-band emissions while simultaneously expanding the carrier frequency ranges and wiring speeds.

Figure 1 shows the structural electrical circuit of the device; figure 2 - timing charts of his work.

The device contains a source 1 of carrier frequency signals, a phase manipulator 2, an amplitude modulator 3, a source of 4 clock pulses, a controlled frequency divider 5, a manipulating signal code generation unit 6, a memory block 7, a source of 8 information signals, a driver 9 of manipulating signals .

The device works as follows.

The device generates a phase-shift keying signal with an amplitude rounding of the fronts approximated by any law of a step envelope. The number of stages is determined by the counting module of block 6, and the duration of each stage is determined by the frequency received from the controlled divider 5 of the pulse train frequency per clock input of block 6,

On figa shows the information

V signal

Inf

in Fig. 26, the signal modulating the carrier frequency in amplitude (linear modulation law is shown) in Fig. 2c - the law of phase change. Phase rotation occurs at the moments when the modulating function (Fig. 26) is zero. Therefore, the phase jump is shifted relative to the imgg pulses of VMHCpHa half the rounding time of the fronts. In FIG. 2g, a voltage is applied to the control input of phase manipulator 2.

Shaper 9 manipulating signals synchronizes the fronts of pulse sequences coming from a source of 4 clock pulses and a source of 8 information signals. The controlled frequency divider generates a clock frequency signal by dividing the frequency of the clock pulses 1 received from the source 4 "

0

five

0

five

0

35

40

45

50

55

Block 6, by the signal VV11) T, arriving at its control input, forms a code (FIG. 2d), the change of which occurs on the fronts of the information dressing. The output code of block 6 is fed to the address inputs of memory block 7. The law of rounding up information infusions is determined by which law is written into memory block 7 (Fig. 2b).

The highest bit of the output code of block 6 is used to form the control voltage supplied to the control input of the phase manipulator 2 (Fig. 02d). At this command, the phase manipulator 2 changes the phase of the output oscillation in accordance with FIG.

Amplitude modulator 3 produces amplitude modulation of the signal supplied from phase manipulator 2 in accordance with the code fed to its control inputs from memory block 7. At the output of the amplitude modulator 3, a phaeomanipulated signal is formed, rounded in amplitude (Fig. &Quot; 2e).

Claims (1)

The formula is invented :, and A device for generating phase-mapped signals, containing a serially connected source of carrier frequency signals and a phase handler, an amplitude modulator, a source of clock pulses, and a serially connected source of information signals and a shaper of manipulating signals, in order to reduce the level of out-of-band emissions, while simultaneously expanding the carrier frequency ranges and wiring speeds, serially connected controlled divider Oy, the manipulating signal code generation unit and the memory block whose outputs are connected to the control inputs of the amplitude modulator, the output of the clock source source is connected to the first input of the controlled frequency divider, the other inputs of which are wiring speed settings commands, the output of the carrier signal source frequency is connected to the second input of the driver of the manipulating signals, the output of which is connected to the second input of the code generator of the manipulating signal, the higher bit output of which is connected to the control input of the phase manipulator, and the output of the phase manipulator is connected to the input of the amplitude modulator, the output of which is the output of the device, 2