JPS6247621A - Liquid crystal display device - Google Patents

Liquid crystal display device

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Publication number
JPS6247621A
JPS6247621A JP60190852A JP19085285A JPS6247621A JP S6247621 A JPS6247621 A JP S6247621A JP 60190852 A JP60190852 A JP 60190852A JP 19085285 A JP19085285 A JP 19085285A JP S6247621 A JPS6247621 A JP S6247621A
Authority
JP
Japan
Prior art keywords
film
electrode
liquid crystal
ito
picture element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60190852A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Kouden
充浩 向殿
Tadanori Hishida
忠則 菱田
Shigehira Minezaki
峰崎 茂平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP60190852A priority Critical patent/JPS6247621A/en
Publication of JPS6247621A publication Critical patent/JPS6247621A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the operating characteristics and the reliability of the device by insulating between a transparent electroconductive film (a ITO film) composed of a picture element electrode and a thin film transistor (TFT), thereby preventing a reaction of the ITO film and the metallic film. CONSTITUTION:The TFT comprises a gate electrode 11, a gate insulating film 12, a semiconductor film 13, a source electrode 18 and a drain electrode 19. The drain electrode 19 is connected with the ITO film 15 of the picture element electrode. The reaction of the film 15 and an Al-Si film 17 of the drain electrode is prevented by lying a P-dopped a-Si film at a junction point of the electrode 19, the film 13 and the film 15, thereby giving an ohmic contact. The indium contd. in the film 15 does not diffuse in the semiconductor film by lying a silicon nitride film 14 between the films 13 and 15, thereby preventing the generation of a deterioration of the TFT characteristics. Thus, the thin film type transistor active matrix liquid crystal display device having the good operation characteristics and the high reliability is obtd.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、半導体層としてア七ルファヌ・シリコン(a
−5i)を用いた薄膜トランジスタ(TPT)をスイッ
チング素子としてマトリックス状に配列形成して成るア
クティブマトリックス型腋晶表示装置に関し、特に上記
TPTにおけるソース・ドレイン電極と透明導電膜で形
成された絵素電極の構造に独特の製造技術を駆使したも
のである。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention uses arphanu silicon (a
-5i) Regarding an active matrix type axillary crystal display device formed by arranging thin film transistors (TPT) as switching elements in a matrix, in particular source/drain electrodes in the TPT and picture element electrodes formed from a transparent conductive film. The structure utilizes unique manufacturing technology.

〈従来の技術〉 近年、液晶を用いた大容量表示装置において、絶縁性基
板上にTFTをマI−IJソックス状形成したアクティ
ブマ) IJフックス液晶表示装置の研究が活発に行な
われている。TPTの半導体材料としてハホリシリコン
(ポリ−5i)、 アモルファスシリコン(a−5i)
、テルル セレン(CdSe)合金等がある。特にa−Siは比較
的低温で生成されるため、安価なガラヌ基板上に多数の
TPTを形成することができる点及びTPTのオン・オ
フ比を105 以上に大きく設定することができる点等
から有望視されている。半導体材料としてa−Si  
を用いた従来のTPTの構造を第3図(A) (B)に
断面図で示す。1はゲーlt、2はゲート絶縁膜、3は
a−Si半導体膜、4は絵素電極、5はソース電極、6
はドレイン電極である。このように絵素電極4とTFT
が連結されかつガラス基板上にマトリックス状に配列さ
れて一方の液晶セル基板が構成される。他方の液晶セル
基板には絵素電極4に対向する対向電極が形成されてお
り、両電極間に印加される電圧がTPTでスイッチング
される。
<Prior Art> In recent years, in large-capacity display devices using liquid crystals, research has been actively conducted on active polymer IJ Fuchs liquid crystal display devices in which TFTs are formed in the shape of an I-IJ sock on an insulating substrate. Half silicon (poly-5i) and amorphous silicon (a-5i) are used as semiconductor materials for TPT.
, tellurium selenium (CdSe) alloy, etc. In particular, since a-Si is generated at a relatively low temperature, it is possible to form a large number of TPTs on an inexpensive galanic substrate, and the on/off ratio of TPTs can be set to a large value of 105 or more. It is seen as promising. a-Si as a semiconductor material
The structure of a conventional TPT using 200 nm is shown in cross-sectional views in FIGS. 3(A) and 3(B). 1 is a gate electrode, 2 is a gate insulating film, 3 is an a-Si semiconductor film, 4 is a picture element electrode, 5 is a source electrode, 6
is the drain electrode. In this way, the picture element electrode 4 and TFT
are connected and arranged in a matrix on a glass substrate to form one liquid crystal cell substrate. A counter electrode facing the picture element electrode 4 is formed on the other liquid crystal cell substrate, and the voltage applied between both electrodes is switched by TPT.

〈発明が解決しようとする問題点〉 アクティブマI・リソクス型液晶表示装置を構成するT
PTの配列された基板において、データ信号を入力する
ソース電極の配線は液晶に十分な電圧を印加するため、
低抵抗の金属によって形成する必要があるか、ソース電
極として低抵抗のAl。
<Problems to be solved by the invention> T constituting the active material I/lithox type liquid crystal display device
In the substrate on which PTs are arranged, the wiring of the source electrode that inputs the data signal applies sufficient voltage to the liquid crystal.
It is necessary to form the source electrode with a low resistance metal or use low resistance Al as the source electrode.

A6−5i等を用いると次のような問題点が生じる。If A6-5i or the like is used, the following problems arise.

TPTが第3図CB)のような構造を有する場合、絵素
電極4として一般的に使用される透明導電膜(ITO膜
)を塩酸系エッチャントでエツチングすると、ITO膜
よりもAlO方がエンチング速度がはるかに大きいため
、TPTのチャネル長となるソース・ドレイン電極間の
距離を精度よくパターニングすることが困難であわ、エ
ツチング液の滲み込みのためA、l配線に断線が生ずる
危惧もあるという欠点が存する。一方、第3図(A)の
ように絵素電極4となるITO膜をパターニングした後
にソース配線を形成する方式では次の如き欠点が生じる
。まず第一にITO膜を被着するときにa−5i半導体
膜中にインジウム(In )が拡散し、特性及び信頼性
に悪影響を及ぼす。第二にAff又はAj?−5i膜を
被着するときにITO膜が変質することがある。第三に
Ae又はAn−5i膜とI’TO膜との密着性が悪くこ
の界面で剥離し易い。
When the TPT has a structure as shown in Figure 3 CB), when a transparent conductive film (ITO film) commonly used as the picture element electrode 4 is etched with a hydrochloric acid etchant, the etching rate of AlO is faster than that of the ITO film. Since the distance between the source and drain electrodes is much larger, it is difficult to accurately pattern the distance between the source and drain electrodes, which is the channel length of the TPT, and there is also the risk of disconnection in the A and L wirings due to seepage of the etching solution. exists. On the other hand, the method of forming the source wiring after patterning the ITO film which becomes the picture element electrode 4 as shown in FIG. 3(A) has the following drawbacks. First of all, when depositing the ITO film, indium (In) diffuses into the a-5i semiconductor film, which adversely affects the characteristics and reliability. Second, Aff or Aj? The ITO film may change in quality when depositing the -5i film. Thirdly, the adhesion between the Ae or An-5i film and the I'TO film is poor and they are likely to peel off at this interface.

TPT構造において、a−Siとソース・ドレイン間に
オーミック・コンタクトをとる目的でリンCP)ドープ
のa−3i膜をノンドープa −S i半導体膜とソー
ス・ドレイン電極間に介在させる方式が一般に採られて
いる。さらにリンドープのa−5i膜をノンドープミー
5i膜とソースドレイン電極間のみならずノンドープa
 −S i膜とITO膜の間あるいはITO膜とAI<
又はA6−5i)膜の間のうちいずれか一方にも介在さ
せることは可能である。しかし、リンドープのa−8i
膜をノンドープのa −S i膜とITO膜の間に介在
させる、!: A6 (又はA#−5i)膜、!:IT
O膜トノ密着性が悪くなるという問題点及びAl (又
はA#−5i膜)を被着するときA7?とITO膜が反
応してITO膜が変質するという問題が残る。又、リン
ドープa−5i嘆をITO嘆と1’ (又はA6−5i
)膜の間に介在させる構造では、ITO膜を被着すると
きa−5i膜とITO膜が反応し、a −5i膜中にI
nが拡散するという問題が残る。
In the TPT structure, a method is generally adopted in which a phosphorus (CP) doped a-3i film is interposed between the non-doped a-Si semiconductor film and the source/drain electrodes in order to establish ohmic contact between the a-Si and the source/drain. It is being In addition, a phosphorus-doped a-5i film is added not only between the non-doped me-5i film and the source-drain electrode, but also between the non-doped a-5i film and the source-drain electrode.
- Between Si film and ITO film or between ITO film and AI<
or A6-5i) It is possible to interpose it between either one of the films. However, phosphorus doped a-8i
A film is interposed between a non-doped a-Si film and an ITO film! : A6 (or A#-5i) membrane,! :IT
Problems with poor adhesion of O film and A7 when depositing Al (or A#-5i film)? There remains the problem that the ITO film reacts with the ITO film and the ITO film changes in quality. Also, lindope a-5i is ITO and 1' (or A6-5i
) In the structure in which the ITO film is interposed between the films, when the ITO film is deposited, the a-5i film and the ITO film react, and the ITO film is deposited in the a-5i film.
The problem remains that n is diffused.

く問題点を解決するための手段〉 本発明は絵素電極形成後にTPTのソース・ドレイン電
極を形成したTPT付加方式アクティブマ) IJソッ
クス動用液晶セル基板を有する液晶表示装置において前
述の欠点を除去することを企図するものである。すなわ
ち例えばPドープのa−5i膜をノンドープのa−5i
膜とソース・ドレイン電憧の間に介在させるとともにI
TO膜とソース・ドレイン電極となるAI(又はA6−
3i)膜等の金属膜との間にも介在させてITO膜と金
属膜即ちANとの反応を阻止するとともに、ノンドープ
のa −S i膜とITO膜との間に絶縁膜を介在させ
てノンドープのa −S i膜とITO膜との反応を阻
止し、TPTの特性及び信頼性の向上化を図ったもので
ある。
Means for Solving the Problems> The present invention eliminates the above-mentioned drawbacks in a liquid crystal display device having a TPT-added type active material in which TPT source/drain electrodes are formed after forming pixel electrodes. It is intended to do so. That is, for example, a P-doped a-5i film is replaced with a non-doped a-5i film.
Interposed between the film and the source/drain electrode, and
TO film and AI (or A6-
3i) An insulating film is also interposed between the non-doped a-Si film and the ITO film to prevent the reaction between the ITO film and the metal film, that is, AN, by interposing it between the ITO film and the metal film such as AN. This is intended to prevent the reaction between the non-doped a-Si film and the ITO film and improve the characteristics and reliability of TPT.

〈実施例1〉 第1図(A) (B) (C)は本発明の1実施例の説
明に供するTPT付加液晶セル基板の製造工程図である
<Example 1> FIGS. 1A, 1B, and 1C are manufacturing process diagrams of a TPT-added liquid crystal cell substrate for explaining one example of the present invention.

本実施例の液晶表示装置はツィヌテッドネマテインク液
晶等の電界効果型液晶を封入した液晶表示セルを基本と
し、一方のセル基板にマ) IJソックス状絵素電極を
配置し、各絵素電極の一端にTPTスイッチング素子を
連結して絵素単位のマトリックス表示パターンを生起す
るTPT付加方式によって駆動される。
The liquid crystal display device of this embodiment is based on a liquid crystal display cell in which a field effect liquid crystal such as a twinned nematic liquid crystal is sealed, and an IJ sock-like pixel electrode is arranged on one cell substrate, and each pixel It is driven by a TPT addition method in which a TPT switching element is connected to one end of an electrode to generate a matrix display pattern in units of picture elements.

先ず第1図(A)に示す如くガラス、プラスチック等の
透明基板上にスパッタリングによりタンク/L/(Ta
)を200OA堆積し、ホトリソグラフイーにて所定の
パターンに形成してゲー) i 極11とする。次にゲ
ート絶縁膜として全面に第一の窒化シリコ7 (Si3
N4 )膜12を2000A重畳し、引き続いてノンド
ープa−5i膜13をプラズマCVD装置により150
0A堆積した後、ホ) IJソゲラフイーにてa−5i
膜13を島状に成形する。その後、全面に第二の窒化シ
リコン(S l 3N4)膜14を50OA、透明導電
膜としてITO膜15を蒸着法により200OA堆積す
る。次に、第1図CB)に示す如く、ホトリソグラフィ
ーにてITO膜15と窒化シリコン嘆14を所定のパタ
ーンに成形し、ITO膜15で絵素電極を構成する。そ
の後第1図(C)に示す如く全面にリン(P)ドープの
a−5i膜16をプラズマCVD装置によシ500A、
l?−5i膜17をヌバッタリングによ、? 3000
A堆積し、ホトリソグラフィーにてA6−5i膜17と
リンドープのa−5illi116を所定のパターンに
成形してソース電極18及びドレイン電極19とする。
First, as shown in FIG. 1(A), a tank /L/(Ta) is deposited on a transparent substrate such as glass or plastic by sputtering.
) was deposited to a thickness of 200 OA and formed into a predetermined pattern using photolithography to form the gate electrode 11. Next, a first silicon nitride 7 (Si3
N4) The film 12 is superimposed by 2000A, and then the non-doped a-5i film 13 is deposited by 150A using a plasma CVD device.
After depositing 0A, e) a-5i at IJ Sogerahui.
The membrane 13 is formed into an island shape. Thereafter, a second silicon nitride (S 1 3N4) film 14 of 50 OA is deposited on the entire surface, and an ITO film 15 of 200 OA as a transparent conductive film is deposited by vapor deposition. Next, as shown in FIG. 1CB), the ITO film 15 and the silicon nitride layer 14 are formed into a predetermined pattern by photolithography, and the ITO film 15 constitutes a picture element electrode. Thereafter, as shown in FIG. 1(C), a phosphorus (P) doped a-5i film 16 is formed on the entire surface using a plasma CVD apparatus.
l? -5i film 17 by Nubatta ring? 3000
A6-5i film 17 and phosphorus-doped A-5illi film 116 are formed into a predetermined pattern by photolithography to form a source electrode 18 and a drain electrode 19.

以上により透明基板上に絵素電極の連結されたTPTが
形成される。このTPTはゲート電極11,5i3Nn
嘆12から成るゲート絶縁膜、ノンドー1a −S i
膜13から成る半導体膜、l?−81膜17から成るソ
ース電極18及び同様にAj?−3i膜17から成るド
レイン電極19で構成され、ドレイン電極19がIT’
O膜15から成る絵素電極の片端に重畳されて重電的に
接続されている。
Through the above steps, a TPT with connected picture element electrodes is formed on the transparent substrate. This TPT is the gate electrode 11,5i3Nn
Gate insulating film consisting of 12, non-do 1a -S i
A semiconductor film consisting of film 13, l? -81 film 17 and similarly Aj? -3i film 17, and the drain electrode 19 is IT'
It is superimposed on one end of a picture element electrode made of an O film 15 and connected in a heavy electrical manner.

ドレイン電極19と絵素電極及び半導体膜の接合部には
Pドープa−5i膜16が介在し、ITO膜15とAg
−5i膜17の反応が阻止されかつオーミックコンタク
トが得られる。ノンドープa ’−S i膜13の半導
体膜と絵素電極のITO膜15の間には第二のSi3N
4膜14が介在しておシ、従ってITO膜1膜中5中n
が半導体膜中に拡散することはなくTPTの特性劣化は
生じない。
A P-doped a-5i film 16 is interposed at the junction between the drain electrode 19, the pixel electrode, and the semiconductor film, and the ITO film 15 and the Ag
-5i film 17 reaction is prevented and ohmic contact is obtained. A second Si3N layer is formed between the semiconductor film of the non-doped a'-Si film 13 and the ITO film 15 of the picture element electrode.
4 films 14 are interposed, therefore, n in 5 in 1 ITO film 1 is interposed.
does not diffuse into the semiconductor film, and the characteristics of TPT do not deteriorate.

上記の如きTPTと絵素電極を透明基板上にマトリック
ヌ状に配列し、TPTのゲート電極を縦方向に共通接続
してゲート配線を形成するとともにソース電極を横方向
に共通接続してソース配線を形成する。ソース配線を介
して信号を供給しゲート配線を介してスイッチング電圧
を印加することにより各TPTが個別にスイッチングさ
れる。
TPTs and picture element electrodes as described above are arranged in a matrix on a transparent substrate, and the gate electrodes of the TPTs are commonly connected vertically to form a gate wiring, and the source electrodes are commonly connected horizontally to form a source wiring. Form. Each TPT is individually switched by supplying a signal through the source wiring and applying a switching voltage through the gate wiring.

この透明基板に対向して各絵素電極に共通の共通対向電
極が形成された対向基板を配し、その間隙に電界効果型
液晶を封入することにより液晶表示装置が作製される。
A liquid crystal display device is manufactured by disposing a counter substrate on which a common counter electrode common to each picture element electrode is formed opposite to this transparent substrate, and filling a field-effect liquid crystal in the gap between the counter substrates.

TPTのスイッチング動作に呼応してドレイン電極より
絵素電極と共通電極間の液晶に駆動電圧が印加され、マ
) IJソックスの液晶表示が実行される。
In response to the switching operation of the TPT, a driving voltage is applied from the drain electrode to the liquid crystal between the picture element electrode and the common electrode, and a) liquid crystal display of the IJ socks is performed.

〈実施例2〉 第2図(A) (B) (C)は本発明の他の実施例の
説明に供するTPT付加液晶セル基板の製造工程図であ
る。
<Example 2> FIGS. 2A, 2B, and 2C are manufacturing process diagrams of a TPT-added liquid crystal cell substrate for explaining another example of the present invention.

第2図(A)に示すクロく透明基板上にタンタルを20
0OA堆積し、ホトリソグラフィーにて所定のパターン
に形成してゲート電極21とする。次に全面に第一の窒
化シリコンi22ヲ2000k。
20 pieces of tantalum are placed on a black transparent substrate as shown in Figure 2 (A).
0OA is deposited and formed into a predetermined pattern by photolithography to form the gate electrode 21. Next, apply the first silicon nitride i22 2000k to the entire surface.

ノンドープのa −S i膜23を15ooA、@二の
窒化シリコン膜24を500^堆積し、ホトリソグラフ
ィーにて第二の窒化シリコン膜24及びノンドープのa
 、7 S i膜23を所定のパターンに形成する。そ
の後第2図CB)に示す如く全面にITO膜25を30
00A堆積しITO膜25の絵素電極となる面上にレジ
スト26をパターンニングする。次いでレジスト膜26
をマスクとしてITO膜25.第二の窒化シリコン膜2
4をエンチングし、第2図(C)に示すように成形する
。このとき第一の窒化シリコン膜22も若干工7チング
されることがあるがTPTの特性上問題は生じない。そ
の後、レジスト膜26を除去し、第2図CD)に示す如
く全面にリンドープのa−3i膜27た後、ホトリソグ
ラフィーにてA(1−5i膜28とリンドープのa−5
i膜27を所定のパターンに成形し、ソース電極29及
びドレイン電極30とする。以上によI)ITO膜25
から成る絵素電極が連結されたTPTが透明基板上に形
成される。このTPTは透明基板上にマ) IJンクス
状に配列され、上述した実施例1と同様の液晶表示装置
が作製される。
A non-doped a-Si film 23 was deposited at a thickness of 150 A, and a second silicon nitride film 24 was deposited at a thickness of 500 A, and the second silicon nitride film 24 and a non-doped a-Si film 24 were deposited by photolithography.
, 7 The Si film 23 is formed in a predetermined pattern. After that, as shown in Fig. 2 CB), an ITO film 25 is applied for 30 minutes over the entire surface.
A resist 26 is patterned on the surface of the 00A deposited ITO film 25 that will become a picture element electrode. Next, the resist film 26
ITO film 25. is used as a mask. Second silicon nitride film 2
4 is etched and shaped as shown in FIG. 2(C). At this time, the first silicon nitride film 22 may also be slightly etched, but this does not cause any problem in terms of the characteristics of TPT. Thereafter, the resist film 26 was removed and a phosphorus-doped a-3i film 27 was formed on the entire surface as shown in FIG.
The i film 27 is formed into a predetermined pattern to form a source electrode 29 and a drain electrode 30. Based on the above I) ITO film 25
A TPT to which picture element electrodes consisting of are connected is formed on a transparent substrate. The TPTs are arranged in a matrix on a transparent substrate to produce a liquid crystal display device similar to that of Example 1 described above.

〈発明の効果〉 以上詳説した如く、TFTのa −S i膜と絵素電極
のITO膜の間に絶縁摸を介在させ、a −5i膜とソ
ース・ドレイン電極の間及びITO膜とソース・ドレイ
ン電極の間にリンドープのa −S i膜を介在させる
ことにより、動作特性及び信頼性のよい薄膜トランシス
クアクティブマトリクス型液晶表示装置を製作すること
ができる。尚、本発明はソース電極の金属がA1.Ti
、Mo等他の金属材料の場合でも同様に適用できる。
<Effects of the Invention> As explained in detail above, an insulating film is interposed between the a-Si film of the TFT and the ITO film of the picture element electrode, and the insulation film is interposed between the a-5i film and the source/drain electrode and between the ITO film and the source/drain electrode. By interposing a phosphorus-doped a-Si film between the drain electrodes, a thin film transisc active matrix liquid crystal display device with good operating characteristics and reliability can be manufactured. Note that in the present invention, the metal of the source electrode is A1. Ti
, Mo, and other metal materials can be similarly applied.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図はそれぞれ本発明の1実施例の説明に
供する液晶表示装置のTPT付加基板の要部製造工程図
である。 第3図は従来のTPT付加基板の断面図である。 11.21・・・ゲート電極  12.22・・・第1
の窒化シリコン膜  13.23・・・a −S i膜
(ノンドープ)   14.24・・・第2の窒化シリ
コン膜   15.25−ITO膜   16.27−
a−S i膜(リンドープ)   17.28・−・A
l −3i膜  18,29・・・ソース電極  19
.30・・・ドレイン電極 代理人 弁理士  福 士 愛 彦(他2名)37  
図 第3図 第2図
FIGS. 1 and 2 are manufacturing process diagrams of essential parts of a TPT-added substrate of a liquid crystal display device, respectively, for explaining one embodiment of the present invention. FIG. 3 is a sectional view of a conventional TPT-added substrate. 11.21... Gate electrode 12.22... First
Silicon nitride film 13.23...a - Si film (non-doped) 14.24... Second silicon nitride film 15.25-ITO film 16.27-
a-S i film (phosphorous doped) 17.28・-・A
l -3i film 18, 29...source electrode 19
.. 30... Drain electrode agent Patent attorney Aihiko Fukushi (and 2 others) 37
Figure 3Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1、セル基板の一方に透明導電膜の絵素電極を配列し、
各絵素電極に連結した薄膜トランジスタを形成して成る
液晶表示装置において、前記薄膜トランジスタの半導体
膜をアモルファスシリコンで構成するとともに該半導体
膜と前記絵素電極の重畳部位に絶縁膜を介在させかつ前
記薄膜トランジスタのソース・ドレイン電極と前記半導
体膜の間にリンドープアモルファスシリコン膜を介在さ
せたことを特徴とする液晶表示装置。
1. Arrange pixel electrodes made of transparent conductive film on one side of the cell substrate,
In a liquid crystal display device comprising a thin film transistor connected to each picture element electrode, a semiconductor film of the thin film transistor is made of amorphous silicon, an insulating film is interposed between the semiconductor film and the picture element electrode, and the thin film transistor A liquid crystal display device characterized in that a phosphorus-doped amorphous silicon film is interposed between the source/drain electrodes and the semiconductor film.
JP60190852A 1985-08-27 1985-08-27 Liquid crystal display device Pending JPS6247621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60190852A JPS6247621A (en) 1985-08-27 1985-08-27 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60190852A JPS6247621A (en) 1985-08-27 1985-08-27 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPS6247621A true JPS6247621A (en) 1987-03-02

Family

ID=16264845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60190852A Pending JPS6247621A (en) 1985-08-27 1985-08-27 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPS6247621A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455926U (en) * 1987-10-01 1989-04-06
JPH0687105U (en) * 1993-06-07 1994-12-20 敬一郎 野邊 Multicolored seatbelts including luminescent zones

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455926U (en) * 1987-10-01 1989-04-06
JPH0687105U (en) * 1993-06-07 1994-12-20 敬一郎 野邊 Multicolored seatbelts including luminescent zones

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