JPS6245849U - - Google Patents
Info
- Publication number
- JPS6245849U JPS6245849U JP13682385U JP13682385U JPS6245849U JP S6245849 U JPS6245849 U JP S6245849U JP 13682385 U JP13682385 U JP 13682385U JP 13682385 U JP13682385 U JP 13682385U JP S6245849 U JPS6245849 U JP S6245849U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor device
- line
- insulating case
- bypass capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案による半導体装置の一実施例を
示す要部破断斜視図、第２図は従来の半導体装置
を示す要部破断斜視図である。 １……絶縁性ケース、２……ＬＳＩ、３……ボ
ンデイングパツド、４……外部接続端子、５……
電源接続端子、５ａ……電源リード部、６……ア
ースリード部、７……バイパスコンデンサ、８…
…ボンデイングパツド、９ａ，９ｂ……バイパス
コンデンサ接続用リード部。
示す要部破断斜視図、第２図は従来の半導体装置
を示す要部破断斜視図である。 １……絶縁性ケース、２……ＬＳＩ、３……ボ
ンデイングパツド、４……外部接続端子、５……
電源接続端子、５ａ……電源リード部、６……ア
ースリード部、７……バイパスコンデンサ、８…
…ボンデイングパツド、９ａ，９ｂ……バイパス
コンデンサ接続用リード部。
Claims (1)
- 集積回路を内蔵した絶縁性ケースの内部に独立
した一対のリード部を設け、該リード部の一端に
バイパスコンデンサを接続し、その他端側を集積
回路上に互いに隣接して設けた電源ライン、アー
スラインのボンデイングパツドにボンデイングワ
イヤを介して接続したことを特徴とする半導体装
置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13682385U JPS6245849U (ja) | 1985-09-09 | 1985-09-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13682385U JPS6245849U (ja) | 1985-09-09 | 1985-09-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6245849U true JPS6245849U (ja) | 1987-03-19 |
Family
ID=31040296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13682385U Pending JPS6245849U (ja) | 1985-09-09 | 1985-09-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6245849U (ja) |
-
1985
- 1985-09-09 JP JP13682385U patent/JPS6245849U/ja active Pending