JPS6243937A - Line diagnosing device - Google Patents

Line diagnosing device

Info

Publication number
JPS6243937A
JPS6243937A JP60183002A JP18300285A JPS6243937A JP S6243937 A JPS6243937 A JP S6243937A JP 60183002 A JP60183002 A JP 60183002A JP 18300285 A JP18300285 A JP 18300285A JP S6243937 A JPS6243937 A JP S6243937A
Authority
JP
Japan
Prior art keywords
data
dce
circuit
transmission
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60183002A
Other languages
Japanese (ja)
Inventor
Kazuyuki Yokota
和之 横田
Yasuo Horie
堀江 康雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60183002A priority Critical patent/JPS6243937A/en
Publication of JPS6243937A publication Critical patent/JPS6243937A/en
Pending legal-status Critical Current

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  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To generate simply an abnormal state and an abnormal sequence on a protocol by providing a synchronizing inspection circuit for a transmission data and a reception data flowing to an interface and a transmission circuit for the transmission data or the reception data and a data block processing circuit. CONSTITUTION:When a transmission data is inputted from a DTE and start-stop synchronization is applied by the synchronization inspection circuit 6, after the parity is checked by a parity checker 9, the data is transferred to a processing circuit 7 and stored in a memory 10. Then the data stored in the memory 10 is sent to a DCE via a transmission circuit 8 normally. In conducting the protocol test, a processor 11 applies the deletion, insertion, or change of the data, the result is sent from the transmission circuit 8 to the DCE or the data is not sent to the DCE. The processing along with the test condition as above is applied and the system is used to test various protocol as a line diagnosing device. Further, similar function is applied as to the reception data from the DCE.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、データ通信機器におけるプロトコル試験、通
信上の障害試験等に使用する回線診断装置に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a line diagnostic device used for protocol testing, communication fault testing, etc. in data communication equipment.

(従来の技術) 従来、日本工業規格のC−6361で規定されている「
モデムと通信制御装置及びデータ端末装置とのインタフ
ェース」に基づき、調歩同期方式によって通信を行う通
信システムのモデムと通信制御装置又はモデムとデータ
端末装置との間に位置して、そのインタフェースに流れ
る信号でそれぞれの装置に接続される〔第3図(a)及
び(b)参照〕回線診断装置は、通信制御装置又はデー
タ端末装置(以下DTEという)とモデム(以下DEC
という)との間のインタフェースに流れる信号に何ら擾
乱を与えることなくその信号をモニタして陰極線管(以
下CRTという)の画面に表示したり、メモリに取り込
む等の機能を備えている。
(Prior art) Conventionally, "
A signal that is located between a modem and a communication control device or a modem and a data terminal device in a communication system that performs communication using the start-stop synchronization method based on the ``interface between a modem and a communication control device and a data terminal device,'' and that flows through that interface. [See Figure 3 (a) and (b)] The line diagnostic equipment is connected to each device at the communication control equipment or data terminal equipment (hereinafter referred to as DTE) and modem (hereinafter referred to as DEC).
It has functions such as monitoring the signals flowing through the interface between the CRT and the CRT and displaying the signals on the screen of a cathode ray tube (hereinafter referred to as CRT) or importing them into memory.

第4図は従来の回線診断装置の構成を示すもので、DT
EとDCEとの間に挿入したインタフェースユニット1
から取り込んだ送信データ及び受信データとの同期をと
るためのフレーミング回路2によってデータブロック毎
に受信して、データキャプチャメモリ3に格納する。そ
して、このデータブロックをビデオRAMを内蔵したC
RTコントロール回路4に転送してCRT5の画面に回
線上の信号を表示することにより、その内容全監視した
り、プロトコル試験等に使用することができるもので、
この動作を図で簡略に示すと第5図のようになる。
Figure 4 shows the configuration of a conventional line diagnostic device.
Interface unit 1 inserted between E and DCE
Each data block is received by a framing circuit 2 for synchronizing with the transmitted data and received data taken in from the data block, and is stored in the data capture memory 3. Then, this data block is stored in a C
By transmitting the signal on the line to the RT control circuit 4 and displaying it on the screen of the CRT 5, the entire contents can be monitored and used for protocol tests, etc.
This operation is briefly illustrated in FIG. 5.

(発明が解決しようとする問題点) しかしながら、データ通信機器を対向接続して、プロト
コル試験を行う場合、正常なグロトコルシーケンスを発
生させての試験は問題なくできるが、異常なグロトコル
シーケンスを発生させての試験はでき々いという問題が
あった。
(Problem to be Solved by the Invention) However, when performing a protocol test by connecting data communication devices face-to-face, the test can be performed by generating a normal protocol sequence without any problem, but the test can be performed by generating an abnormal protocol sequence. There was a problem in that it was difficult to conduct a test by causing the problem to occur.

本発明は、このよう々問題を解決するためになされたも
ので、プロトコル上の異常状態、異常シーケンスを簡単
に発生できる回線診断装置を提供することを目的とする
ものである。
The present invention has been made to solve these problems, and an object of the present invention is to provide a line diagnostic device that can easily generate abnormal states and abnormal sequences in the protocol.

(問題全解決するための手段) 本発明は、インタフェースに流れる送信データ及び受信
データの同期検定回路、データブロックの処理回路及び
送信データ又は受信データの送信回路を備えたものであ
る。
(Means for Solving All Problems) The present invention includes a synchronization verification circuit for transmission data and reception data flowing through an interface, a data block processing circuit, and a transmission circuit for transmission data or reception data.

(作 用) DTEからの送信データ及びDCEからの受信データを
同期検定回路に通して、データブロック全検出した上、
そのデータをメモリに格納し、且つ、そのデータに対し
て削除、挿入、変更等の処理を行ったり、データブロッ
クの削除、新規追加、部分変更、無処理中継等を行って
送信データとしてDCEに、受信データとしてDTEに
それぞれ送出できるので、DTEからの送信データ或い
はDCEからの受信データを流れるデータブロックの全
体削除、部分変更、一定時間遅延等を行った送信データ
全DCEに送信したり、同様の処理を行った受信データ
をDTEに送信することによって、プロトコルシーケン
ス上の異常状態を容易に発生することができる。
(Function) After passing the transmission data from the DTE and the reception data from the DCE through the synchronization verification circuit and detecting all the data blocks,
The data is stored in memory, and the data is processed by deletion, insertion, modification, etc., data block deletion, new addition, partial modification, unprocessed relaying, etc., and sent to the DCE as transmission data. , each can be sent to the DTE as received data, so it is possible to completely delete, partially change, or delay a certain period of data blocks flowing from the transmitted data from the DTE or the received data from the DCE, and send the transmitted data to all the DCEs, etc. By transmitting the processed received data to the DTE, an abnormal state in the protocol sequence can be easily generated.

(実施例) 第1図は、本発明の一実施例の構成を示すもので、DT
Eからの送信データ信号の処理系統及びDCEからの受
信データ信号の処理系統に同期検定回路6、処理回路7
及び送信回路8が挿入されており、送信データ信号或い
は受信データ信号を加工することができる。
(Embodiment) FIG. 1 shows the configuration of an embodiment of the present invention.
A synchronization verification circuit 6 and a processing circuit 7 are included in the processing system for the transmission data signal from E and the processing system for the reception data signal from DCE.
A transmission circuit 8 is inserted, and the transmission data signal or the reception data signal can be processed.

このように構成された本実施例では、DTEから送信デ
ータが入力して、同期検定回路6で調歩同期がとられる
と、パリティチェッカ9でパリティチェックされた後、
そのデータが処理回路7に転送されてメモリ10に格納
される。そして、メモリ10に格納されたデータは、通
常、送信回路8を経てDCEに送出されるが、プロトコ
ル試験等を行うときには、プロセッサ11によってデー
タの削除、挿入、変更等を施して送信回路8からDCE
へ送出したり、データi DCEに送出しないようにす
る等の試験条件に沿った処理を行い、回線診断装置とし
て各種のプロトコル試験等に使用できる。
In this embodiment configured as described above, when transmission data is input from the DTE and start-stop synchronization is established in the synchronization verification circuit 6, the parity checker 9 performs a parity check, and then
The data is transferred to the processing circuit 7 and stored in the memory 10. The data stored in the memory 10 is normally sent to the DCE via the transmitting circuit 8, but when performing a protocol test or the like, the data is deleted, inserted, modified, etc. by the processor 11 and sent from the transmitting circuit 8. DCE
It performs processing in accordance with test conditions, such as sending data to the iDCE or not sending it to the data i DCE, and can be used as a line diagnostic device for various protocol tests.

尚、DCEからの受信データについても同様に機能する
Note that the same function applies to data received from the DCE.

(発明の効果) 以上説明したように、本発明によれば、DTEとDCE
との間のインタフェースに流れる信号に対するデータブ
ロックレベルでの加工を可能とし、フレームの削除、フ
レーム内データの変更等ができるという効果がある。
(Effect of the invention) As explained above, according to the present invention, DTE and DCE
It is possible to process the signal flowing through the interface between the two at the data block level, and it has the effect of allowing frames to be deleted, data within the frame to be changed, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の概略ブロック図、第2図は
本発明における信号処理系統図、第3図(a)はDTE
とDCEとの接続系統を示す図、第3図(bJはDTE
とDCEの間に回線診断装置を接続したときの系統図、
第4図は従来の回線診断装置の概略ブロック図、第5図
は従来の回線診断装置における信号処理系統図である。 6・・・同期検定回路、7・・・処理回路、8・・・送
信回路。 第1図 第2図
FIG. 1 is a schematic block diagram of an embodiment of the present invention, FIG. 2 is a signal processing system diagram in the present invention, and FIG. 3(a) is a DTE
Figure 3 shows the connection system between and DCE (bJ is DTE
System diagram when a line diagnostic device is connected between and DCE,
FIG. 4 is a schematic block diagram of a conventional line diagnostic device, and FIG. 5 is a signal processing system diagram in the conventional line diagnostic device. 6... Synchronization verification circuit, 7... Processing circuit, 8... Transmission circuit. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 調歩同期方式によって通信を行う通信システムのモデム
と通信制御装置又はモデムとデータ端末装置との間に位
置して、そのインタフェースに流れる信号でそれぞれの
装置を接続する回線診断装置において、前記データ端末
装置からの送信データと調歩同期をとりながらデータキ
ャラクタ並びにデータブロックを受信したり、前記モデ
ムからの受信データと調歩同期をとりながらデータキャ
ラクタ並びにデータブロックを受信する同期検定手段と
、受信したデータブロック内のデータ等をメモリに格納
すると共に、前記メモリに格納した前記データ等に削除
、挿入、変更等の処理を施す処理手段と、前記メモリ内
のデータを送信データとして前記モデムに送出したり、
前記メモリ内のデータを受信データとして前記データ端
末装置に送出する送出手段とが具備されていることを特
徴とする回線診断装置。
In a line diagnostic device that is located between a modem and a communication control device or a modem and a data terminal device in a communication system that performs communication using a start-stop synchronization method, and connects each device with a signal flowing through the interface, the data terminal device synchronization verification means for receiving data characters and data blocks in start-stop synchronization with data transmitted from the modem, and receiving data characters and data blocks in start-stop synchronization with data received from the modem; processing means for storing data, etc. in a memory and performing processing such as deletion, insertion, modification, etc. on the data stored in the memory; and a processing means for transmitting the data in the memory as transmission data to the modem;
A line diagnostic device comprising: sending means for sending the data in the memory as received data to the data terminal device.
JP60183002A 1985-08-22 1985-08-22 Line diagnosing device Pending JPS6243937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60183002A JPS6243937A (en) 1985-08-22 1985-08-22 Line diagnosing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60183002A JPS6243937A (en) 1985-08-22 1985-08-22 Line diagnosing device

Publications (1)

Publication Number Publication Date
JPS6243937A true JPS6243937A (en) 1987-02-25

Family

ID=16128036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60183002A Pending JPS6243937A (en) 1985-08-22 1985-08-22 Line diagnosing device

Country Status (1)

Country Link
JP (1) JPS6243937A (en)

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