JPH11168527A - Transmission line fault detection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the transmission line fault detection system by which a fault is concretely classified and a real status of the fault is grasped. SOLUTION: In the transmission line fault detection system, micro processors in a host device 101 and a terminal equipment 201 provide an output of an operation instruction signal to inform an opposite party of a line fault in the case of error detection in communication data at reception circuits 103, 203 respectively. Control signal transmission reception circuits 105, 205 generate and output a control signal for the test of a line fault depending on contents of the fault based on the operation instruction signal to an opposite party via an exclusive control line. Test circuits 104, 204 generate and output test data in response to the fault contents denoted by the control signal according to the operation instruction signal to identify and test the contents of the line fault. For example, the test circuits 104, 204 regard the fault as a line short- circuit when data received by the opposite party resulting from transmission of the test data are all zero.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly performs error detection and error-free data transfer when bidirectional communication is performed through transmission and reception of differential signals through data encoding and level conversion on a transmission line. The present invention relates to a transmission line fault detection system applied to a bidirectional transmission system, and more particularly, to a transmission line fault detection system having a function of detecting an error based on generated test data and isolating a fault.

[0002]

2. Description of the Related Art Conventionally, in this type of transmission line fault detection system, when performing bidirectional communication between a terminal device and a higher-level device that accommodates the terminal device via a transmission line, error detection is performed by error detection means, and retransmission is performed. Error-free data transfer is performed by the means described above. As a well-known technique related to such a system, for example, Japanese Patent Application Laid-Open No. 62-2414
In the circuit test method disclosed in Japanese Patent Publication No. 52, a means for generating predetermined test data and error message data in a data terminal and an exchange accommodating the data terminal, and a means for comparing and comparing the generated data with the received data are provided. Provided.

In this circuit test method, test data sent from the terminal device to the exchange is compared with correct test data in the exchange, and the test data sent from the exchange to the terminal device is correct in the data terminal. It is compared with the test data, but as a result, only when the test data sent from either the terminal device or the exchange to the other matches the test data generated in the other, the data is changed from the other to the one. The test data is transmitted, and such communication is repeated. If there is a mismatch as a result of the comparison and collation, error message data is sent to the other one, whereby it is determined whether a failure has occurred in the uplink or the downlink. .

[0004]

In the case of the above-described line test system (transmission line fault detection system), if there is a defect such as a broken pair on the transmission line, the line fault is detected and the direction is determined. For example, specific failures such as which of a transmission circuit and a reception circuit commonly provided in a terminal device or a higher-level device (exchange) is defective, whether a transmission line is disconnected, or whether a pair is actually broken. There is a problem that it is not possible to perform the isolation and it is not possible to grasp the actual condition of the failure.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a technical problem thereof is to detect a transmission line failure capable of identifying a specific failure and grasping the actual condition of the failure. It is to provide a system.

[0006]

According to the present invention, there is provided a transmission circuit and a reception circuit for performing transmission and reception, respectively, in bidirectional communication between a terminal device and a higher-level device which accommodates the terminal device via a transmission line. In a transmission line fault detection system for detecting an error based on test data generated in each of the higher-level device and the terminal device and isolating the fault, the terminal device and the higher-level device perform line detection when detecting error in communication data in a receiving circuit. A microprocessor for outputting an operation instruction signal for notifying the partner apparatus of the failure, and a control signal for testing a line failure according to the content of the failure in accordance with the operation instruction signal, and outputting the control signal via a dedicated control line Control signal transmission / reception circuit for transmission to the partner device Transmission line fault detection system comprising a test circuit for identifying test the contents of the generated output to line fault is obtained.

According to the present invention, in the transmission path failure detection system, the microprocessor stops the bidirectional communication data transmission and reception in the transmission circuit and the reception circuit after outputting the operation instruction signal, and operates the test circuit. Thus, a transmission path failure detection system is obtained.

Further, according to the present invention, in the above-mentioned transmission line fault detection system, the test circuit is configured to consider a line short when all the received data in the partner device due to the transmission of the test data is zero. Is obtained.

[0009] In addition, according to the present invention, in any of the above transmission line fault detection systems, the test circuit may be arranged so that the reception level of the other device by transmitting the test data is equal to or less than a predetermined level range. If this is the case, a transmission path failure detection system that can be regarded as line disconnection can be obtained.

According to the present invention, in any one of the above transmission line fault detection systems, the test circuit disconnects the transmission line by setting the transmission line to high impedance when transmitting test data. A transmission path fault detection system is provided which amplifies the test data in a receiving circuit of the apparatus and detects a pair break on the transmission line based on the presence or absence of a pulse and the magnitude of crosstalk.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A transmission line fault detection system according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a basic configuration of a transmission line fault detection system according to one embodiment of the present invention.
In this transmission path failure detection system, a terminal device 201 is accommodated in a host device 101 via a transmission line 301, and the host device 101 includes a transmission circuit 102 and a reception circuit 10
3, the terminal device 201 has a test circuit 104, a control signal transmission / reception circuit 105, and a microprocessor 106, and the terminal device 201 has the same configuration as the transmission circuit 202, the reception circuit 203, the test circuit 204, the control signal transmission / reception circuit 205, and the microprocessor 206. have.

The transmission circuit 10 of the host device 101
2 and the receiving circuit 203 of the terminal device 201, and the terminal device 2
01 of the transmission circuit 202 and the reception circuit 1 of the host device 101
The control signal transmission / reception circuit 105 of the host device 101 and the control signal transmission / reception circuit 105 of the terminal device 201 are connected to each other via the transmission line 301. The microprocessor 106 of the higher-level device 101 is connected to the control signal transmission / reception circuit 105 to transmit and receive control signals, and is connected to the transmission circuit 102, the reception circuit 103, and the test circuit 104 to perform each control. Further, the test circuit 104 is connected to the transmission circuit 102 via the transmission data line 107 and is connected to the reception circuit 103 via the reception data line 108.

Similarly, the microprocessor 206 of the terminal device 201 is connected to the control signal transmission / reception circuit 205 to transmit and receive control signals, and is connected to the transmission circuit 202, the reception circuit 203, and the test circuit 204, respectively. Perform control. The test circuit 204 is connected to the transmission circuit 202 via the transmission data line 207 and to the reception circuit 203 via the reception data line 208.

In this transmission line fault detection system, when performing bidirectional communication between the terminal device 201 and the higher-level device 101 that accommodates the terminal device 201 via the transmission line 301, an error in communication data is detected to perform fault isolation. , The microprocessors 106 and 206 in the host device 101 and the terminal device 201 are connected to the receiving circuits 103 and 20 respectively.
3 to output an operation instruction signal for notifying the partner apparatus of the line failure when detecting an error in the communication data in step 3, so that the control signal transmitting / receiving circuits 105 and 205 test the line failure according to the contents of the failure in accordance with the operation instruction signal. The test circuits 104 and 204 generate and output test data in accordance with the operation instruction signal for each fault content indicated by the control signal, and generate and output a control signal. The content of the test is identified.

At this time, the microprocessors 106 and 2
06, the test circuits 104 and 204 stop transmitting and receiving bidirectional communication data between the transmission circuit 102 and the reception circuit 103 of the host device 101 and the transmission circuit 202 and the reception circuit 203 of the terminal device 201 after outputting the operation instruction signal. To work. The test circuits 104 and 204 regard the other party's reception data resulting from the transmission of the test data as a line short when all are zero, and if the reception level of the other party due to the transmission of the test data is below a predetermined level range. It is assumed that the line is disconnected. The test circuits 104 and 204
When transmitting the test data, the transmission line 301 is set to high impedance to disconnect the line, and the test data is amplified by the receiving circuit in the partner device, and the transmission line 30 is amplified based on the presence or absence of the pulse and the magnitude of the crosstalk.
1 is detected.

The operation of the transmission line fault detection system will be described in detail. Normally, the transmission circuit 102, the transmission line 301, the reception circuit 203 of the terminal device 201, and the reception data line 20
8, but in the reverse direction, from the transmission data line 207 of the terminal device 201 to the transmission circuit 202, the transmission line 301, the reception circuit 103 of the host device 101, and the reception data line 108. Data flows.

For example, when a data error is detected by the receiving circuit 103 of the host device 101 and it is determined that a line failure has occurred,
The microprocessor 106 of the higher-level device 101 transmits an operation instruction signal to the control signal transmission / reception circuit 105, and the control signal transmission / reception circuit 105 generates and outputs a control signal for testing a line failure according to the content of the failure according to the operation instruction signal. The control signal is transmitted to the microprocessor 206 through the control signal transmission / reception circuit 205 of the terminal device 201 facing the terminal device 201 via the transmission line 301 by a dedicated control line.

FIG. 2 shows control signal transmitting / receiving circuits 105 and 20.
5 illustrates a bit assignment of a test control signal corresponding to the failure content according to FIG. However, here test 1
Is a transmission circuit return test, Test 2 is a reception circuit return test, Test 3 is a line short test, Test 4 is a line disconnection test, and Test 5 is a pair break test.

These control signals are frame-synchronized by the host device 101, and the terminal device 2
01 is notified as line fault information. When the information of the line fault is notified to both the microprocessors 106 and 206 in this way, the transmission and reception of data in both directions are stopped, and the test circuits 104 and 204 are operated.

In the test circuit 204 of the terminal device 201,
The test circuit 10 sends the test data to the test circuit 10
If the received data is all zero for a certain period of time in step 4, it is considered that the differential signal is short-circuited because it does not become all zero because there is originally a flag pattern. That is, when the received data becomes zero for a certain period of time longer than the flag interval, this state can be detected as a line short.

The test circuit 204 of the terminal device 201
In transmitting test data, the transmission line is disconnected by the relay of the transmission circuit 202, the impedance of the transmission line is changed to high impedance, and the test data is amplified by the reception circuit 103 of the host device 101 to a level corresponding to the line length. At this time, the terminal device 2
The first transmitting circuit 202 operates to transmit the test data from the test circuit 204. Here, if there is no pair break in the transmission line 301, it is removed as in-phase noise and no pulse is generated. Therefore, if there is a pulse, it can be detected as a pair break.

Further, the reception levels of the receiving circuit 103 of the higher-level device 101 and the receiving circuit 203 of the terminal device 201 are within the same range with the same line length.
Test circuit 104 of the terminal device 201 from the test circuit 104 of
The test data is transmitted to the test circuit 104 of the host device 101 from the test circuit 204 of the terminal device 201.
4 transmits the test data to the receiving circuit 1 of the higher-level apparatus 101.
03, the reception level is detected. More specifically, information is added to the reception level bit of the control signal shown in FIG.
If there is a difference below a specific level range, it can be detected as line disconnection. By the way, since the level is about 1/2 in the case of one-line disconnection and 0 level in the case of all-line disconnection, the transmission line 301 can be examined using this as a guide to remove the line fault.

When the terminal device 201 detects a line fault, the same operation may be performed in the opposite direction, so that the up / down state of the transmission line 301 can be tested. If the transmission circuits 102 and 202 and the reception circuits 103 and 203 are provided with a loopback test function, the normality of each of these circuits can be tested.

FIG. 3 is a flow chart showing an example of the test operation processing by the transmission path failure detection system.
Here, when the line failure is detected by any of the receiving circuits 103 and 203 (step S1), the test circuit is activated (step S2), and the success or failure of the transmission circuit return test failure detection is determined as a test order (step S3). ), Success / failure judgment of failure detection of receiving circuit loopback test (step S
After confirming the normality of each circuit by performing 4), the success / failure determination of the line short test short detection (step S5) and the success / failure determination of the line disconnection test line disconnection (step S6) are performed to perform the physical normality of the line. Finally, a pair failure test is performed to determine the success or failure of the pair failure detection (step S7), and in the case of any of the success / failure determination results, if a detection state is detected, an alarm is notified (step S9). If there is, it shifts to the normal operation (step S8).

However, if the line test is performed by using the test operation bit and the test response bit of the control signal shown in FIG. Alarm can be notified to the host device 101. If the test results are displayed on a maintenance terminal, for example, the host device 1
01, the terminal device 201, and the transmission line 301 can be isolated, and the cause can be easily investigated and recovered.

[0027]

As described above, according to the transmission path failure detection system of the present invention, a microprocessor for outputting an operation instruction signal for notifying a partner side of a line failure when detecting an error in communication data, A control signal transmitting / receiving circuit for generating and outputting a control signal in accordance with the operation instruction signal and transmitting a line fault to the other party through a dedicated control line; and a test circuit generating and outputting test data in accordance with the operation instruction signal to generate a line fault. Is identified, it is possible to isolate a specific failure, and it is possible to grasp the actual state of the failure.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a transmission path failure detection system according to one embodiment of the present invention. .

FIG. 2 illustrates a bit assignment of a test control signal according to a failure content in a control signal transmission / reception circuit provided in the transmission path failure detection system shown in FIG.

FIG. 3 is a flowchart illustrating an example of a test operation process performed by the transmission path failure detection system illustrated in FIG. 1;

[Explanation of symbols]

 Reference Signs List 101 Upper device 102, 202 Transmission circuit 103, 203 Reception circuit 104, 204 Test circuit 105, 205 Control signal transmission / reception circuit 106, 206 Microprocessor 107, 207 Transmission data line 108, 208 Receiving data line 201 Terminal device

Claims (5)

[Claims] When bidirectional communication is performed between a terminal device and a higher-level device that accommodates the terminal device via a transmission line, the terminal device and the higher-level device each include a transmission circuit and a reception circuit for performing transmission and reception, respectively. In a transmission line fault detection system that detects an error based on generated test data and isolates a fault, the terminal device and the higher-level device each notify a partner device of a line fault when detecting an error in communication data in the receiving circuit. A microprocessor for outputting an operation instruction signal for performing the operation, and generating and outputting a control signal for testing the line failure in accordance with the content of the failure in accordance with the operation instruction signal and transmitting the control signal to a partner apparatus via a dedicated control line. A control signal transmission / reception circuit that performs the test data according to the operation instruction signal according to a failure content indicated by the control signal. And a test circuit for generating and outputting a test signal for identifying the content of the line fault. 2. The transmission line fault detection system according to claim 1, wherein the microprocessor stops bidirectional transmission and reception of the communication data in the transmission circuit and the reception circuit after outputting the operation instruction signal. A transmission line fault detection system for operating a test circuit. 3. The transmission line fault detection system according to claim 2, wherein said test circuit regards a line short when the received data at the partner device due to the transmission of said test data is all zero. Transmission line fault detection system. 4. The transmission line fault detection system according to claim 2, wherein the test circuit is configured to control the line if the reception level of the other device by transmitting the test data is equal to or less than a predetermined level range. A transmission line fault detection system characterized as being disconnected. 5. The transmission line fault detection system according to claim 2, wherein the test circuit sets the line of the transmission line to high impedance when transmitting the test data, and sets the line to high impedance. A transmission line fault detection system, comprising separating the test data and amplifying the test data by the receiving circuit in the partner apparatus and detecting a pair break on the transmission line based on the presence or absence of a pulse and the magnitude of crosstalk. .