JPS6243931A - Character synchronizing device for synchronous communication - Google Patents

Abstract

PURPOSE:To attain synchronous communication by providing a frequency division circuit for character synchronization to the transmission side and providing a frequency division circuit for character synchronizing and a reception control section detecting a synchronizing character to the reception size to apply character synchronization at initial transmission only. CONSTITUTION:A synchronous communication equipment consists of a reception buffer means 4 using a synchronizing clock to fetch a serial data and storing it while shifting it sequentially, a synchronizing character detection means 9 detecting a synchronizing character from the serial data stored in the reception buffer means and a frequency division counting sequentially a synchronizing clock for bit number constituting a data and applying frequency division after the synchronizing character detection means is used to detect the synchronizing character. Then the reception buffer means 4 is synchronized one to one with the frequency division output of the frequency division means and the fetched serial data is outputted through an internal data bus in bit parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a communication device that transmits and receives data, and more particularly to a character synchronization device for synchronous communication that transmits and receives data in synchronization with a synchronization clock.

[Conventional technology]

Communication between computers or between a computer and a terminal device is generally divided into synchronous communication methods and asynchronous communication methods. The synchronous communication method is a method in which the data to be sent or received is sent or received as serial data in synchronization with a synchronous clock, whereas the asynchronous communication method is a method in which the data to be sent or received is sent or received as serial data in synchronization with a synchronous clock.The asynchronous communication method is a method in which the data to be sent or received is sent or received as serial data in synchronization with a synchronous clock. This is a method of transmitting or receiving serial data by providing synchronization bits before and after the serial data. The asynchronous communication method has separate clock generation circuits in the transmitting device and the receiving device, and by providing a start bit at the beginning of the serial data and a stop bit after the serial data, the data is synchronized in units of data. This method requires a circuit to insert start bits and stop bits.

Furthermore, since the above-mentioned start bit and stop bit are provided before and after the data, transmission efficiency decreases.

The synchronous communication method does not require a circuit for inserting such start bits and stop bits, and is also characterized by high transmission efficiency because such start bits and stop bits are not inserted. For this reason, the synchronous communication method is generally used in communication of large amounts of data between computers.

On the other hand, in the synchronous communication method, characters must be synchronized for each transmission block or transmission control block in order to clearly demarcate the received data.

For example, in the case of BSC communication, transmission of a synchronization character (SYN) to send control I/roll codes (TCC) such as ENQ and ACK that are sent in synchronization with a synchronization clock shared between the sending and receiving sides, and must transmit a synchronization character (SYN) similar to that described above to send data.

Generally, 5 to 15 such synchronization characters or SYN characters are transmitted immediately before one block. For this reason, a synchronization character is inserted each time a small amount of data is transferred.

There was a problem in that the transmission of these synchronization characters took a lot of time, resulting in a decrease in transmission efficiency.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a character synchronization device for synchronous communication that eliminates the need for TCC and character synchronization characters (SYN) provided for each transmission block and further improves transmission efficiency.

[Key points of the invention]

In order to achieve the above object, the present invention provides a reception control means for sequentially shifting and storing serial data in a synchronous communication device using the same clock.

Synchronization character detection means for detecting a synchronization character code from serial data stored in the reception control means.

After the synchronization character is detected by the synchronization character detection means, the frequency division means sequentially counts and divides the synchronization clock for the number of bits constituting the character, and the reception control means controls the frequency division means. 1 for divided output
It is characterized in that the captured serial data is output as parallel data in one-to-one synchronization.

The effect is that in the synchronous communication device, the frequency dividing means divides the frequency of the synchronous clock by the number of bits constituting the data or character, and on the transmitter side, a synchronous signal is generated for each data or character to be transmitted. On the receiver side, the reception control means converts the serial data into parallel data and generates the data to be received and the timing for taking in each character.

On the receiver side, when the synchronization character detection means detects the synchronization character inserted at the beginning of the block, the frequency division means starts counting and generates a synchronization signal.

〔Example〕

The present invention will be described in detail below using one drawing.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The internal data bus 1 has a data bus buffer 2. Transmission buffer 3. Receive buffer 4. A modem control unit 5 is stored. The data stored in the data bus buffer 22 is output via the internal data bus 1 as transmit data TxD via the transmit buffer, and the receive data RxD added to the receive buffer is input.

First, data transmission will be explained.

The modem control unit 5 is a circuit that sends and receives communication control signals DSR, DTR, CTS, and RTS from modem devices (not shown) to confirm the operating state of the nine devices and whether the modem is capable of communication. Although not shown, a signal notifying that the device is in operation is applied to the modem control unit 5 via a data bus buffer by a microprocessor connected to an external data bus, and the modem device sends DSR and CTS signals to the modem control unit 5.
, the modem control section 5 outputs DTP and RTS to the modem device, and sends a ready signal R to the transmission control section 6.
Output DY.

Note that writing and reading of control data via the internal data bus 1 is performed by control signals applied from the read/write control section 7.

On the other hand, the read/write control section 7 receives the read/write signal and selection signal C/D from the microprocessor mentioned above. The read/write control unit 7 applies a control signal to the data bus buffer 2 to output the stored data from the data bus buffer in which data output from a microprocessor or the like is stored. In response to this signal, data bus buffer 2 outputs data to the internal data bus. The read/write control section 7 applies an acquisition control signal to the transmission control section 6 to acquire data into the transmission buffer 3 .

The transmission control unit 6 transmits the internal data bus 1 using the acquisition control signal.
A start signal is output to the transmission buffer 3, which takes in the data output to the transmission buffer 3, converts it into parallel/serial data, and outputs the transmission data T and D. Note that the start signal consists of a clock for serial data of the transmission clock TxC applied from a modem device (not shown).

The transmission buffer 3 not only takes in data in response to this start signal, but also converts the parallel data into serial data and outputs it.

The aforementioned transmission control section 6 outputs a start signal to the transmission buffer and at the same time further outputs a count start signal to the character synchronization counter 8.

A transmission clock TxC is applied to the character synchronization counter 8, and the character synchronization counter 8 receives the transmission clock TxC at the same time as the count start signal is applied.
It starts counting XC, performs frequency division by the number of bits constituting one data, and outputs the result to the transmission control section 6. Since the character synchronization counter 8 always divides the frequency and outputs a frequency-divided signal by 1 from the time when the above-mentioned load start signal is applied, the data stored in the data bus buffer 2 is sequentially processed under the control of the read/write control section 7. Frequency-divided signal added from character synchronization counter 8, that is, character synchronization signal TX
The transmission control unit 6 controls the transmission buffer 3 to output the signal in synchronization with the CC.

FIG. 2 shows the character synchronization signal TxCC of the embodiment of the present invention.
and a timing chart of transmission data. In the embodiment of the present invention, one data, that is, one character (one character) consists of 8 bits, and one character is transmitted in response to eight transmission clocks. When the first character, for example SYN, is transmitted, a character synchronization signal is output, and then the second character, etc. are transmitted in synchronization with the character synchronization signal. In the second embodiment of the present invention, the transmission data when the character synchronization counter 8 starts a current is a synchronization character.

Through the above-described operation, data, characters, etc., which are continuously added from the external data bus, and transmission data TXD, that is, serial data, are sent to another computer via the modem device.

The embodiment of the present invention shown in FIG. 1 is used oppositely, and the transmission data of the above-described operation is normally received by the receiving function of the embodiment of the present invention, which will be described later.

The transmission data outputted by the above-mentioned transmission function is transmitted via the modem as reception data Rx D as shown in FIG.
When added to the reception buffer 4 of the embodiment of the present invention, the reception buffer 4 stores serial reception data RXD added sequentially in a shift register.

Note that a reception clock is applied to the reception buffer 4 via the reception control section 9, and the aforementioned reception data RxD is shifted in synchronization with this reception clock. The reception buffer 4 has a comparison circuit that determines whether 8 bits of the sequentially shifted data are a specific code (SYN), and when the comparison circuit detects a specific code (SYN), that is, a synchronization character. , outputs a coincidence detection signal to the reception control section 9. The reception control section 9 outputs a count start signal to the character synchronization counter 10 when the coincidence detection signal is added. Character synchronization counter 10
includes a receive clock.

When the count start signal is applied, the character synchronization counter 10 starts counting, divides the frequency by the number of bits constituting the data, that is, divides the frequency by 8, and outputs the frequency to the reception control section 9 as a character synchronization signal.

After a match is detected, the character synchronization counter described above sequentially counts the received clock and outputs the character synchronization signal RxCC whose frequency is divided by eight, so that the reception control unit 9
converts the received data sequentially shifted in the shift register in synchronization with the character synchronization signal Rx CC into parallel data, and stores the contents of the receive buffer 4 in the data bus buffer 2 via the internal data bus 1.

FIG. 3 shows the character synchronization signal RxCC of the embodiment of the present invention.
FIG. 1 is a timing chart of received data. As described above, in the embodiment of the present invention, one data, that is, one character (one character) consists of 8 bits, and one data is received for eight reception clocks. Then, from the time the synchronization establishment character, that is, the synchronization character is detected, the character synchronization clocks R and CC are
is generated, and subsequent data is unconditionally separated in synchronization with this character synchronization clock RxCC.

The received data generally consists of a block of multiple characters, and the subsequent received data is sequentially stored from the receive buffer 4 to the data bus buffer 2 under the control of the above-mentioned reception control unit 9, and is then stored in the data bus buffer 2 by the microprocessor etc. Captured via the connected external data bus.

The aforementioned transmission control unit 6 and reception control unit respectively send transmittable signals T and RDY and reception completion signals R and RDY to the microprocessor connected to the external data bus.
The configuration includes the addition of

The transmission enable signal is a signal indicating that the data stored in the data bus buffer 2 is stored in the transmission buffer and that the primary data can be stored in the data bus buffer. Note that the data stored in the transmission buffer is automatically sent out by a clock applied from the transmission control section 6. Also.

The reception completion signal RXRDY receives the reception data.

This signal indicates that data is stored in the data bus buffer 2.

For example, these signals are used as interrupts to microprocessors.

Transmission control unit 6. The reception control unit 9 includes a read/write control unit 7.
A control signal is added, which controls the transmission control unit 6 to move the transmission data from the data bus buffer 2 to the transmission buffer 3.

and vice versa, a control signal to the reception control section 9 for moving the received data from the reception buffer 4 to the data bus buffer 2.

The operations described above enable character synchronization between the transmitting side device and the receiving side device using one synchronization character. Therefore, there is no need to insert any synchronization character in the following data block or even in the next successive data block, unless synchronization occurs between the transmitting side and the receiving side.

Transmission control unit 6. A character synchronization establishment request signal 5YNDET output from an external microprocessor (not shown) is added to the reception control section 9. This signal causes the transmission control section 6 to operate a character synchronization counter, and the reception control section 9 The received data is compared and when they match, the character synchronization counter is operated.

FIG. 4 is a timing chart showing the procedure of the transmitting side device and the receiving side device in the embodiment of the present invention. When transmitting a data block, the transmitting device first sends out a synchronization character SYN multiple times under some conditions.

These multiple transmissions constitute one data block. By transmitting this synchronization character SYN, a character synchronization signal of the receiving side device is generated from the character synchronization counter described above, and subsequent character synchronization is performed.

Second, a 7-segment signal 8C1-0 indicates that the receiving device has received the first data block, that is, a data block consisting of a plurality of synchronization characters and ENQ.
To send multiple synchronized f3υSYN and Anok signals to AC
The first response data block 11 consisting of KO is sent to the sending device. Since the No. 1 L1 block 17 sent from the receiving device also has a plurality of synchronization characters, the character synchronization counter of the sending device generates a character synchronization signal, which makes it possible to receive ACK O. can. Since the character synchronization counter 10 of each of the above-mentioned transmitting side device and receiving side device generates a character synchronization signal, one data block can be sent out using only STX, data, and ETr3 for subsequent transmission. Also,
As a response from the receiving side device, it is possible to do this simply by sending only the answer signal ACK1 or the like. The above operation is 1, for example BSC
The present invention is applicable not only to data transmission having a single order of procedures, but also to data transmission without any procedure, provided that the communication is synchronous.

〔Effect of the invention〕

As described above, the present invention provides a synchronous communication device in which a frequency dividing circuit for character synchronization is provided on the transmitting side, and a frequency dividing circuit for character synchronization and a reception control unit for detecting a synchronization character are provided on the receiving side. By providing this, it is possible to perform synchronous communication by performing character synchronization only at the time of initial transmission.1 According to the present invention, synchronous communication is possible without constantly transmitting unnecessary synchronization characters SYN and TCC control codes. Therefore, a character synchronization device for synchronous communication with high transmission efficiency can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention. FIG. 2 is a timing chart of transmission data of a character synchronization signal during transmission. FIG. 3 is a timing chart of character synchronization signals and received data during reception. FIG. 4 is a timing chart showing the procedure for transmitting and receiving according to the present invention. 3... Transmission buffer. 4...Reception buffer. 8.10...Character synchronization counter. 6... Transmission control unit. 9...Reception control section.

Claims (2)

[Claims] (1) In a synchronous communication device, receiving buffer means (4) receives serial data using a synchronous clock, sequentially shifts and stores the data, and synchronous character detection detects a synchronous character from the serial data stored in the receiving buffer means. means (9); and frequency dividing means (10) for sequentially counting and frequency-dividing the synchronizing clock for the number of bits constituting data after the synchronizing character is detected by the synchronizing character detecting means, Means (4) is a character synchronization device for synchronous communication, characterized in that the means (4) synchronizes one-to-one with the frequency-divided output of the frequency dividing means and outputs the captured serial data with the internal data bus being bit-parallel. . (2) In a synchronous communication device, a transmission buffer means (3) converts parallel data into serial data in synchronization with a synchronous clock, and a bit that starts counting the synchronous clock when a synchronous character is transmitted and constitutes data. The transmitting buffer means converts the parallel data into serial data in one-to-one synchronization with the divided output of the frequency dividing means. A character synchronization device for synchronous communication characterized by converting and outputting a character.