CN118605692A

CN118605692A - Clock domain conversion circuit, method and related device

Info

Publication number: CN118605692A
Application number: CN202410829895.3A
Authority: CN
Inventors: 王雪
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2024-06-25
Filing date: 2024-06-25
Publication date: 2024-09-06

Abstract

The application discloses a clock domain conversion circuit, a clock domain conversion method and a related device, and belongs to the technical field of data transmission. Wherein the clock domain conversion circuit includes: the input end of the first control unit is connected with the receiving end of the clock domain conversion circuit; the input end of the processing unit is connected with the output end of the first control unit; the input end of the second control unit is connected with the output end of the processing unit, and the output end of the second control unit is connected with the transmitting end of the clock domain conversion circuit; the first control unit is used for sending data to the processing unit under the condition that the data belonging to the first clock domain is acquired from the receiving end; the processing unit is used for storing data and converting a clock domain of the data from a first clock domain to a second clock domain in the case of receiving the data from the first control unit; the second control unit is used for acquiring the converted data from the processing unit and outputting the converted data through the transmitting end.

Description

Clock domain conversion circuit, method and related device

Technical Field

The application belongs to the technical field of data transmission, and particularly relates to a clock domain conversion circuit, a clock domain conversion method and a related device.

Background

In general, when two functional modules belonging to different clock domains in an electronic device perform data transmission, one of the functional modules may first send data to an asynchronous first-in first-out (First Input First Output, FIFO) so that the asynchronous FIFO may convert the clock domain of the data from the clock domain of the one functional module to the clock domain of the other functional module and send the converted data to the other functional module, so that the other functional module may accurately identify and process the converted data to use the processed data.

However, since the situation that the another functional module cannot identify and process the converted data in time may occur, at this time, the one functional module may still send the subsequent data to the asynchronous FIFO, so that the asynchronous FIFO sends the converted subsequent data to the another functional module, and thus, the another functional module may discard the converted subsequent data due to the fact that the another functional module cannot identify and process the converted subsequent data, which may result in incomplete data received by the another functional module, and thus, poor quality of data transmission performed by functional modules belonging to different clock domains in the electronic device may result.

Disclosure of Invention

The embodiment of the application aims to provide a clock domain conversion circuit, a clock domain conversion method and a related device, which can avoid incomplete data received by a functional module in two functional modules belonging to different clock domains, thereby improving the quality of data transmission of the functional modules belonging to different clock domains.

In a first aspect, an embodiment of the present application provides a clock domain switching circuit, including: the input end of the first control unit is connected with the receiving end of the clock domain conversion circuit; the input end of the processing unit is connected with the output end of the first control unit; the input end of the second control unit is connected with the output end of the processing unit, and the output end of the second control unit is connected with the transmitting end of the clock domain conversion circuit; the first control unit is used for sending data to the processing unit under the condition that the data belonging to the first clock domain is acquired from the receiving end; the processing unit is used for storing data and converting a clock domain of the data from a first clock domain to a second clock domain in the case of receiving the data from the first control unit; the second control unit is used for acquiring the converted data from the processing unit and outputting the converted data through the transmitting end.

In a second aspect, an embodiment of the present application provides a clock domain conversion method, which is applied to the clock domain conversion circuit in the first aspect, and the method includes: transmitting data to a processing unit of the clock domain switching circuit through a first control unit of the clock domain switching circuit under the condition that a receiving end of the clock domain switching circuit receives the data belonging to the first clock domain; storing the data and converting the clock domain of the data from the first clock domain to the second clock domain by the processing unit; and acquiring the converted data from the processing unit through a second control unit of the processing unit, and outputting the converted data through a transmitting end of the clock domain conversion circuit.

In a third aspect, an embodiment of the present application provides a clock domain conversion device, including: and the transmitting module is used for transmitting the data to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit under the condition that the receiving end of the clock domain conversion circuit receives the data belonging to the first clock domain. And the processing module is used for storing the data sent by the sending module and converting the clock domain of the data from the first clock domain to the second clock domain through the processing unit. The acquisition module is used for acquiring the data converted by the processing module from the processing unit through the second control unit of the processing unit. And the output module is used for outputting the converted data acquired by the acquisition module through the transmitting end of the clock domain conversion circuit.

In a fourth aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method as described in the second aspect.

In a fifth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor implement the steps of the method according to the second aspect.

In a sixth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and where the processor is configured to execute a program or instructions to implement a method according to the second aspect.

In a seventh aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement the method according to the second aspect.

In the embodiment of the application, the clock domain conversion circuit comprises a first control unit, a processing unit and a second control unit, wherein the input end of the first control unit is connected with the receiving end of the clock domain conversion circuit, the input end of the processing unit is connected with the output end of the first control unit, and the input end of the second control unit is connected with the output end of the processing unit, and the output end of the second control unit is connected with the transmitting end of the clock domain conversion circuit; the first control unit is used for sending data to the processing unit under the condition that the data belonging to the first clock domain is acquired from the receiving end; the processing unit is used for storing data and converting a clock domain of the data from a first clock domain to a second clock domain in the case of receiving the data from the first control unit; the second control unit is used for acquiring the converted data from the processing unit and outputting the converted data through the transmitting end. The processing unit can convert the clock domain of the data from the first clock domain to the second clock domain, and can store the data (namely complete data), so that the second control unit can acquire the converted complete data from the processing unit at proper time (for example, when the function module connected with the transmitting end can timely identify and process the converted data), and output the converted complete data to the function module, so that the function module can accurately identify and process the converted complete data to receive the converted complete data, and therefore the situation that the function module cannot identify and process the converted data and discards the converted data can be avoided, the situation that the converted data received by the function module is incomplete can be avoided, and the quality of data transmission by the function modules belonging to different clock domains in the electronic equipment can be improved.

In the embodiment of the application, the electronic device can send the data to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit under the condition that the receiving end of the clock domain conversion circuit receives the data belonging to the first clock domain, and store the data through the processing unit and convert the clock domain of the data from the first clock domain to the second clock domain, so that the electronic device can acquire the converted data from the processing unit through the second control unit of the processing unit, and output the converted data through the transmitting end of the clock domain conversion circuit. After the first control unit of the clock domain conversion circuit sends the data belonging to the first clock source to the processing unit, the processing unit can convert the clock domain of the data from the first clock domain to the second clock domain, and can store the data (namely complete data), so that the electronic equipment can acquire the converted complete data from the processing unit at a proper time (for example, when the functional module connected with the sending end can timely identify and process the converted data) through the second control unit, and output the converted complete data to the functional module through the output end, so that the functional module can accurately identify and process the converted complete data to receive the converted complete data.

Drawings

Fig. 1 is one of data flow diagrams in which a function module 1 transmits data to a function module 2 in the related art;

FIG. 2 is a second diagram of a data flow of the related art in which the function module 1 sends data to the function module 2;

fig. 3 is one of the data flow diagrams of the processing unit forwarding function module 1 of the clock domain switching circuit according to the embodiment of the present application for transmitting data to the function module 2;

Fig. 4 is a second data flow diagram of the processing unit forwarding function module 1 of the clock domain switching circuit according to the embodiment of the present application for transmitting data to the function module 2;

FIG. 5 is a schematic diagram of a clock domain switching circuit according to an embodiment of the present application;

FIG. 6 is a second schematic diagram of a clock domain switching circuit according to an embodiment of the present application;

FIG. 7 is a third schematic diagram of a clock domain switching circuit according to an embodiment of the present application;

Fig. 8 is a schematic circuit diagram of a first processing channel of a processing unit of a clock domain switching circuit according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a data processing timing sequence of a first processing channel of a processing unit of a clock domain switching circuit according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a clock domain switching circuit according to an embodiment of the present application;

FIG. 11 is a schematic circuit diagram of a second processing channel of a processing unit of the clock domain switching circuit according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a data processing timing sequence of a second processing channel of a processing unit of the clock domain switching circuit according to an embodiment of the present application;

FIG. 13A is a schematic diagram of a clock domain switching circuit according to an embodiment of the present application;

FIG. 13B is a schematic diagram of a clock domain switching circuit according to an embodiment of the present application;

FIG. 13C is a diagram of a clock domain switching circuit according to an embodiment of the present application;

FIG. 14 is a schematic diagram of a clock domain switching circuit according to an embodiment of the present application;

FIG. 15 is a timing diagram illustrating operations performed on data when a verification unit of a clock domain switching circuit according to an embodiment of the present application turns on a verification function;

FIG. 16 is a timing diagram illustrating operations performed on data when a verification unit of a clock domain switching circuit according to an embodiment of the present application turns off a verification function;

FIG. 17 is a diagram illustrating a clock domain switching circuit according to an embodiment of the present application;

FIG. 18 is a schematic diagram of a clock domain switching circuit according to an embodiment of the present application;

FIG. 19 is a flowchart of a clock domain conversion method according to an embodiment of the present application;

Fig. 20 is a schematic structural diagram of a clock domain conversion device according to an embodiment of the present application;

Fig. 21 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application;

fig. 22 is a second schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

The clock domain conversion circuit, the clock domain conversion method and the related devices provided by the embodiment of the application are described in detail below through specific embodiments and application scenes thereof with reference to the accompanying drawings.

The clock domain conversion circuit provided by the embodiment of the application can be applied to a scene of data transmission of two functional modules belonging to different clock domains in electronic equipment.

Currently, a System On Chip (SOC) in an electronic device includes a plurality of functional modules, such as a central processing unit (Central Processing Unit, CPU), a graphics Processor (Graphics Processing Unit, GPU), an image signal Processor (IMAGE SIGNAL Processor, ISP), and the like, some of the functional modules may belong to different clock domains, and interfaces of the functional modules may be connected through a bus and an asynchronous FIFO, so that the functional modules may perform data interaction across the clock domains through the bus and the asynchronous FIFO.

In the related art, assuming that two functional modules, such as a functional module 1 and a functional module 2, are included in the plurality of functional modules, the functional module 1 belonging to the clock domain 1 and the functional module 2 belonging to the clock domain 2, when the functional module 1 is to transmit data (e.g., data d0 to d 3) to the functional module 2, the functional module 1 may transmit the data d0 to d3 to the asynchronous FIFO through the bus first so that the asynchronous FIFO may convert the clock domain of the data d0 to d3 from the clock domain 1 to the clock domain 2 and transmit the converted data d0 to d3 to the functional module 2, so that the functional module 2 can accurately recognize and process the converted data d0 to d3 to use the processed data d0 to d3. However, due to the limited data processing capability of the functional module 2, there may be a situation that the functional module 2 processes too much data, and cannot recognize and process the converted data in time, for example, as shown in fig. 1, the interfaces of the functional module 1 and the functional module 2 do not support the back pressure function (i.e., when the functional module 2 processes too much data, the functional module 1 does not stop sending data), and when the functional module 2 recognizes and processes the converted data d0, the functional module 2 processes too much data, and cannot recognize and process the converted data in time, that is, an output back pressure occurs, at this time, the functional module 1 may still send the subsequent data (i.e., the data d1 to d 3) to the asynchronous FIFO, so that the asynchronous FIFO may send the converted subsequent data d1 to the functional module 2, and thus, the functional module 2 may discard the converted subsequent data (e.g., discard the data d1 and the data d 2) due to the failure to recognize and process the converted subsequent data d1 to d3, and thus may result in that the functional module 2 receives incomplete data, i.e., receives only the data d1 to d3. And, since the situation of waiting to send data may occur in the process that the function module 1 sends the data d0 to d3 to the asynchronous FIFO through the bus, for example, as shown in fig. 2, the situation of waiting to send data may occur after the function module 1 sends the data d0 and the data d1 to the asynchronous FIFO through the bus, that is, after the function module 1 waits for a certain period of time, sends the data d2 to the asynchronous FIFO again through the bus, and the situation of waiting to send the data d2 to the asynchronous FIFO after the function module 1 waits for a certain period of time, that is, the situation of discontinuous output of the converted data d0 to d3 by the asynchronous FIFO may be caused, so that the data received by the function module 2 may be discontinuous, and the quality of data transmission of the function modules belonging to different clock sources is affected.

However, in the embodiment of the present application, a clock domain switching circuit may be provided in the electronic device, and interfaces of the above-described plurality of functional modules may be connected to the clock domain switching circuit through a bus. Thus, when the functional module 1 is to send data (e.g., data d0 to d 3) to the functional module 2, the functional module 1 may send the data d0 to d3 to the clock domain switching circuit through the bus, so that the first control unit of the clock domain switching circuit may receive the data d0 to d3 through the receiving end and send the data d0 to d3 to the processing unit of the clock domain switching circuit, so that the clock domain switching circuit may store the data d0 to d3 and switch the clock domain of the data d0 to d3 from the clock domain 1 to the clock domain 2. Next, the second control unit may obtain the converted data d0 from the processing unit, and output the converted data d0 through the output end of the clock domain conversion circuit, so that the functional module 2 may receive the data d0, for example, as shown in fig. 3, the interface between the functional module 1 and the functional module 2 does not support the back pressure function, when the functional module 2 recognizes and processes the converted data d0, the functional module 2 processes too much data to recognize and process the converted data in time, and at this time, the second control unit may suspend obtaining the converted data d1 to d3 from the processing unit, and continue obtaining the converted data d1 to d3 from the processing unit at a proper time (for example, when the functional module 2 can recognize and process the converted data in time), and output the converted data d1 to d3 through the output end, so that the functional module 2 may accurately recognize and process the converted data d1 to d3 (i.e., the converted data) so that the functional module 2 may receive the converted data d0 to d3 (i.e., the converted data is not completely) and thus the functional module 2 may not receive the converted data completely. And, when the situation of waiting to send data occurs in the process that the functional module 1 sends data d0 to d3 to the clock domain switching circuit through the bus, for example, as shown in fig. 4, the functional module 1 sends the data d0 and the data d1 to the clock domain switching circuit through the bus, that is, the functional module 1 sends the data d2 to the clock domain switching circuit again through the bus after waiting for a certain period of time, and after sending the data d2 to the clock domain switching circuit through the bus, that is, the functional module 1 sends the data d3 to the clock domain switching circuit again through the bus after waiting for a certain period of time, at this time, the processing unit in the clock domain switching circuit can store the data d0 to d3, so that the second control module can acquire the converted data d0 to d3 from the processing unit at a proper timing (for example, when the processing unit switches to finish a certain amount of data), and continuously output the converted data d0 to d3 through the output terminal, thereby avoiding the discontinuous condition of outputting the converted data d0 to d3, and thus, the discontinuous reception of the converted data by the functional module 2 can be avoided. Therefore, the quality of data transmission of the functional modules belonging to different clock sources is improved.

Fig. 5 shows a schematic circuit structure of a clock domain switching circuit according to an embodiment of the present application. As shown in fig. 5, the clock domain conversion circuit provided by the embodiment of the present application may include: a first control unit 10, an input terminal 101 of the first control unit 10 is connected to a receiving terminal 11 of the clock domain switching circuit; a processing unit 12, an input 121 of the processing unit 12 being connected to an output 102 of the first control unit 10; and a second control unit 13, wherein an input end 131 of the second control unit 13 is connected with an output end 122 of the processing unit 12, and an output end 132 of the second control unit 13 is connected with a transmitting end 14 of the clock domain conversion circuit.

In some embodiments of the present application, the receiving end 11 may be connected to at least one functional module in the electronic device, so that the receiving end 11 may receive data belonging to the first clock domain from an interface of the at least one functional module.

In some embodiments of the present application, the first control unit 10 may be any one of the following: a CPU, a programmable logic device (Programmable Logic Device, PLD), a field programmable gate array (FieldProgrammable GATE ARRAY, FPGA), a controller, a microcontroller, and a microprocessor. Of course, the first control unit 10 may also be another control unit, which is not limited herein.

In some embodiments of the present application, the first control unit 10 described above may be referred to as a write control unit. Of course, the first control unit 10 may also be referred to as other units, and embodiments of the present application are not limited herein.

In the embodiment of the present application, the first control unit 10 is configured to send data to the processing unit 12 when the data belonging to the first clock domain is acquired from the receiving end 11.

In some embodiments of the present application, the first control unit 10 belongs to a first clock domain. It will be appreciated that in case of a rising or falling edge of the clock signal of the first clock domain, the first control unit 10 may receive data from the receiving terminal 11 and send the data to the processing unit 12.

In some examples, the first control unit 10 may transmit a write data request signal to the processing unit 12 in the case of receiving data from the receiving end 11, so that the processing unit 12 may determine whether the amount of data received by the processing unit 12 reaches an upper limit, and transmit a full signal to the first control unit 10 in the case of determining that the amount of data received reaches the upper limit, the full signal indicating that the amount of data received by the processing unit 12 reaches the upper limit, or not transmit a full signal to the first control unit 10 in the case of determining that the amount of data received does not reach the upper limit. The first control unit 10 may thereby determine whether a full signal is received within a first preset time period from the time of transmitting the write data request signal, and in the case where the full signal is received, wait for a second preset time period and then transmit the write data request signal to the processing unit 12 again, or may transmit data to the processing unit 12 in the case where the full signal is not received.

It will be appreciated that, since the first control unit 10 may first send the write data request signal to the processing unit 12, so that the processing unit 12 may determine whether the amount of data received by the processing unit 12 reaches the upper limit, and indicate to the first control unit 10 whether the amount of data received by the processing unit 12 reaches the upper limit, the first control unit 10 may send data to the processing unit 12 only when the amount of data received by the processing unit 12 does not reach the upper limit, and thus, a situation that the processing unit 12 cannot receive data due to the amount of data received by the processing unit 12 reaching the upper limit, thereby causing the data to be transmitted to be lost may be avoided.

In the embodiment of the present application, the processing unit 12 is configured to store data and convert a clock domain of the data from a first clock domain to a second clock domain in a case of receiving the data from the first control unit 10.

In the embodiment of the present application, the second clock domain is different from the first clock domain.

It should be noted that, the embodiments of the present application are not limited herein with respect to the sequence of the processing unit 12 storing data and converting the clock domain of the data from the first clock domain to the second clock domain. In one example, processing unit 12 may store data first and then convert the clock domain of the data from a first clock domain to a second clock domain; in another example, processing unit 12 may first convert the clock domain of the data from the first clock domain to the second clock domain and then store the data.

In some embodiments of the present application, the input 121 of the processing unit 12 may belong to a first clock domain, and the output 122 of the processing unit 12 may belong to a second clock domain. It will be appreciated that in the case where the processing unit 12 stores data first and then converts the clock domain of the data from the first clock domain to the second clock domain, the processing unit 12 may store the data in the case where a rising or falling edge occurs in the clock signal of the first clock domain, and the processing unit 12 may convert the clock domain of the data from the first clock domain to the second clock domain in the case where a rising or falling edge occurs in the clock signal of the second clock domain. In the case where the processing unit 12 converts the clock domain of the data from the first clock domain to the second clock domain first and then stores the data, the processing unit 12 may convert the clock domain of the data from the first clock domain to the second clock domain in the case where the clock signal of the first clock domain has a rising edge or a falling edge, and the processing unit 12 may store the data in the case where the clock signal of the second clock domain has a rising edge or a falling edge.

In some embodiments of the present application, the processing unit 12 may include at least one processing channel, which may include at least one memory and at least one asynchronous FIFO. It will be appreciated that the processing unit 12 may store data through the memory and convert the clock domain of the data from the first clock domain to the second clock domain through the asynchronous FIFO.

In some examples, the memory may include at least one of: static Random Access Memory (SRAM), random Access Memory (RAM). Of course, the memory may be other memory devices, and embodiments of the present application are not limited herein.

It should be noted that, for the explanation of the asynchronous FIFO converting the clock domain of the data from the first clock domain to the second clock domain, reference may be made to the specific description in the related art, and the embodiments of the present application are not repeated here.

In some examples, each of the at least one processing channel may store data prior to converting a clock domain of the data from a first clock domain to a second clock domain. Wherein the at least one memory of each processing channel and the input of the at least one asynchronous FIFO belong to a first clock domain and the output of the at least one asynchronous FIFO belong to a second clock domain, such that the at least one memory can fetch data from the first control unit 10 and send the data to the at least one asynchronous FIFO in case of a rising or falling edge of a clock signal of the first clock domain and the at least one asynchronous FIFO can convert the clock domain of the data from the first clock domain to the second clock domain in case of a rising or falling edge of a clock signal of the second clock domain.

In other examples, each of the at least one processing channel may first convert a clock domain of data from a first clock domain to a second clock domain and then store the data. Wherein the input of the at least one asynchronous FIFO belongs to the first clock domain, the output of the at least one asynchronous FIFO and the at least one memory belong to the second clock domain, such that the at least one asynchronous FIFO may obtain data from the first control unit 10 in case of a rising or falling edge of the clock signal of the first clock domain, and the at least one asynchronous FIFO may convert the clock domain of the data from the first clock domain to the second clock domain in case of a rising or falling edge of the clock signal of the second clock domain, and send the converted data to the at least one memory, such that the at least one memory may store the converted data.

In still other examples, a portion of the at least one processing channel may first store data and then convert a clock domain of the data from a first clock domain to a second clock domain, and another portion of the at least one processing channel may first convert the clock domain of the data from the first clock domain to the second clock domain and then store the data. Wherein at least one memory of the portion of the processing channels and an input of at least one asynchronous FIFO belong to a first clock domain and an output of at least one asynchronous FIFO belongs to a second clock domain; the input of at least one asynchronous FIFO of the further part of the processing channels belongs to a first clock domain, the output of at least one asynchronous FIFO and at least one memory belongs to a second clock domain.

The following will exemplify that at least one of the processing channels comprises two processing channels.

In some embodiments of the present application, in conjunction with fig. 5, as shown in fig. 6, the processing unit 12 includes: a first processing channel 123, an input 1231 of the first processing channel 123 being connected to the output 102 of the first control unit 10, an output 1232 of the first processing channel 123 being connected to the input 131 of the second control unit 13; a second processing channel 124, an input 1241 of the second processing channel 124 being connected to the output 102 of the first control unit 10, and an output 1242 of the second processing channel 124 being connected to the input 131 of the second control unit 13.

In the embodiment of the present application, the first processing channel 123 is configured to store data first and then convert the clock domain of the data from the first clock domain to the second clock domain when receiving the data from the first control unit 10.

In some embodiments of the present application, the input terminal 1231 of the first processing channel 123 belongs to a first clock domain, and the output terminal 1232 of the first processing channel 123 belongs to a second clock domain.

In some embodiments of the present application, the first processing channel 123 may include at least one memory and at least one asynchronous FIFO, where an input of the at least one memory may be connected to the output 102 of the first control unit 10, and an output of the at least one asynchronous FIFO may be connected to the input 131 of the second control unit 13, and the at least one memory and the at least one asynchronous FIFO may be connected in series and/or in parallel. Thus, the first processing channel 123 may store data first and then convert the clock domain of the data from the first clock domain to the second clock domain in the case of receiving the data from the first control unit 10. Wherein at least one memory of the first processing channel 123 and at least one input of the asynchronous FIFO belong to a first clock domain and at least one output of the asynchronous FIFO belong to a second clock domain.

In the embodiment of the present application, since the first clock domain and the second clock domain are different, the frequency of the clock signal in the first clock domain and the frequency of the clock signal in the second clock domain are also different, so that the situation that the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain may occur, at this time, if the first processing channel 123 converts the clock domain of data from the first clock domain to the second clock domain, and then stores the data, that is, the rate of the input data of the asynchronous FIFO is greater than the rate of the output data of the asynchronous FIFO (and the rate of the storage storing the converted data), the situation may occur that the asynchronous FIFO cannot receive the data due to the fact that the storage space of the asynchronous FIFO is less, so that the data is lost, and the situation may occur that the storage can only store less data due to the fact that the rate of the output converted data of the asynchronous FIFO is slower, so that the utilization rate of the storage is lower. Thus, the first processing channel 123 may store data first and then convert the clock domain of the data from the first clock domain to the second clock domain.

The first processing channel 123 will be exemplified below as comprising a memory and an asynchronous FIFO.

In some embodiments of the present application, referring to fig. 5 and 6, as shown in fig. 7, the first processing channel 123 includes: a first memory 1233, the input 12331 of the first memory 1233 being connected to the output 102 of the first control unit 10; a first asynchronous FIFO1234, the input 12341 of the first asynchronous FIFO1234 being connected to the output 12332 of the first memory 1233, the output 12342 of the first asynchronous FIFO1234 being connected to the input 131 of the second control unit 13.

In some embodiments of the present application, the first memory 1233 may include at least one of: static Random Access Memory (SRAM), random Access Memory (RAM). Of course, the first memory 1233 may be other memory devices, which are not limited herein.

In the embodiment of the present application, the first memory 1233 is used to store data.

In some embodiments of the present application, the first control unit 10 may transmit the write data request signal to the first memory 1233 when a rising edge or a falling edge occurs in the clock signal of the first clock domain in the case of receiving data from the receiving terminal 11, so that the first memory 1233 may determine whether the amount of data received by the first memory 1233 reaches an upper limit when a rising edge or a falling edge occurs in the clock signal of the first clock domain, as shown in connection with fig. 7, and transmit the full signal buf_full to the first control unit 10 when a rising edge or a falling edge occurs in the clock signal of the first clock domain in the case of determining that the amount of data received reaches the upper limit, the full signal buf_full indicating that the amount of data received by the first memory 1233 reaches the upper limit, or not transmit the full signal buf_full to the first control unit 10 in the case of determining that the amount of data received does not reach the upper limit. The first control unit 10 may thus determine whether the full signal buf_full is received within a first preset time period from the time when the write data request signal is transmitted when the rising edge or the falling edge of the clock signal of the first clock domain occurs, and, after waiting for a second preset time period when the full signal buf_full is received, may transmit the write data request signal to the first memory 1233 again when the rising edge or the falling edge of the clock signal of the first clock domain occurs, or may transmit the buf_wr signal to the first memory 1233 when the rising edge or the falling edge of the clock signal of the first clock domain occurs when the full signal buf_full is not received, the buf_wr signal being used to carry the data. Next, the first memory 1233 may send a afifo _wr signal to the first asynchronous FIFO1234 at a rising or falling edge of the clock signal of the first clock domain, the afifo _wr signal being used to carry the data so that the first asynchronous FIFO1234 may receive the data.

In an embodiment of the present application, the first asynchronous FIFO1234 is used to convert the clock domain of data from the first clock domain to the second clock domain.

It should be noted that, for the explanation of the conversion of the clock domain of the data from the first clock domain to the second clock domain of the first asynchronous FIFO1234, reference may be made to the detailed description in the related art, and the embodiments of the present application are not repeated here.

In some embodiments of the present application, in conjunction with fig. 8, in the case where the first asynchronous FIFO1234 does not receive data, the first asynchronous FIFO1234 may send a null signal afifo _empty to the second control unit 13 when a rising or falling edge occurs in the clock signal of the second clock domain, where the null signal afifo _empty is used to indicate that no data is stored in the first asynchronous FIFO1234, so as to avoid that the second control unit 13 obtains data from the first asynchronous FIFO1234 when a rising or falling edge occurs in the clock signal of the second clock domain. The first asynchronous FIFO1234 may obtain the data from the first memory 1233 when the clock signal of the first clock domain has a rising edge or a falling edge, and convert the clock domain of the data from the first clock domain to the second clock domain when the clock signal of the second clock domain has a rising edge or a falling edge, and stop sending the null signal afifo _empty to the second control unit 13, so that the second control unit 13 may obtain the converted data from the first asynchronous FIFO1234, for example, at an adaptation timing (for example, when the functional module connected to the transmitting end 14 is capable of timely identifying and processing the converted data) and when the clock signal of the second clock domain has a rising edge or a falling edge.

In the embodiment of the present application, the first processing channel 123 may store data through the first memory 1233, and then convert the clock domain of the data from the first clock domain to the second clock domain through the first asynchronous FIFO1234, so as to avoid the situation that the utilization rate of the first memory 1233 is lower and the data is lost when the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain.

Illustratively, fig. 9 shows a timing diagram of the data processing of the first processing channel 123. assuming that the input 12341 of the first asynchronous FIFO1234 of the first processing channel 123 is connected to the output 102 of the first control unit 10, the output 12342 of the first asynchronous FIFO1234 is connected to the input 12331 of the first memory 1233, the output 12332 of the first memory 1233 is connected to the input 131 of the second control unit 13, i.e. assuming that the first processing channel 123 first converts the clock domain of data from the first clock domain to the second clock domain and then stores the data, the clock signal rx_clk of the first clock domain has a frequency twice the frequency of the clock signal co_clk of the second clock domain, the depth of the first asynchronous FIFO1234 is 4 and the memory space of the first memory 1233 is larger than the memory space of the first asynchronous FIFO 1234. As shown in fig. 9, at time T0, the first asynchronous FIFO1234 may receive data (e.g., data d 0-d 5) from the first control unit 10, at which time the first control unit 10 sends a afifo _ wr signal to the first asynchronous FIFO1234, which afifo _ wr signal is used to carry the data d 0-d 5, i.e., the afifo _ wr signal goes high at time T0, so that the first asynchronous FIFO1234 may be clocked out of the first control unit 10 after one clock cycle of the clock signal co _ clk after the time at which the data was received, at the time at which the rising edge of the clock signal co _ clk occurred, The clock domain of the received data is converted from the first clock domain to the second clock domain, however, since the depth of the first asynchronous FIFO1234 is 4, in case the first asynchronous FIFO1234 receives four data (i.e., data d0 to d 3), the storage space of the first asynchronous FIFO1234 is full, at which time the first asynchronous FIFO1234 may send a full signal afifo full to the first control unit 10 when a falling edge (i.e., time T1) occurs in the clock signal co_clk, i.e., when the afifo _wr signal goes high at time T1, and when a falling edge occurs in the clock signal co_clk after the first asynchronous FIFO1234 receives the data d1, the transmission of the null signal afifo _empty to the first memory 1233 is stopped. In this way, the first control unit 10 may stop sending the afifo _wr signal to the first asynchronous FIFO1234 after receiving the full signal afifo _full and one clock period of the clock signal rx_clk, when the rising edge of the clock signal rx_clk occurs, but at this time, the first control unit 10 may have sent the data D4 and the data D5, so the first asynchronous FIFO1234 cannot receive the data D4 and the data D5, and the data D4 and the data D5 may be lost; Also, the first memory 1233 may transmit the afifo _rd signal to the first memory 1233 after a clock cycle of the clock signal co_clk after a moment when the empty signal afifo _empty is not received, when the rising edge of the clock signal co_clk occurs, since the first asynchronous FIFO1234 may convert only the clock domain of the data d0 from the first clock domain to the second clock domain at this time, the afifo _rd signal may carry only the data d0, that is, the first memory 1233 may store only one data (i.e., the data d 0), Resulting in lower utilization of the first memory 1233. As can be seen from the above, in the case that the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain, if the data is stored and converted from the first clock domain to the second clock domain through the first processing channel 123, the data should be stored first and then converted from the first clock domain to the second clock domain.

Therefore, the output end of the first control unit can be sequentially connected with the first memory and the first asynchronous FIFO, so that when the data is stored through the first processing channel and the clock domain of the data is converted from the first clock domain to the second clock domain, the data is stored first, and then the clock domain of the data is converted from the first clock domain to the second clock domain, and the situation that the utilization rate of the first memory is lower and the data is lost due to the fact that the storage space of the first asynchronous FIFO is full can be avoided under the condition that the frequency of the clock signal of the first clock domain is larger than that of the clock signal of the second clock domain.

In the embodiment of the present application, the second processing channel 124 is configured to convert the clock domain of the data from the first clock domain to the second clock domain and then store the data when receiving the data from the first control unit 10.

In some embodiments of the present application, the input 1241 of the second processing channel 124 belongs to the first clock domain, and the output of the second processing channel 124 belongs to the second clock domain.

In some embodiments of the present application, the second processing channel 124 may include at least one memory and at least one asynchronous FIFO, where an input of the at least one asynchronous FIFO may be connected to the output 102 of the first control unit 10, an output of the at least one memory may be connected to the input 131 of the second control unit 13, and the at least one memory and the at least one asynchronous FIFO may be connected in series and/or in parallel. Thus, the second processing channel 124 may first convert the clock domain of the data from the first clock domain to the second clock domain and then store the data in case of receiving the data from the first control unit 10. Wherein at least one asynchronous FIFO input of the second processing channel 124 belongs to a first clock domain and at least one memory and an output of the at least one asynchronous FIFO belongs to a second clock domain.

In the embodiment of the present application, since the first clock domain and the second clock domain are different, the frequency of the clock signal in the first clock domain and the frequency of the clock signal in the second clock domain are also different, so that the situation that the frequency of the clock signal in the first clock domain is smaller than the frequency of the clock signal in the second clock domain may occur, and the rate of the asynchronous FIFO output data (and the rate of the memory storing the converted data) is greater than the rate of the asynchronous FIFO input data, the second processing channel 124 may convert the clock domain of the data from the first clock domain to the second clock domain and store the data, so as to reduce the time for storing the converted data into the memory.

The second processing channel 124 will be exemplified below as comprising a memory and an asynchronous FIFO.

In some embodiments of the present application, referring to fig. 5 and 6, as shown in fig. 10, the second processing channel 124 includes: a second asynchronous FIFO1243, the input 12431 of the second asynchronous FIFO1243 being connected to the output 102 of the first control unit 10; a second memory 1244, the input 12441 of the second memory 1244 being connected to the output 12432 of the second asynchronous FIFO1243, the output 12442 of the second memory 1244 being connected to the input 131 of the second control unit 13.

In the embodiment of the present application, the second asynchronous FIFO1243 is used to convert the clock domain of data from the first clock domain to the second clock domain.

It should be noted that, for the explanation of the second asynchronous FIFO1243 converting the clock domain of the data from the first clock domain to the second clock domain, reference may be made to the specific description in the related art, and the embodiments of the present application will not be repeated here.

In some embodiments of the present application, the first control unit 10 may transmit the write data request signal to the second asynchronous FIFO1243 upon occurrence of a rising edge or a falling edge of the clock signal of the first clock domain in case of receiving data from the receiving end 11, so that the second asynchronous FIFO1243 may determine whether the amount of data received by the second asynchronous FIFO1243 reaches an upper limit upon occurrence of a rising edge or a falling edge of the clock signal of the first clock domain, in combination with fig. 11, and transmit the full signal afifo _full to the first control unit 10 upon occurrence of a rising edge or a falling edge of the clock signal of the first clock domain, the full signal afifo _full being used to indicate that the amount of data received by the second asynchronous FIFO1243 reaches an upper limit, or not transmit the full signal afifo _full to the first control unit 10 in case of determining that the amount of data received does not reach the upper limit. The first control unit 10 may thus determine whether the full signal afifo _full is received within a first preset time period from the moment of sending the write data request signal when a rising or falling edge occurs in the clock signal of the first clock domain, and, after waiting for a second preset time period in the case of receiving the full signal afifo _full, send the write data request signal to the second asynchronous FIFO1243 again when a rising or falling edge occurs in the clock signal of the first clock domain, or may send the afifo _wr signal to the second asynchronous FIFO1243 when a rising or falling edge occurs in the clock signal of the first clock domain in the case of not receiving the full signal afifo _full, the afifo _wr signal being for carrying the data. Next, the second asynchronous FIFO1243 may convert the clock domain of the data from the first clock domain to the second clock domain when a rising or falling edge occurs in the clock signal of the second clock domain, and send a buf_wr signal to the second memory 1244, the buf_wr signal being used to carry the converted data.

In some embodiments of the present application, the second memory 1244 may include at least one of: static Random Access Memory (SRAM), random Access Memory (RAM). Of course, the second memory 1244 may be other memory devices, which are not limited herein.

In the embodiment of the present application, the second memory 1244 is used for storing data.

In some embodiments of the present application, in connection with fig. 11, in a case where the second memory 1244 does not receive data, the second memory 1244 may send a null signal buf_empty to the second control unit 13 when a rising edge or a falling edge occurs in the clock signal of the second clock domain, where the null signal buf_empty is used to indicate that no data is stored in the second memory 1244, so as to avoid the second control unit 13 from retrieving data from the second memory 1244 when the rising edge or the falling edge occurs in the clock signal of the second clock domain. And, when a rising edge or a falling edge occurs in the clock signal of the second clock domain, the second memory 1244 may obtain the converted data from the second asynchronous FIFO1243, and stop sending the null signal buf_empty to the second control unit 13, so that the second control unit 13 may obtain the buf_rd signal from the second memory 1244 when an adaptation timing (for example, when the function module connected to the transmitting end 14 is capable of timely identifying and processing the converted data) occurs, and when a rising edge or a falling edge occurs in the clock signal of the second clock domain, the buf_rd signal is used to carry the converted data.

In the embodiment of the present application, the second processing channel 124 may convert the clock domain of the data from the first clock domain to the second clock domain through the second asynchronous FIFO1243, and then store the converted data through the second memory 1244, so as to reduce the time for storing the converted data into the second memory 1244.

Illustratively, FIG. 12 shows a timing diagram of the data processing of the second processing channel 124. Assuming that the frequency of the clock signal co_clk of the second clock domain is twice the frequency of the clock signal rx_clk of the first clock domain, the depth of the second asynchronous FIFO1243 is 4, and the memory space of the second memory 1244 is larger than the memory space of the second asynchronous FIFO 1243. As shown in fig. 12, at time T0, the rising edge of the clock signal rx_clk occurs, and the second asynchronous FIFO1243 may receive data (e.g., data d 0-d 4) from the first control unit 10, at which time the first control unit 10 sends a afifo _wr signal to the second asynchronous FIFO1243, which afifo _wr signal is used to carry the data d 0-d 4, i.e., the afifo _wr signal goes high at time T0, so that the second asynchronous FIFO1243 may be clocked one clock cycle after the time of receipt of the data (i.e., data d 0), Upon rising edges of the clock signal co_clk, the clock domain of the received data d0 is converted from the first clock domain to the second clock domain, and upon rising edges of the clock signal co_clk (i.e., time T1) after one clock cycle of the clock signal co_clk is spaced, a afifo _rd signal is sent to the second memory 1244, the afifo signal being used to carry the converted data, i.e., the afifo _rd signal goes high at time T1, so that the second memory 1244 can store the converted data d0, and the second asynchronous FIFO1243 can send afifo _empty signals to the second memory 1244, The afifo _empty signal is used to indicate that no data is stored in the second asynchronous FIFO1243, i.e., the afifo _rd signal goes low at time T1 to avoid the second memory 1244 reading data from the second asynchronous FIFO1243 when the rising edge of the clock signal co_clk occurs, and so on until the converted data d 1-d 4 are sent to the second memory 1244. Also, after the second memory 1244 stores the converted data d0, after one clock period (for example, at time T2) of the interval clock signal co_clk, the second memory 1244 may stop sending the buf_empty signal for indicating that no data is stored in the second memory 1244, i.e., the buf_empty signal becomes low level at time T2, to the second control unit 13. The second control unit 13 may thus read the converted data from the second memory 1244 at an adaptation time (e.g. when the converted data d0 to d4 are stored in the second memory 1244), e.g. at time T3, i.e. the second memory 1244 sends a buf_rd signal to the second control unit 13, which buf_rd signal is used to carry the converted data, i.e. the buf_rd signal goes high at time T3, and the second control unit 13 may receive the converted data d0 to d4. it will be appreciated that since the second control unit 13 reads the converted data from the second memory 1244 at the adaptation timing, the second control unit 13 can continuously acquire the converted data d0 to d4. It will be appreciated that, since the converted data of the second asynchronous FIFO1243 may be stored in the second memory 1244 in time, the memory space of the second asynchronous FIFO1243 will not be full of data during the process of transmitting the data d0 to d4, i.e. the afifo _full signal is always low.

Therefore, the output end of the first control unit can be sequentially connected with the second asynchronous FIFO and the second memory, so that when the data is stored through the second processing channel and the clock domain of the data is converted from the first clock domain to the second clock domain, the clock domain of the data is firstly converted from the first clock domain to the second clock domain, and then the data is stored, the time for storing the converted data into the second memory is shortened, and the time for processing the data through the second processing channel can be shortened.

In the embodiment of the present application, the first control unit 10 is specifically configured to send data to the first processing channel 123 when the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain; or to the second processing channel 124 in case the frequency of the clock signal of the first clock domain is smaller than the frequency of the clock signal of the second clock domain.

It will be appreciated that in the case where the frequency of the clock signal of the first clock domain is greater than the frequency of the clock signal of the second clock domain, the first control unit 10 may send data to the first processing channel 123 to process the data through the first processing channel 123; or in case the frequency of the clock signal of the first clock domain is smaller than the frequency of the clock signal of the second clock domain, the first control unit 10 may send data to the second processing channel 124 to process the data through the second processing channel 124.

In summary, since the first control unit may select to process data through the first processing channel or the second processing channel according to the magnitude relation between the frequency of the clock signal in the first clock domain and the frequency of the clock signal in the second clock domain, when the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain, the situation that the utilization rate of the first memory is low and the data is lost due to the full storage space of the first asynchronous FIFO can be avoided; or in case the frequency of the clock signal of the first clock domain is smaller than the frequency of the clock signal of the second clock domain, the time consumption for processing data through the second processing channel may be reduced.

In some embodiments of the present application, the second control unit 13 may be any one of the following: CPU, PLD, FPGA, a controller, a microcontroller and a microprocessor. Of course, the second control unit 13 may also be another control unit, which is not limited herein.

In some embodiments of the present application, the second control unit 13 may be referred to as a read control unit. Of course, the second control unit 13 may also be referred to as other units, and embodiments of the present application are not limited herein.

In the embodiment of the present application, the second control unit 13 is configured to obtain the converted data from the processing unit 12, and output the converted data through the transmitting end 14.

In some embodiments of the present application, the second control unit 13 may acquire the converted data from the processing unit 12 at an appropriate timing and output the converted data through the transmitting end 14.

The appropriate time may include when the functional module connected to the transmitting end 14 can timely identify and process the converted data. The appropriate timing may also include the processing unit 12 converting to complete a certain amount of data, which may be preset. Of course, the foregoing suitable timing may also include other timing, and those skilled in the art may set the timing according to requirements, and embodiments of the present application are not limited herein.

The embodiment of the application provides a clock domain conversion circuit, which comprises a first control unit, a processing unit and a second control unit, wherein the input end of the first control unit is connected with the receiving end of the clock domain conversion circuit, the input end of the processing unit is connected with the output end of the first control unit, and the input end of the second control unit is connected with the output end of the processing unit, and the output end of the second control unit is connected with the transmitting end of the clock domain conversion circuit; the first control unit is used for sending data to the processing unit under the condition that the data belonging to the first clock domain is acquired from the receiving end; the processing unit is used for storing data and converting a clock domain of the data from a first clock domain to a second clock domain in the case of receiving the data from the first control unit; the second control unit is used for acquiring the converted data from the processing unit and outputting the converted data through the transmitting end. The processing unit can convert the clock domain of the data from the first clock domain to the second clock domain, and can store the data (namely complete data), so that the second control unit can acquire the converted complete data from the processing unit at proper time (for example, when the function module connected with the transmitting end can timely identify and process the converted data), and output the converted complete data to the function module, so that the function module can accurately identify and process the converted complete data to receive the converted complete data, and therefore the situation that the function module cannot identify and process the converted data and discards the converted data can be avoided, the situation that the converted data received by the function module is incomplete can be avoided, and the quality of data transmission by the function modules belonging to different clock domains in the electronic equipment can be improved.

In addition, the processing unit can convert the clock domain of the data from the first clock domain to the second clock domain, and can store the data (namely the complete data), so that the second control unit can acquire the converted data from the processing unit at proper time (for example, when the processing unit converts a certain amount of data), and continuously output the converted data through the output end, thereby avoiding the situation of discontinuous output of the converted data, avoiding discontinuous data received by the function module connected with the transmitting end, and improving the quality of data transmission by the function module belonging to different clock domains in the electronic equipment.

Of course, in order to ensure the accuracy of data transmitted by functional modules belonging to different clock domains in an electronic device, a check unit may also be provided in the clock domain conversion circuit to determine whether the data is erroneous by the check unit, as will be illustrated below.

In some embodiments of the present application, the clock domain conversion circuit further includes: a check unit connected to at least one of the first control unit 10 and the second control unit 13.

It should be noted that, for the description of the structure of the verification unit, reference may be made to the specific description in the related art, and the embodiments of the present application are not repeated herein.

In some embodiments of the present application, the number of the verification units may be at least one.

In some examples, in case the number of check units is one, the check unit may be connected with the first control unit 10 and/or the check unit may be connected with the second control unit 13.

For example, assuming that the number of the above-mentioned verification units is one, as shown in fig. 13A in conjunction with fig. 5, the verification unit 15 may be connected to the first control unit 10. Or in connection with fig. 5, the verification unit 15 may be connected to the second control unit 13 as shown in fig. 13B. Or in connection with fig. 5, the verification unit 15 may be connected to the first control unit 10 and the second control unit 13 as shown in fig. 13C.

In other examples, in case the number of check units is at least two, at least one of them may be connected with the first control unit 10 and the other at least one check unit may be connected with the second control unit 13. It can be understood that the data with packet loss and the data without packet loss can be accurately determined by setting a plurality of verification units to verify the data for a plurality of times, so that the data with packet loss and the data without packet loss can be discarded and the data without packet loss can be sent, and the accuracy of the sent data can be further ensured.

For example, assuming that the number of the above-mentioned check units is at least two, as shown in fig. 14 in conjunction with fig. 5, the check units may include a check unit 16 and a check unit 17, the check unit 16 may be connected with the first control unit 10, and the check unit 17 may be connected with the second control unit 13.

In the embodiment of the application, the verification unit is used for controlling the connected control unit to send the acquired data under the condition that the data acquired by the connected control unit is determined to have no packet loss; or under the condition that the packet loss exists in the data acquired by the connected control unit, the control unit controlling the connection discards the acquired data.

It should be noted that, for the description of the flow of determining whether the packet loss exists in the data acquired by the control unit, which is determined by the verification unit, reference may be made to the specific description in the related art, and the embodiments of the present application are not repeated herein.

It may be understood that, in the case where the verification unit is connected to the first control unit 10, the verification unit is configured to control the first control unit 10 to send the acquired data to the processing unit 12 in the case where there is no packet loss in the data acquired by the first control unit 10; or in the case where it is determined that there is a packet loss in the data acquired by the first control unit 10, the first control unit 10 is controlled to discard the acquired data. And/or, in the case that the verification unit is connected to the second control unit 13, the verification unit is configured to control the second control unit 13 to send the acquired data to the processing unit 12 when there is no packet loss in the data acquired by the second control unit 13; or in the case where it is determined that there is a packet loss in the data acquired by the second control unit 13, the second control unit 13 is controlled to discard the acquired data.

In some embodiments of the present application, when the verification function of the verification unit is turned on, the verification unit is configured to control the connected control unit to send the acquired data when it is determined that there is no packet loss in the data acquired by the connected control unit; or under the condition that the packet loss exists in the data acquired by the connected control unit, the control unit controlling the connection discards the acquired data.

For example, fig. 15 shows a timing diagram of the operation of the data when the verification unit turns on the verification function. Assuming that the verification unit is connected to the first control unit 10, as shown in fig. 15, the first control unit 10 may receive data (e.g., data d0 to d 5) from the transmitting terminal 14 of the clock domain switching circuit when a rising edge or a falling edge occurs in the clock signal of the first clock domain, and the verification unit may verify the data d0 to d 5. If the check unit determines that there is a packet loss in the data d0 to d5, the check unit may send a check_error signal to the first control unit 10, where the check_error signal is used to indicate that there is a packet loss in the data d0 to d5, i.e. the check_error signal may change to a high level, so that the first control unit 10 does not send the afifo _wr signal to the processing unit 12, where the afifo _wr signal is used to carry the data d0 to d5, i.e. the afifo _wr signal is maintained at a low level, i.e. the processing unit 12 does not store the data d0 to d5 and switch the clock domain of the data d0 to d5 from the first clock domain to the second clock domain.

For example, fig. 16 shows a timing diagram of the operation of the data when the verification unit turns off the verification function. Assuming that the verification unit is connected to the first control unit 10, as shown in fig. 16, the first control unit 10 may receive data (e.g. data d0 to d 5) from the transmitting end 14 of the clock domain switching circuit when a rising edge or a falling edge occurs in the clock signal of the first clock domain, at this time, since the verification unit turns off the verification function, the verification unit does not verify the data d0 to d5, i.e. the check_error signal is maintained at a low level, so that the first control unit 10 may send a afifo _wr signal to the processing unit 12, where the afifo _wr signal is used to carry the data d0 to d5, i.e. the afifo _wr signal may be changed to a high level, i.e. the processing unit 12 may store the data d0 to d5 and switch the clock domain of the data d0 to d5 from the first clock domain to the second clock domain, regardless of whether there is a packet loss in the data d0 to d 5.

Therefore, the check unit can be arranged in the clock domain conversion circuit to determine whether the data acquired by the connected control unit has packet loss or not, so that the check unit can control the connected control unit to discard the data with packet loss or control the connected control unit to send the data without packet loss, namely the check unit can control the connected control unit to discard the wrong data or control the connected control unit to send the accurate data, and the accuracy of the sent data can be ensured.

Of course, in order to ensure that the converted data output from the transmitting end of the clock domain conversion circuit is continuous data, a counting unit may be provided in the clock domain conversion circuit to determine whether the converted data stored in the processing unit 12 is sufficient by the counting unit, as will be exemplified below.

In some embodiments of the present application, in conjunction with fig. 5, as shown in fig. 17, the clock domain conversion circuit further includes: a counting unit 18, the counting unit 18 being connected to the processing unit 12 and the second control unit 13.

In the embodiment of the present application, the counting unit 18 is configured to record the number value of the converted data stored in the processing unit 12. The second control unit 13 is specifically configured to acquire the converted data from the processing unit (12) when the number value of the converted data recorded by the counting unit (18) is greater than or equal to a predetermined number value.

In some embodiments of the present application, the counting unit 18 may first acquire the data output position required for outputting the data each time, determine the predetermined number value according to the data-related information and the data output position, and then determine whether the number value of the data stored in the processing unit 12 is greater than or equal to the predetermined number value.

In some examples, assuming that the above-mentioned data is data of an image, the above-mentioned data output position is a line end of each line of pixels of the image, the counting unit 18 may first acquire the data output position required for outputting the data each time (for example, the line end of each line of pixels), and determine the above-mentioned predetermined number value, which is equal to the number of each line of pixels of the image, based on the number of each line of pixels of the data of the image and the line end of each line of pixels, so that in the case where the number value of the data of the input image in the processing unit 12 is greater than or equal to the above-mentioned predetermined number value, the counting unit 18 may increase by 1 in the count value indicating the number corresponding to the line of pixels stored in the processing unit 12, so that the second control unit 13 may acquire the converted data from the processing unit 12 in the case where the count value of the counting unit 18 is determined to be greater than 0, that in the case where the number value of the data of the image stored in the processing unit 12 is greater than or equal to the above-mentioned predetermined number value.

It should be noted that, in the above example, the data output position is shown as the end of each row of pixels of the image, and in practical application, those skilled in the art may set the data output position according to the needs, which is not limited by the embodiment of the present application.

As can be seen from this, since the counting unit may be provided in the clock domain converting circuit, the electronic device may determine, by means of the counting unit, whether the number value of the converted data stored in the processing unit is greater than or equal to the predetermined number value, and control the second control unit to acquire the converted data from the processing unit in the case where the number value of the converted data stored in the processing unit is greater than or equal to the predetermined number value, that is, in the case where a sufficient number of the converted data is stored in the processing unit, it may be ensured that the second control unit outputs continuous converted data through the transmitting terminal, so that the function module connected to the transmitting terminal may receive continuous converted data.

Of course, due to the diversity of application scenarios, even with the same interface type, the allocated clock resources may not be uniform, and thus, the synchronous bridge unit 19 may be provided in the clock domain switching circuit to synchronize the timing relationship between the transmitting end and the connected functional modules through the synchronous bridge unit 19, which will be illustrated below.

In some embodiments of the present application, in conjunction with fig. 5, as shown in fig. 18, the clock domain conversion circuit further includes: an asynchronous bridge unit 19, the input 191 of the asynchronous bridge unit 19 being connected to the output of the transmitting terminal 14.

It should be noted that, for the description of the structure of the synchronous bridge unit 19, reference may be made to the specific description in the related art, and the embodiments of the present application are not described herein.

In some embodiments of the application, the above-mentioned asynchronous bridge unit 19 may be connected to a functional module. The functional module is a functional module connected to the transmitting end 14 in the above embodiment.

In the embodiment of the present application, the asynchronous bridge unit 19 is configured to convert the clock domain of the converted data from the second clock domain to the third clock domain when the converted data is obtained from the transmitting end 14.

In some embodiments of the present application, the electronic device may first obtain the third clock domain from the functional module connected to the transmitting end 14, and then convert the clock domain of the converted data from the second clock domain to the third clock domain through the asynchronous bridge unit 19.

It should be noted that, for the explanation of the conversion of the clock domain of the converted data from the second clock domain to the third clock domain by the synchronous bridge unit 19, reference may be made to the specific description in the related art, and the embodiments of the present application are not repeated here.

Therefore, the asynchronous bridge unit is further arranged in the clock domain conversion circuit, so that the clock domain of the converted data can be converted from the second clock domain to the required clock domain through the asynchronous bridge unit, and the functional module connected with the transmitting end can accurately identify and use the reconverted data, and can be ensured to receive the data.

Fig. 19 is a schematic flow chart of a clock domain conversion method according to an embodiment of the present application, which is applied to an electronic device including the clock domain conversion circuit as in fig. 5 to 18. As shown in fig. 19, the clock domain conversion method provided by the embodiment of the present application may include the following steps 101 to 103.

In step 101, when the receiving end of the clock domain conversion circuit receives data belonging to the first clock domain, the electronic device sends the data to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit.

In some embodiments of the present application, in a case where a functional module of an electronic device connected to a receiving end is to transmit data to a functional module connected to a transmitting end, in a case where a rising edge or a falling edge occurs in a clock signal of a first clock domain, the functional module connected to the receiving end may transmit data belonging to the first clock domain to the receiving end, so that the receiving end may receive the data.

It should be noted that, for the explanation that the electronic device sends the data to the processing unit of the clock domain switching circuit through the first control unit of the clock domain switching circuit, reference may be made to the specific description in the foregoing embodiment, and the embodiments of the present application are not repeated herein.

Step 102, the electronic device stores data and converts a clock domain of the data from a first clock domain to a second clock domain by the processing unit.

It should be noted that, for the description of the electronic device storing data and converting the clock domain of the data from the first clock domain to the second clock domain through the processing unit, reference may be made to the specific description in the foregoing embodiments, and the embodiments of the present application are not repeated herein.

In some embodiments of the present application, before the step 102, the clock domain conversion method provided in the embodiment of the present application may further include the following step 201, and the step 102 may be specifically implemented by the following step 102a or step 102 b.

Step 201, the electronic device determines, by the first control unit, a magnitude relation between a frequency of a clock signal of the first clock domain and a frequency of a clock signal of the second clock domain.

In step 102a, when the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain, the electronic device controls the first control unit to send data to the first processing channel of the processing unit, so as to store the data through the first processing channel first, and then convert the clock domain of the data from the first clock domain to the second clock domain.

In step 102b, when the frequency of the clock signal in the first clock domain is smaller than the frequency of the clock signal in the second clock domain, the electronic device controls the first control unit to send data to the second processing channel of the processing unit, so as to convert the clock domain of the data from the first clock domain to the second clock domain through the second processing channel, and then store the data.

As can be seen from this, the electronic device can select to process data through the first processing channel or the second processing channel according to the magnitude relation between the frequency of the clock signal in the first clock domain and the frequency of the clock signal in the second clock domain by the first control unit, so that in the case that the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain, the situation that the utilization rate of the first memory is low and the data is lost due to the full storage space of the first asynchronous FIFO can be avoided; or in case the frequency of the clock signal of the first clock domain is smaller than the frequency of the clock signal of the second clock domain, the time consumption for processing data through the second processing channel may be reduced.

Step 103, the electronic device obtains the converted data from the processing unit through the second control unit of the processing unit, and outputs the converted data through the transmitting end of the clock domain conversion circuit.

In some embodiments of the present application, before the step 103, the clock domain conversion method provided in the embodiment of the present application may further include the following step 202, and the step 103 may be specifically implemented by the following step 103 a.

Step 202, the electronic device obtains the number value of the data stored in the processing unit through the counting unit of the clock domain conversion circuit.

It should be noted that, the above description of the execution sequence of step 201 and step 202 is not limited to the embodiment of the present application. In some examples, the electronic device may perform step 201 first and then step 202; in other examples, the electronic device may perform step 202 first and then step 201; in still other examples, the electronic device may perform step 202 at the same time as performing step 201.

Step 103a, in the case that the number value is greater than or equal to the predetermined number value, the electronic device acquires the converted data from the processing unit through the second control unit.

As can be seen from this, since the electronic device can determine, through the counting unit, whether the number value of the converted data stored in the processing unit is greater than or equal to the predetermined number value, and in the case where the number value of the converted data stored in the processing unit is greater than or equal to the predetermined number value, that is, in the case where a sufficient number of the converted data is stored in the processing unit, the converted data is acquired from the processing unit through the second control unit, it can be ensured that the second control unit outputs continuous converted data through the transmitting end, so that the functional module connected to the transmitting end can receive continuous converted data.

The embodiment of the application provides a clock domain conversion method, wherein an electronic device can send data to a processing unit of a clock domain conversion circuit through a first control unit of the clock domain conversion circuit under the condition that a receiving end of the clock domain conversion circuit receives the data belonging to a first clock domain, and store the data through the processing unit and convert the clock domain of the data from the first clock domain to a second clock domain, so that the electronic device can acquire the converted data from the processing unit through the second control unit of the processing unit, and output the converted data through a transmitting end of the clock domain conversion circuit. After the first control unit of the clock domain conversion circuit sends the data belonging to the first clock source to the processing unit, the processing unit can convert the clock domain of the data from the first clock domain to the second clock domain, and can store the data (namely complete data), so that the electronic equipment can acquire the converted complete data from the processing unit at a proper time (for example, when the functional module connected with the sending end can timely identify and process the converted data) through the second control unit, and output the converted complete data to the functional module through the output end, so that the functional module can accurately identify and process the converted complete data to receive the converted complete data.

In some embodiments of the present application, before "sending data to the processing unit of the clock domain conversion circuit through the first control unit of the clock domain conversion circuit" in the above step 101, the clock domain conversion method provided in the embodiment of the present application may further include the following step 203, and the above step 101 may be specifically implemented by the following step 101 a.

In step 203, when the receiving end of the clock domain conversion circuit receives the data belonging to the first clock domain, the electronic device determines, through the checking unit of the clock domain conversion circuit, whether the data acquired by the first control unit has packet loss.

In step 101a, under the condition that it is determined that the packet loss does not exist in the data acquired by the first control unit, the electronic device controls the first control unit to send the data to the processing unit through the checking unit.

In some embodiments of the present application, the above step 101a may be replaced by the following step 101b.

Step 101b, under the condition that the packet loss exists in the data acquired by the first control unit, the electronic equipment controls the first control unit to discard the acquired data through the checking unit.

Therefore, the electronic device can determine whether the data acquired by the first control unit has packet loss through the check unit, so that the electronic device can control the first control unit to discard the data with the packet loss through the check unit, or control the first control unit to send the data without the packet loss, namely, the electronic device can control the first control unit to discard the wrong data through the check unit, or the first control unit sends the accurate data, and therefore the accuracy of the data sent by the first control unit can be ensured.

In some embodiments of the present application, before the step 103 of outputting the converted data through the transmitting end of the clock domain conversion circuit, the clock domain conversion method provided in the embodiment of the present application may further include the following step 204, and the step 103 may be specifically implemented by the following step 103 b.

Step 204, the electronic device obtains the converted data from the processing unit through the second control unit of the processing unit, and determines whether the data obtained by the second control unit has packet loss or not through the checking unit of the clock domain conversion circuit.

Step 103b, under the condition that the data acquired by the second control unit is determined to have no packet loss, the electronic device controls the second control unit to output the converted data through the transmitting end through the checking unit.

In some embodiments of the present application, the above step 103b may be replaced by the following step 103c.

Step 103c, the electronic device controls the second control unit to discard the acquired data through the checking unit under the condition that the packet loss exists in the data acquired by the second control unit.

Therefore, the electronic device can determine whether the data acquired by the second control unit has packet loss through the check unit, so that the electronic device can control the second control unit to discard the data with packet loss through the check unit, or control the second control unit to send the data without packet loss, namely, the electronic device can control the second control unit to discard wrong data through the check unit, or the second control unit to send accurate data, and therefore the accuracy of the data sent by the second control unit can be ensured.

In some embodiments of the present application, after the step 103, the clock domain conversion method provided in the embodiment of the present application may further include the following steps 301 and 302.

Step 301, the electronic device obtains a third clock domain to which a receiving interface corresponding to the data belongs through an asynchronous bridge unit of the clock domain conversion circuit.

In the embodiment of the present application, the receiving interface corresponding to the data may be understood as: and the interface of the functional module is connected with the transmitting end.

Step 302, the electronic device converts the clock domain of the converted data from the second clock domain to the third clock domain through the synchronous bridge unit.

Therefore, the electronic device can convert the clock domain of the converted data from the second clock domain to the required clock domain through the asynchronous bridge unit, so that the functional module connected with the sending end can accurately identify and use the converted data, and the functional module can be ensured to receive the data.

According to the clock domain conversion method provided by the embodiment of the application, the execution main body can be a clock domain conversion device. In the embodiment of the application, the clock domain conversion device is taken as an example to execute the clock domain conversion method.

Fig. 20 shows a schematic structural diagram of a clock domain conversion device according to an embodiment of the present application. As shown in fig. 20, the clock domain conversion device 40 provided in the embodiment of the present application may include: the transmitting module 41 is configured to transmit data to the processing unit of the clock domain switching circuit through the first control unit of the clock domain switching circuit when the receiving end of the clock domain switching circuit receives data belonging to the first clock domain. The processing module 42 is configured to store the data transmitted by the transmitting module 41 and convert the clock domain of the data from the first clock domain to the second clock domain by the processing unit. The obtaining module 43 is configured to obtain, from the processing unit, the data converted by the processing module 42 through the second control unit of the processing unit. An output module 44, configured to output the converted data obtained by the obtaining module 43 through a transmitting end of the clock domain conversion circuit.

The embodiment of the application provides a clock domain conversion device, because after a first control unit of a clock domain conversion circuit sends data belonging to a first clock source to a processing unit, the processing unit can not only convert a clock domain of the data from the first clock domain to a second clock domain, but also store the data (namely complete data), so that the clock domain conversion device can acquire the converted complete data from the processing unit at proper time (for example, when a functional module connected with a sending end can timely identify and process the converted data) through a second control unit, and output the converted complete data to the functional module through an output end, so that the functional module can accurately identify and process the converted complete data to receive the converted complete data.

In a possible implementation manner, the processing module 42 is further configured to determine, by the first control unit, a magnitude relation between a frequency of a clock signal of the first clock domain and a frequency of a clock signal of the second clock domain, before storing, by the processing unit, the data and converting, by the processing unit, the clock domain of the data from the first clock domain to the second clock domain; under the condition that the frequency of the clock signal of the first clock domain is larger than that of the clock signal of the second clock domain, the first control unit is controlled to send data to the first processing channel of the processing unit, so that the data is stored firstly through the first processing channel, and then the clock domain of the data is converted from the first clock domain to the second clock domain; or under the condition that the frequency of the clock signal of the first clock domain is smaller than that of the clock signal of the second clock domain, the first control unit is controlled to send data to the second processing channel of the processing unit, so that the clock domain of the data is firstly converted from the first clock domain to the second clock domain through the second processing channel, and then the data is stored.

In a possible implementation manner, the processing module 42 is further configured to determine, by using a verification unit of the clock domain switching circuit, whether the data acquired by the first control unit has packet loss before the sending module 41 sends the data to the processing unit through the first control unit. The sending module 41 is specifically configured to control, by using the verification unit, the first control unit to send data to the processing unit when the processing module 42 determines that there is no packet loss in the data acquired by the first control unit. The above-mentioned sending module 41 is further configured to, when the processing module 42 determines that there is a packet loss in the data acquired by the first control unit, control the first control unit to discard the acquired data through the checking unit.

In a possible implementation manner, the processing module 42 is further configured to determine, by using a verification unit of the clock domain conversion circuit, whether the packet loss exists in the data acquired by the second control unit before the output module 44 outputs the converted data through the transmitting end. The output module 44 is specifically configured to control, by using the verification unit, the second control unit to output the converted data through the transmitting end when the processing module 42 determines that the packet loss does not exist in the data acquired by the second control unit. The output module 44 is further configured to control, by using the verification unit, the second control unit to discard the acquired data when the processing module 42 determines that there is a packet loss in the data acquired by the second control unit.

In a possible implementation manner, the obtaining module 43 is further configured to obtain, by using the counting unit of the clock domain converting circuit, the number value of the data stored in the processing unit before obtaining, by using the second control unit, the converted data from the processing unit. The above-mentioned obtaining module 43 is specifically configured to obtain, from the processing unit, the converted data through the second control unit when the number value is greater than or equal to the predetermined number value.

In a possible implementation manner, the obtaining module 43 is further configured to obtain, through an asynchronous bridge unit of the clock domain conversion circuit, a third clock domain to which the receiving interface corresponding to the data belongs after the output module 44 outputs the converted data through the transmitting end. The processing module 42 is further configured to convert, by the asynchronous bridge unit, the clock domain of the converted data from the second clock domain to the third clock domain acquired by the acquiring module 43.

The clock domain conversion device in the embodiment of the application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices than a terminal. The electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a Mobile Internet Device (MID), an augmented reality (augmentedreality, AR)/Virtual Reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer, a UMPC, a netbook, a Personal Digital Assistant (PDA), or the like, and may be a server, a network attached storage (network attached storage, NAS), a personal computer (personal computer, PC), a Television (TV), an teller machine, a self-service machine, or the like, which is not particularly limited.

The clock domain conversion device in the embodiment of the application can be a device with an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, and the embodiment of the present application is not limited specifically.

The clock domain conversion device provided by the embodiment of the present application can implement each process implemented by the method embodiment of fig. 19, and in order to avoid repetition, a detailed description is omitted here.

Optionally, as shown in fig. 21, the embodiment of the present application further provides an electronic device 50, including a processor 51 and a memory 52, where the memory 52 stores a program or an instruction that can be executed on the processor 51, and the program or the instruction implements each process step of the above clock domain conversion method embodiment when executed by the processor 51, and the process steps can achieve the same technical effects, so that repetition is avoided, and no further description is given here.

The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.

Fig. 22 is a schematic hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 100 includes, but is not limited to: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, and processor 110.

Those skilled in the art will appreciate that the electronic device 100 may further include a power source (e.g., a battery) for powering the various components, and that the power source may be logically coupled to the processor 110 via a power management system to perform functions such as managing charging, discharging, and power consumption via the power management system. The electronic device structure shown in fig. 22 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than those shown in the drawings, or may combine some components, or may be arranged in different components, which will not be described in detail herein.

Wherein, the processor 110 is configured to send data to the processing unit of the clock domain switching circuit through the first control unit of the clock domain switching circuit when the receiving end of the clock domain switching circuit receives the data belonging to the first clock domain; and storing the data and converting the clock domain of the data from the first clock domain to the second clock domain by the processing unit; and acquiring the converted data from the processing unit through a second control unit of the processing unit, and outputting the converted data through a transmitting end of the clock domain conversion circuit.

The embodiment of the application provides an electronic device, wherein after a first control unit of a clock domain conversion circuit sends data belonging to a first clock source to a processing unit, the processing unit can convert a clock domain of the data from the first clock domain to a second clock domain and can store the data (namely complete data), so that the electronic device can acquire the converted complete data from the processing unit at proper time (for example, when a functional module connected with a sending end can timely identify and process the converted data) through a second control unit, and output the converted complete data to the functional module through an output end, so that the functional module can accurately identify and process the converted complete data to receive the converted complete data.

In a possible implementation, the processor 110 is further configured to determine, by the first control unit, a magnitude relation between a frequency of the clock signal of the first clock domain and a frequency of the clock signal of the second clock domain before storing the data and converting the clock domain of the data from the first clock domain to the second clock domain by the processing unit.

The processor 110 is specifically configured to any one of the following: under the condition that the frequency of the clock signal of the first clock domain is larger than that of the clock signal of the second clock domain, the first control unit is controlled to send data to a first processing channel of the processing unit so as to store the data firstly through the first processing channel and then convert the clock domain of the data from the first clock domain to the second clock domain; and under the condition that the frequency of the clock signal of the first clock domain is smaller than that of the clock signal of the second clock domain, controlling the first control unit to send data to the second processing channel of the processing unit so as to firstly convert the clock domain of the data from the first clock domain to the second clock domain through the second processing channel and then store the data.

In a possible implementation manner, the processor 110 is further configured to determine, by using a verification unit of the clock domain switching circuit, whether the data acquired by the first control unit has packet loss before the data is sent to the processing unit of the clock domain switching circuit by using the first control unit of the clock domain switching circuit.

The processor 110 is specifically configured to control, by using the verification unit, the first control unit to send data to the processing unit when it is determined that there is no packet loss in the data acquired by the first control unit.

The above processor 110 is further configured to control, by using the verification unit, the first control unit to discard the acquired data if it is determined that the packet loss exists in the data acquired by the first control unit.

In a possible implementation manner, the processor 110 is further configured to determine, by using a verification unit of the clock domain conversion circuit, whether the packet loss exists in the data acquired by the second control unit before the converted data is output by the transmitting end of the clock domain conversion circuit.

The processor 110 is specifically configured to control, by using the verification unit, the second control unit to output the converted data through the transmitting end when it is determined that the packet loss does not exist in the data acquired by the second control unit.

The processor 110 is further configured to control, by using the verification unit, the second control unit to discard the acquired data if it is determined that the packet loss exists in the data acquired by the second control unit.

In a possible implementation manner, the processor 110 is further configured to obtain, by using the counting unit of the clock domain conversion circuit, the number value of the data stored in the processing unit before the converted data is obtained from the processing unit by using the second control unit of the processing unit.

The processor 110 is specifically configured to obtain, when the number value is greater than or equal to a predetermined number value, the converted data from the processing unit through the second control unit.

In a possible implementation manner, the processor 110 is further configured to obtain, through an asynchronous bridge unit of the clock domain conversion circuit, a third clock domain to which a receiving interface corresponding to the data belongs after the converted data is output through a transmitting end of the clock domain conversion circuit; and converting the clock domain of the converted data from the second clock domain to the third clock domain through the asynchronous bridge unit.

It should be appreciated that in embodiments of the present application, the input unit 104 may include a graphics processor (graphics processing unit, GPU) 1041 and a microphone 1042, the graphics processor 1041 processing image data of still pictures or video obtained by an image capturing device (e.g. a camera) in a video capturing mode or an image capturing mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also referred to as a touch screen. The touch panel 1071 may include two parts of a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.

Memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a first memory area storing programs or instructions and a second memory area storing data, wherein the first memory area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 109 may include volatile memory or nonvolatile memory, or the memory 109 may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM), static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (doubledata RATE SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCH LINKDRAM, SLDRAM), and direct memory bus random access memory (direct rambus RAM, DRRAM). Memory 109 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.

Processor 110 may include one or more processing units; optionally, the processor 110 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, etc., and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 110.

The embodiment of the application also provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the above clock domain conversion method embodiment, and can achieve the same technical effects, so that repetition is avoided, and no further description is given here.

Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes computer readable storage medium such as computer readable memory ROM, random access memory RAM, magnetic or optical disk, etc.

The embodiment of the application further provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the clock domain conversion method embodiment, and the same technical effects can be achieved, so that repetition is avoided, and the description is omitted here.

It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.

Embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the above-described clock domain conversion method embodiment, and achieve the same technical effects, and for avoiding repetition, a detailed description is omitted herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. A clock domain switching circuit, comprising:

the input end of the first control unit is connected with the receiving end of the clock domain conversion circuit;

the input end of the processing unit is connected with the output end of the first control unit;

the input end of the second control unit is connected with the output end of the processing unit, and the output end of the second control unit is connected with the transmitting end of the clock domain conversion circuit;

The first control unit is used for sending the data to the processing unit under the condition that the data belonging to the first clock domain is acquired from the receiving end;

the processing unit is used for storing the data and converting the clock domain of the data from the first clock domain to the second clock domain in the case of receiving the data from the first control unit;

the second control unit is used for acquiring the converted data from the processing unit and outputting the converted data through the sending end.

2. The clock domain switching circuit of claim 1, wherein the processing unit comprises:

The input end of the first processing channel is connected with the output end of the first control unit, and the output end of the first processing channel is connected with the input end of the second control unit;

The input end of the second processing channel is connected with the output end of the first control unit, and the output end of the second processing channel is connected with the input end of the second control unit;

The first processing channel is used for storing the data firstly and then converting the clock domain of the data from the first clock domain to the second clock domain under the condition that the data is received from the first control unit;

The second processing channel is used for converting the clock domain of the data from the first clock domain to the second clock domain and then storing the data under the condition that the data is received from the first control unit;

The first control unit is specifically configured to send the data to the first processing channel when the frequency of the clock signal in the first clock domain is greater than the frequency of the clock signal in the second clock domain; or sending the data to the second processing channel in case the frequency of the clock signal of the first clock domain is smaller than the frequency of the clock signal of the second clock domain.

3. The clock domain switching circuit of claim 2, wherein the first processing channel comprises:

The input end of the first memory is connected with the output end of the first control unit;

the input end of the first asynchronous first-in first-out FIFO is connected with the output end of the first memory, and the output end of the first asynchronous first-out FIFO is connected with the input end of the second control unit;

The first memory is used for storing the data, and the first asynchronous FIFO is used for converting the clock domain of the data from the first clock domain to the second clock domain.

4. A clock domain switching circuit according to claim 2 or 3, wherein the second processing channel comprises:

The input end of the second asynchronous FIFO is connected with the output end of the first control unit;

the input end of the second memory is connected with the output end of the second asynchronous FIFO, and the output end of the second memory is connected with the input end of the second control unit;

wherein the second asynchronous FIFO is configured to convert a clock domain of the data from the first clock domain to the second clock domain, and the second memory is configured to store the data.

5. The clock domain switching circuit of claim 1, wherein the clock domain switching circuit further comprises:

The verification unit is connected with at least one of the first control unit and the second control unit;

the verification unit is used for controlling the connected control unit to send the acquired data under the condition that the data acquired by the connected control unit is determined to have no packet loss; or under the condition that the packet loss exists in the data acquired by the connected control unit, the control unit controlling the connection discards the acquired data.

6. The clock domain switching circuit of claim 1, wherein the clock domain switching circuit further comprises:

The counting unit is connected with the processing unit and the second control unit;

Wherein the counting unit is used for recording the quantity value of the converted data stored in the processing unit;

The second control unit is specifically configured to acquire the converted data from the processing unit when the number value of the converted data recorded by the counting unit is greater than or equal to a predetermined number value.

7. The clock domain switching circuit of claim 1, wherein the clock domain switching circuit further comprises:

The input end of the asynchronous bridge unit is connected with the output end of the sending end;

The asynchronous bridge unit is used for converting the clock domain of the converted data from the second clock domain to the third clock domain under the condition that the converted data are acquired from the transmitting end.

8. A clock domain conversion method applied to an electronic device, the electronic device comprising the clock domain conversion circuit according to any one of claims 1 to 7, the method comprising:

transmitting the data to a processing unit of the clock domain switching circuit through a first control unit of the clock domain switching circuit under the condition that a receiving end of the clock domain switching circuit receives the data belonging to a first clock domain;

Storing the data and converting a clock domain of the data from the first clock domain to a second clock domain by the processing unit;

And acquiring converted data from the processing unit through a second control unit of the processing unit, and outputting the converted data through a transmitting end of the clock domain conversion circuit.

9. The clock domain conversion method according to claim 8, wherein before the storing of the data by the processing unit and the conversion of the clock domain of the data from the first clock domain to the second clock domain, the method further comprises:

determining, by the first control unit, a magnitude relationship between a frequency of a clock signal of the first clock domain and a frequency of a clock signal of the second clock domain;

the storing of the data and the conversion of the clock domain of the data from the first clock domain to a second clock domain by the processing unit comprises any one of the following:

Controlling the first control unit to send the data to a first processing channel of the processing unit under the condition that the frequency of a clock signal of the first clock domain is larger than that of a clock signal of the second clock domain, so as to store the data through the first processing channel first and then convert the clock domain of the data from the first clock domain to the second clock domain;

and under the condition that the frequency of the clock signal of the first clock domain is smaller than that of the clock signal of the second clock domain, controlling the first control unit to send the data to the second processing channel of the processing unit so as to firstly convert the clock domain of the data from the first clock domain to the second clock domain through the second processing channel and then store the data.

10. The clock domain conversion method according to claim 8, wherein before the data is transmitted to the processing unit of the clock domain conversion circuit by the first control unit of the clock domain conversion circuit, the method further comprises:

Determining whether the data acquired by the first control unit has packet loss or not through a checking unit of the clock domain conversion circuit;

The sending, by the first control unit of the clock domain switching circuit, the data to the processing unit of the clock domain switching circuit includes:

controlling the first control unit to send the data to the processing unit through the checking unit under the condition that the data acquired by the first control unit is determined to have no packet loss;

the method further comprises the steps of:

And under the condition that the packet loss exists in the data acquired by the first control unit, controlling the first control unit to discard the acquired data through the checking unit.

11. The clock domain conversion method according to claim 8, wherein before the converted data is output by the transmitting end of the clock domain conversion circuit, the method further comprises:

determining whether the data acquired by the second control unit has packet loss or not through a checking unit of the clock domain conversion circuit;

The outputting, by the transmitting end of the clock domain conversion circuit, the converted data includes:

under the condition that the data acquired by the second control unit is determined to have no packet loss, the second control unit is controlled by the verification unit to output the converted data through the transmitting end;

the method further comprises the steps of:

and under the condition that the packet loss exists in the data acquired by the second control unit, controlling the second control unit to discard the acquired data through the checking unit.

12. The clock domain conversion method according to claim 8, wherein before the converted data is acquired from the processing unit by the second control unit of the processing unit, the method further comprises:

acquiring the number value of the data stored in the processing unit through a counting unit of the clock domain conversion circuit;

the obtaining, by the second control unit of the processing unit, the converted data from the processing unit includes:

and acquiring the converted data from the processing unit through the second control unit when the number value is greater than or equal to a preset number value.

13. The clock domain conversion method according to claim 8, wherein after the converted data is output by the transmitting end of the clock domain conversion circuit, the method further comprises:

Acquiring a third clock domain to which a receiving interface corresponding to the data belongs through an asynchronous bridge unit of the clock domain conversion circuit;

And converting the clock domain of the converted data from the second clock domain to the third clock domain through the asynchronous bridge unit.

14. A clock domain switching apparatus, comprising:

A transmitting module, configured to transmit, when a receiving end of the clock domain conversion circuit receives data belonging to a first clock domain, the data to a processing unit of the clock domain conversion circuit through a first control unit of the clock domain conversion circuit;

A processing module, configured to store, by the processing unit, the data sent by the sending module and convert a clock domain of the data from the first clock domain to a second clock domain;

The acquisition module is used for acquiring the data converted by the processing module from the processing unit through a second control unit of the processing unit;

And the output module is used for outputting the converted data acquired by the acquisition module through the transmitting end of the clock domain conversion circuit.

15. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the clock domain conversion method of any one of claims 8 to 13.

16. A readable storage medium, characterized in that the readable storage medium has stored thereon a program or instructions which, when executed by a processor, implement the steps of the clock domain conversion method according to any of claims 8 to 13.

17. A chip comprising a processor and a communication interface, the communication interface being coupled to the processor, the processor being configured to execute programs or instructions to implement the steps of the clock domain conversion method of any one of claims 8 to 13.