JP2932851B2 - Asynchronous serial data transceiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transmitting / receiving apparatus, and more particularly to an apparatus for transmitting / receiving asynchronous serial data of a plurality of channels.

[0002]

2. Description of the Related Art Conventionally, when transmitting and receiving two channels of asynchronous serial data, two channels of asynchronous serial data transmitting and receiving devices which can operate independently are used. Alternatively, as shown in FIG. 4, the asynchronous serial data transmission / reception device 400 as hardware for transmitting and receiving serial data has only one channel, and only has two channels of asynchronous serial data input / output terminals, and switching is performed at terminal portions. A method of using it while performing was considered.

[0003]

When two channels of the conventional asynchronous serial data transmitting / receiving apparatus are used, the amount of hardware is large and the cost is high, and the price of an application system using the asynchronous serial data transmitting / receiving apparatus is increased. I was invited. Further, in reality, the microcomputer that controls the asynchronous serial data transmission / reception device has two
Since it is difficult to manage two asynchronous serial data transmission / reception devices, the period during which serial data transmission / reception is actually performed is generally short, and the use efficiency of hardware is extremely low.

Further, in the conventional asynchronous serial data transmitting / receiving apparatus of the terminal switching type, switching timing and the like must be managed by a microcomputer or the like.
Asynchronous operation, which is the main advantage of asynchronous serial data transmission / reception (operation in which devices that transmit / receive serial data transmit / receive in synchronization with the start bit even if the microcomputer does not control the timing of the transmission / reception operation) However, there is a problem that the effect of using the asynchronous serial data transmission / reception method is completely lost.

An object of the present invention is to provide an inexpensive asynchronous serial data transmission / reception device that utilizes the advantages of the asynchronous system.

[0006]

To achieve the above object, an asynchronous serial data transmitting / receiving apparatus according to the present invention comprises a receiving register, a transmitting register, a start bit detecting means, a notifying means, and an output means. An asynchronous serial data transmitting and receiving device that synchronizes by detecting a start bit, wherein the receiving register is connected to a two-channel serial data receiving terminal and stores received serial data; The transmission register is connected to two channels of serial data transmission terminals,
The serial data to be transmitted is stored. The start bit detecting means is connected to the serial data receiving terminals of two channels to detect the start bit. The notifying means is connected to the serial data receiving terminal. When the start bit detection means detects the start bit, the reception bit is notified to the other party, and the storage means selectively stores data from the serial data reception terminal where the start bit is detected. The output means selectively outputs the transmission data from the transmission register to the serial data transmission terminals of two channels.

In addition, a function is provided in which priority is set to the start bit detecting means of the two channels, and when the start bits are detected simultaneously, the output of the start bit detecting means having priority is given priority.

[0008]

Since the asynchronous serial transmission / reception circuit has two built-in start bit detection circuits, it can be used as a 2-channel serial transmission / reception device at low cost while taking advantage of the asynchronous system.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing an asynchronous serial data transmitting / receiving apparatus according to a first embodiment of the present invention.

Referring to FIG. 1, an asynchronous serial data transmitting / receiving apparatus 150 according to the present invention includes a reception register 100, a transmission register 101, a baud rate generator 102 for controlling a clock frequency for transmission and reception, and a start for detecting a start bit of serial data. Bit detector 10
4, 108, a shift clock control circuit 105, switching circuits 106 and 110, a reception control unit 107, a transmission control unit 109, and a register 111.

Two sets of terminals for transmission and reception are provided for channel 0 and channel 1. The RXD0 / RXD1 terminal is used for receiving serial data, and the TXD0 / TXD1 terminal is used for transmitting serial data.

The CTS0 (inverted) / CTS1 (inverted) terminal is an input terminal, which is a signal for externally controlling the transmission operation, and can be transferred only when the logical value is "0".

The RTS0 / RTS1 terminal outputs a logical value "0" when reception is possible at the output terminal, and outputs "1" when reception is not possible, and is connected to a CTS (inverting) terminal of a device for transmitting serial data. .

Next, the operation will be described. Here, as shown in FIG. 1, a serial data transmission / reception device 160 having the same function as the serial data transmission / reception device 150 is connected, and the level of the RTS0 / RTS1 terminal is set to a logical value “0” in advance. . Start bit detector 1
The baud rate generator 102 indicates that the level on the RXD0 terminal has changed from the logical value “1” to “0”.
And detects the first bit of the serial data.

Further, a shift clock for shifting the reception register 100 is supplied to the shift clock control unit 105. Here, when the start bit is detected, the detection output is transmitted by the reception control unit 107, and the reception control unit 107
Since the S1 terminal has the logical value “1”, the CTS11 (inverted) terminal has the logical value “1”, and the transfer of serial data from the TXD11 terminal of the serial data transmitting / receiving device 160 is prohibited.

The reception control unit 107 is provided with the switching circuit 1
06, and RXD0
Transmits signals on terminals. In addition, the shift clock control unit 105 is controlled to supply the clock from the start bit detection unit 104 to the reception register 100.

On the other hand, the start bit detector 108
When the start bit on the XD1 terminal is detected, a detection output is transmitted to the reception control unit 107, and the reception control unit 107
Since the TS0 terminal has the logical value “1”, the CTS10 (inverted) terminal has the logical value “1”, and the transfer of serial data from the TXD10 terminal of the serial data transmitting / receiving device 160 is prohibited.

The reception control unit 107 is provided with the switching circuit 1
06 to RXD1
Transmits signals on terminals. Further, the shift clock control unit 105 is controlled to supply the clock from the start bit detection unit 108 to the reception register 100. The start bit is simultaneously detected by the start bit detector 10
In the case of detection at 4, 108, the output of the start bit detection unit 104 is prioritized to prevent malfunction.

The transmitting operation is performed as follows.
When data to be transmitted is written into the transmission register 101 by a microcomputer (not shown), the switching circuit 11
T specified by register 111 by the action of 0
Transmission data is output to the XD0 or TXD1 terminal.
At this time, if the logical value of the corresponding CTS (inverted) terminal is “1”, this is detected by the reception control unit 109, and the transfer operation is suspended.

Next, the operation will be described with reference to the timing chart of FIG. In the figure, at T1 timing, RXD
The start bit from the TXD10 terminal is supplied to the 0 terminal, and this is detected by the start bit detection unit 104. Therefore, the RTS1 terminal becomes a logical value “1” by the operation of the reception control unit 107. Therefore, transfer of serial data from the TXD11 terminal is not performed. Serial data (7
At the T2 timing when the data transfer of (bit) ends,
The reception control unit 107 detects this, and sets the RTS1 terminal to a logical value “0”, whereby the TXD10 terminal, TXD11
Transfer from the terminal is enabled. At the timing T3, the start bit detection unit 108 detects the start bit, so that the RTS0 terminal has a logical value “1”, and
The transfer from the XD10 terminal is suspended. At the timing T4, the data transfer ends, and the RTS0 terminal returns to the logical value “0” again.

(Embodiment 2) FIG. 3 is a block diagram showing Embodiment 2 of the present invention. In the first embodiment, since only one baud rate generator is built in, only one baud rate can be handled.

In this embodiment, a baud rate generator 200 is newly added. The reception baud rate of the RXD0 terminal and the reception baud rate of the RXD1 terminal can be controlled independently. For transmission, the transmission control unit 109 selects a baud rate generator specified by the register 111 and supplies the selected baud rate generator to the transmission register 101.

[0024]

As described above, since the present invention incorporates two start bit detection circuits in an asynchronous serial transmission / reception circuit, it can be used inexpensively as a 2-channel serial transmission / reception device while taking advantage of the asynchronous system. It has a practical effect of being possible. In addition, in the case of serial data transfer, since a register for designating a data output terminal is built in, there is an effect that data can be output to an arbitrary serial line.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional asynchronous serial data transmission / reception device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 reception register 102, 200 baud rate generator 104, 108 start bit detection unit 105 shift clock control unit 107 reception control unit 109 transmission control unit 101 transmission register 106, 110 switching circuit 111 register 400 asynchronous serial data transmission / reception device 401 register

Claims (2)

(57) [Claims] 1. An asynchronous serial data transmitting and receiving device comprising a receiving register, a transmitting register, a start bit detecting means, a notifying means, and an output means, and performing synchronization by detecting a start bit. The reception register is connected to serial data reception terminals of two channels and stores received serial data. The transmission register is connected to serial data transmission terminals of two channels and stores serial data to be transmitted. The start bit detecting means is connected to the serial data receiving terminals of two channels, respectively, and detects the start bit. The notifying means is provided by the start bit detecting means connected to the serial data receiving terminal. When the start bit is detected, it notifies the other party that reception is not possible. Means for selectively storing data from the serial data reception terminal at which the start bit is detected in the reception register; and output means for selecting transmission data from the transmission register to the serial data transmission terminals of two channels. An asynchronous serial data transmission / reception device characterized in that the data is selectively switched and output. 2. The apparatus according to claim 1, wherein a priority is set to the start bit detecting means of the two channels, and when the start bits are simultaneously detected, the output of the start bit detecting means having the priority is given priority. The asynchronous serial data transmitting / receiving device according to claim 1.