JP2004266433A - Method for controlling synchronization and modulator-demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronization controlling method capable of suppressing an increase in a circuit scale and preventing bit slippage even when a multicarrier signal is handled and to provide a modulator-demodulator. <P>SOLUTION: In this synchronization controlling method for controlling a modulator for inputting data transmitted together with a first clock signal CLK1 from a prescribed information processing terminal through a data buffer and modulating the data extracted from the data buffer by digital signal processing to transmit the extracted data in synchronization with an internally generated second clock signal CLK2, the residual amount of the data stored in the data buffer 31 or a residual amount of the buffer is monitored, and the frequency of the second clock signal CLK2 is automatically adjusted in accordance with the volume of the detected residual amount. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a synchronization control method and a modulation / demodulation device that can be used when performing data communication by performing modulation / demodulation by digital signal processing, and more particularly to a synchronization control method and a modulation / demodulation device, or between a plurality of information processing terminals and a multicarrier modulation / demodulation device. This is used to prevent a bit slip due to a timing shift of digital signal processing between the two.
[0002]
[Prior art]
When data communication is performed by connecting a predetermined information processing terminal and a modem, digital signal processing in the modem follows an internal clock generated inside the modem or a specific reference clock provided from the outside. It is processed at the timing of
[0003]
However, when the modem performs digital signal processing using the internal clock, a frequency deviation occurs between the reference clock that determines the timing in the information processing terminal and the internal clock of the modem.
This frequency deviation causes a timing shift in digital signal processing, causing a bit shift, that is, a bit slip. Therefore, data loss or data error may occur.
[0004]
As a synchronous clock generation circuit for preventing a bit slip, a technique disclosed in Patent Document 1 is known.
A modulation device using such a conventional technique is generally configured as shown in FIG. That is, input data (transmission data) input from the information processing terminal to the modulation device is sequentially written to the data buffer in synchronization with the data clock CLK1 output from the information processing terminal.
[0005]
The internal clock CLK2 that determines the timing of modulation in the modulation circuit and the timing of reading data from the data buffer is generated by a clock generation circuit.
In order to prevent the occurrence of bit slip, it is necessary to synchronize the frequency of the internal clock CLK2 with the data clock CLK1. Therefore, a clock comparison circuit is provided.
[0006]
The clock comparison circuit compares the data clock CLK1 with the internal clock CLK2. The control signal output circuit generates a control signal according to the comparison result of the clock comparison circuit. The clock adjusting circuit adjusts the frequency of the internal clock CLK2 according to the control signal output from the control signal output circuit.
On the other hand, a conventional demodulator is configured as shown in FIG. That is, received data input from the transmission line as a modulated signal is demodulated by digital signal processing in a demodulation circuit, and the demodulated received data is output to an information processing terminal via a data buffer.
[0007]
The internal clock CLK1 that determines the timing of outputting the demodulated received data to the information processing terminal is generated by a reproduced clock output circuit. The reproduction clock output circuit reproduces a clock representing the timing based on the received signal.
[Patent Document 1]
JP-A-5-308354
[0008]
[Problems to be solved by the invention]
However, in the conventional modulation device, there is a problem that the circuit scale of the clock comparison circuit provided to prevent bit slip increases. Also, in a modulation device that handles multi-carrier signals so that a plurality of information processing terminals simultaneously communicate using a plurality of communication channels, a data clock input from each information processing terminal to the modulation device is different for each information processing terminal. Therefore, it is necessary to provide clock comparison circuits as many as the number of information processing terminals to be connected.
[0009]
Also, in a demodulation device that handles multicarrier signals in order to simultaneously communicate with a plurality of information processing terminals using a plurality of communication channels, the timing of the received data and the reproduction clock of each communication channel are different from each other. In addition, it is necessary to provide an independent circuit and bus wiring, and the scale of the device becomes large, and it is difficult to mount the circuit and wiring.
[0010]
An object of the present invention is to provide a synchronization control method and a modulation / demodulation device capable of suppressing an increase in circuit scale and preventing a bit slip even when a multicarrier signal is handled.
[0011]
[Means for Solving the Problems]
According to a first aspect of the present invention, data transmitted together with a first clock signal from a predetermined information processing terminal is input via a data buffer and taken out of the data buffer in synchronization with a second clock signal generated internally. A synchronous control method for controlling a modulation device for modulating and transmitting the data by digital signal processing, wherein the remaining amount of data accumulated in the data buffer or the remaining amount of the buffer is monitored and the detected remaining amount is monitored. The frequency of the second clock signal is automatically adjusted in accordance with the magnitude of the second clock signal.
[0012]
According to the first aspect, the frequency of the clock signal is automatically adjusted based on the remaining amount of the data buffer. For example, if the frequency of the first clock signal becomes higher than the second clock signal due to a change in frequency, the amount of data written to the data buffer per unit time becomes larger than the amount of data read from the data buffer per unit time. The remaining amount of data stored in the buffer increases. Therefore, when the remaining amount of data increases, the frequency of the second clock signal is adjusted so as to increase, so that the frequencies of the first clock signal and the second clock signal can be synchronized.
[0013]
Similarly, when the frequency of the first clock signal is lower than that of the second clock signal, the amount of data written to the data buffer per unit time is smaller than the amount of data read from the data buffer per unit time, and the data stored in the data buffer is reduced. The amount of data remaining decreases. Therefore, when the remaining amount of data decreases, the frequency of the second clock signal is adjusted to be lower, so that the frequencies of the first clock signal and the second clock signal can be synchronized.
[0014]
The remaining amount of data stored in the data buffer and the remaining amount of the buffer can be monitored using a relatively simple circuit. That is, since it is not necessary to use a clock comparison circuit having a complicated configuration, the configuration of the demodulation device can be simplified.
According to a second aspect of the present invention, after receiving and demodulating data modulated by digital signal processing, the data is temporarily stored in a data buffer, and read out from the data buffer in synchronization with a clock signal generated by an internal clock generation circuit. A synchronous control method for controlling a demodulator that outputs received data to a predetermined information processing terminal, wherein the remaining amount of data stored in the data buffer or the remaining amount of the buffer is monitored and the detected remaining amount is monitored. The frequency of the clock signal is automatically adjusted according to the magnitude of the clock signal.
[0015]
According to the second aspect, the frequency of the clock signal is automatically adjusted based on the remaining amount of the data buffer. If the timing at which the demodulation device demodulates the received data (frequency of CLK1) and the timing at which the data output by the demodulation device is processed by the information processing terminal (frequency of CLK2) are shifted, the data is written to the data buffer per unit time. There is a difference between the amount of data to be read and the amount of data read from the data buffer and output to the information processing terminal, so that the remaining amount of data stored in the data buffer changes.
[0016]
Therefore, if the frequency of the clock signal (CLK2) is adjusted according to the remaining amount of the data buffer and the remaining amount of the data buffer is controlled so as to be constant, the timing at which the demodulation device demodulates the received data (the frequency of the CLK1) ) Can be synchronized with the timing (frequency of CLK2) at which the data output from the demodulator is processed by the information processing terminal.
[0017]
According to a third aspect of the present invention, data transmitted together with a first clock signal from a predetermined information processing terminal is input via a data buffer, and is taken out from the data buffer in synchronization with a second clock signal generated internally. And a buffer remaining amount monitoring circuit for monitoring the remaining amount of data stored in the data buffer or the remaining amount of the buffer, and a buffer remaining amount monitoring circuit. A control signal output circuit for generating a control signal for changing a clock frequency in accordance with the magnitude of the detected remaining amount; a clock generation circuit for generating the second clock signal; A clock adjusting circuit for adjusting the frequency of the second clock signal in accordance with the control signal.
[0018]
According to the third aspect, similarly to the first aspect, it is not necessary to use a clock comparison circuit having a complicated configuration, so that the configuration of the demodulation device can be simplified.
According to a fourth aspect of the present invention, after data modulated by digital signal processing is received and demodulated, the data is temporarily stored in a data buffer and read out from the data buffer in synchronization with a clock signal generated by an internal clock generation circuit. A demodulator that outputs the received data to a predetermined information processing terminal, a buffer remaining amount monitoring circuit that monitors a remaining amount of data or a remaining amount of the buffer stored in the data buffer, and a buffer remaining amount monitoring circuit. A control signal output circuit for generating a control signal for changing a clock frequency in accordance with the magnitude of the detected remaining amount, a clock generation circuit for generating the clock signal, and a clock signal generation circuit for generating the clock signal. A clock adjusting circuit for adjusting a frequency in accordance with the control signal.
[0019]
In claim 4, as in claim 2, the timing at which the demodulation device demodulates the received data (frequency of CLK1) and the timing at which the data output from the demodulation device is processed by the information processing terminal (frequency of CLK2). Can be synchronized.
6. A digital signal which is input from a plurality of information processing terminals together with an independent first set of clock signals and is synchronized with a second set of internally generated clock signals. In a modulation device that modulates and transmits by processing and generates a multicarrier signal to simultaneously secure a plurality of communication channels corresponding to the plurality of information processing terminals, a predetermined sequence of time slots is used as a timing signal. A time slot generation circuit for outputting, a time division processing modulation circuit for performing time division division modulation processing of a plurality of communication channels simultaneously communicating, and a time division processing modulation for processing data output from a plurality of information processing terminals, respectively. A plurality of transmission data processing circuits to be provided to the circuit, and a plurality of clocks for generating the second set of clock signals. A clock generation circuit, and automatically adjusting a frequency of each of the second set of clock signals generated by the plurality of clock generation circuits in accordance with a plurality of control signals generated by the plurality of transmission data processing circuits and appearing as time division signals. And a time-division processing clock adjusting circuit for adjusting the data to be transmitted to each of the plurality of transmission data processing circuits in synchronization with the first set of clock signals. A data buffer for providing the stored data to the time-division processing modulation circuit in synchronization with the second set of clock signals; and a remaining amount of data stored in the data buffer or a remaining amount of the buffer. A buffer remaining amount monitoring circuit for monitoring the clock amount of the second set of clock signals according to the size of the remaining amount detected by the buffer remaining amount monitoring circuit. A control signal output circuit that outputs a control signal for changing the number at a timing on a predetermined time slot, wherein a first set of clock signals output from the plurality of information processing terminals and the It is characterized in that synchronous control of two sets of clock signals is individually performed for each stream.
[0020]
According to the fifth aspect, it is possible to prevent the occurrence of bit slip for each of a plurality of communication channels performing simultaneous communication, and to simplify the configuration of the demodulation device because it is not necessary to use a clock comparison circuit having a complicated configuration. it can. In addition, since signal processing is performed in a time-division manner in synchronization with the generated time slot, the circuit configuration can be further simplified.
[0021]
According to a sixth aspect of the present invention, in the modulation device according to the fifth aspect, each of the control signal output circuits represents three types of states of increasing, decreasing, and holding the clock frequency in synchronization with the timing of a time slot assigned in advance. It is characterized by outputting a signal.
According to the sixth aspect, a plurality of control signals independent for each stream are output in synchronization with the assigned time slots, so that a common bus wiring can be used to transmit the plurality of control signals. Thereby, the number of wirings is reduced, and the configuration of the device can be simplified.
[0022]
According to a seventh aspect of the present invention, in the modulation device according to the fifth aspect, the time-division processing clock adjustment circuit controls the plurality of control signals corresponding to each of the plurality of communication channels in accordance with the timing of a predetermined time slot. The frequency of the second set of clock signals is obtained from each signal output circuit and adjusted by time division processing for each communication channel.
[0023]
According to the seventh aspect, the time-division processing clock adjustment circuit performs the processing of a plurality of communication channels by the time-division processing. Therefore, it is not necessary to provide a plurality of clock adjustment circuits, and the device configuration can be simplified.
A demodulation for demodulating received signals of a plurality of communication channels which are modulated by digital signal processing and arriving as multicarrier signals for each communication channel, and outputting the demodulated data of the plurality of channels to a destination information processing terminal. In the device, a time-division processing demodulation circuit that demodulates received signals of a plurality of communication channels for each channel by time-division processing, and processes reception data demodulated by the time-division processing demodulation circuit for each communication channel to generate a plurality of destinations. A plurality of reception data processing circuits respectively outputting to the information processing terminal, wherein each of the plurality of reception data processing circuits has a first data output timing for each of the information processing terminals communicating using each communication channel. A clock generation circuit that generates a set of clock signals and the demodulation processing timing of each communication channel are displayed. Receives data in synchronization with a second set of clock signals, temporarily stores the received data, and outputs the stored received data to the information processing terminal in synchronization with the first set of clock signals output by the clock generation circuit. A data buffer to be monitored, a buffer remaining amount monitoring circuit for monitoring a remaining amount of data stored in the data buffer or a remaining amount of the buffer, and a buffer remaining amount monitoring circuit that detects the remaining amount of the buffer according to the size of the remaining amount detected by the buffer remaining amount monitoring circuit. A control signal output circuit for outputting a control signal for changing a frequency of a first set of clock signals, and a clock adjustment circuit for adjusting the frequency of the first set of clock signals generated by the clock generation circuit in accordance with the control signal Are provided.
[0024]
According to the eighth aspect, the occurrence of bit slips can be prevented for each of a plurality of communication channels that perform simultaneous communication, and signal processing is performed in a time-division manner in synchronization with the generated time slots. Becomes possible.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
(First Embodiment)
One embodiment of a synchronization control method and a modulation / demodulation device of the present invention will be described with reference to FIGS. 1 to 3 and FIG. This embodiment corresponds to claims 1 to 4.
[0026]
FIG. 1 is a block diagram showing the configuration of the modulation device of this embodiment. FIG. 2 is a block diagram showing a configuration of the demodulation device of this embodiment. FIG. 3 is a block diagram illustrating a configuration example of a communication system. FIG. 7 is a time chart showing an example of the control signal.
In this embodiment, the information processing terminal, the data buffer, the buffer remaining amount monitoring circuit, the control signal output circuit, the clock generation circuit, and the clock adjusting circuit according to claim 3 are respectively composed of the information processing terminal 11, the data buffer 31, and the buffer remaining amount monitoring circuit. 33, a control signal output circuit 34, a clock generation circuit 36, and a clock adjustment circuit 35.
[0027]
The data buffer, the information processing terminal, the buffer remaining amount monitoring circuit, the control signal output circuit, the clock generation circuit, and the clock adjusting circuit according to the present invention are respectively composed of a data buffer 42, an information processing terminal 23, a buffer remaining amount monitoring circuit 44, It corresponds to the control signal output circuit 45, the clock generation circuit 47, and the clock adjustment circuit 46.
In this embodiment, it is assumed that the present invention is applied to a communication system as shown in FIG. That is, data is transmitted from the data transmission side 10 to the data reception side 20 via the communication network 25.
[0028]
The data transmission side 10 is provided with an information processing terminal 11, a modulation device 12, and a transmission facility 13, and the data reception side 20 is provided with a reception facility 21, a demodulation device 22, and an information processing terminal 23.
The modulation device 12 modulates data output from the information processing terminal 11 by digital signal processing. The transmission data modulated by the modulation device 12 is transmitted to the communication network 25 via the transmission equipment 13.
[0029]
The transmission data transmitted from the data transmission side 10 is input to the receiving equipment 21 via the communication network 25. The received data input to the receiving equipment 21 is input to a demodulation device 22 and demodulated by digital signal processing. The received data demodulated by the demodulation device 22 is output to the information processing terminal 23.
The modulation device 12 is configured as shown in FIG. 1, and the demodulation device 22 is configured as shown in FIG.
[0030]
The information processing terminal 11 of the data transmitting side 10 outputs a clock signal CLK1 indicating the timing together with the data to be transmitted. At the input of the modulation device 12, the output of the information processing terminal 11 appears as input data (CLK1) and a clock signal CLK1. That is, the input data (CLK1) is synchronized with the timing of the clock signal CLK1.
[0031]
The input data (CLK1) is sequentially written to the data buffer 31 in synchronization with the timing of the clock signal CLK1, and this data is temporarily stored inside the data buffer 31.
The data stored in the data buffer 31 is sequentially read from the data buffer 31 in synchronization with the timing of the modulation clock signal CLK2, and applied to the input of the modulation circuit 32 as transmission data (CLK2).
[0032]
The modulation circuit 32 modulates the input transmission data (CLK2) by digital signal processing in synchronization with the timing of the modulation clock signal CLK2. Transmission data (modulated signal) output from the modulation circuit 32 is transmitted to the communication network 25 via the transmission equipment 13.
By the way, the modulated clock signal CLK2 is generated by the clock generation circuit 36. However, when there is a difference between the frequency of the clock signal CLK1 and the frequency of the modulated clock signal CLK2, a bit slip occurs due to a timing difference in digital signal processing in the modulation circuit 32.
[0033]
To prevent this bit slip, it is necessary to synchronize the modulated clock signal CLK2 with the clock signal CLK1. To realize this synchronization, the modulation device 12 is provided with a buffer remaining amount monitoring circuit 33, a control signal output circuit 34, and a clock adjustment circuit 35.
The buffer remaining amount monitoring circuit 33 monitors the remaining amount of data stored in the data buffer 31 or the remaining amount of the buffer. Actually, the read pointer RP indicating the read position on the data buffer 31 and the write pointer WP indicating the write position on the data buffer 31 are monitored, and when the value of the read pointer RP is updated, the difference X (X = RP -WP) is detected as the remaining amount.
[0034]
The control signal output circuit 34 generates a control signal for changing the frequency of the modulated clock signal CLK2 based on the remaining amount (X) detected by the buffer remaining amount monitoring circuit 33. Actually, a ternary signal indicating one of three types of states (up, hold, and down) as shown in FIG. 7 is output according to the remaining amount (X).
For example, when (X−X0 ≧ + x1) is obtained using a predetermined reference value (X0) and threshold value (x1), the output speed (CLK2) of the data buffer 31 is reduced to reduce the input speed. A (lower) signal is output as a control signal in order to approach (CLK1), and when (X−X0 ≦ −x1), the output speed (CLK2) of the data buffer 31 is increased to increase the input side speed. In order to approach the speed (CLK1), a (up) signal is output as a control signal, and otherwise, a (hold) signal is output as a control signal.
[0035]
The clock adjustment circuit 35 controls the clock generation circuit 36 according to the control signal output from the control signal output circuit 34, and performs fine adjustment of the frequency of the modulated clock signal CLK2. For example, when a (down) signal is input as a control signal, the frequency of the modulated clock signal CLK2 is controlled to be lowered over a certain period, and when a (up) signal is input, it is controlled over a certain period. The frequency of the modulated clock signal CLK2 is controlled to be increased, and when a (hold) signal is input, the frequency is fixed.
[0036]
With such control, the modulated clock signal CLK2 generated by the clock generation circuit 36 is automatically adjusted to be synchronized with the timing of the clock signal CLK1. Therefore, occurrence of bit slip is prevented.
On the other hand, the demodulation device 22 includes a demodulation circuit 41, a data buffer 42, a clock generation circuit 43, a buffer remaining amount monitoring circuit 44, a control signal output circuit 45, a clock adjustment circuit 46, and a clock generation circuit 47 as shown in FIG. I have.
[0037]
Received data input from the communication network 25 as a modulation signal is demodulated by a demodulation circuit 41 at timing synchronized with the clock signal CLK1 by digital signal processing. The received data (CLK1) demodulated by the demodulation circuit 41 is written into the data buffer 42, temporarily stored, read out in synchronization with the clock signal CLK2, and sent out as output data (CLK2). The output data (CLK2) and the clock signal CLK2 are input to the information processing terminal 23.
[0038]
A clock signal CLK1 that determines the timing of digital signal processing in the demodulation circuit 41 is generated by a clock generation circuit 43. The frequency of the clock signal CLK1 is determined in advance by communication between the data transmission side 10 and the data reception side 20, and is assigned to the clock generation circuit 43. Therefore, the frequency of the clock signal CLK1 is constant.
[0039]
On the other hand, the clock signal CLK2 that determines the timing of transmitting the received data to the information processing terminal 23 is generated by the clock generation circuit 47.
If the frequencies of the two clock signals CLK1 and CLK2 are different, a bit slip may occur. Therefore, in order to synchronize the clock signal CLK2 with the clock signal CLK1, a buffer remaining amount monitoring circuit 44, a control signal output circuit 45, and a clock adjustment circuit 46 are provided.
[0040]
The buffer remaining amount monitoring circuit 44 monitors the remaining amount of data in the data buffer 42 or the remaining amount of the buffer similarly to the buffer remaining amount monitoring circuit 33 described above. Actually, the read pointer RP indicating the read position on the data buffer 42 and the write pointer WP indicating the write position on the data buffer 42 are monitored, and when the value of the read pointer RP is updated, the difference X (X = RP -WP) is detected as the remaining amount.
[0041]
The control signal output circuit 45 generates a control signal for changing the frequency of the clock signal CLK2 based on the remaining amount (X) detected by the buffer remaining amount monitoring circuit 44. Actually, a ternary signal indicating one of three types of states (up, hold, and down) as shown in FIG. 7 is output according to the remaining amount (X).
The clock adjustment circuit 46 controls the clock generation circuit 47 according to the control signal output from the control signal output circuit 45, and performs fine adjustment of the frequency of the clock signal CLK2. For example, when a (lower) signal is input as a control signal, control is performed such that the frequency of the clock signal CLK2 is reduced for a certain period, and when a (up) signal is input, the clock is higher for a certain period. Control is performed to increase the frequency of the signal CLK2, and when a (hold) signal is input, the frequency is fixed.
[0042]
With such control, the clock signal CLK2 generated by the clock generation circuit 47 is synchronized with the clock signal CLK1. This clock signal CLK2 is applied to the data buffer 42 and the information processing terminal 23.
(Second embodiment)
One embodiment of the synchronization control method and the modulation / demodulation device of the present invention will be described with reference to FIG. 4 to FIG. 6 and FIG. This form corresponds to claims 5 to 8.
[0043]
FIG. 4 is a block diagram showing a configuration of the modulation device of this embodiment. FIG. 5 is a block diagram showing the configuration of the demodulation device of this embodiment. FIG. 6 is a block diagram illustrating a configuration example of a communication system. FIG. 8 is a time chart showing an example of the control signal.
This embodiment is a modification of the first embodiment, and the basic operation for synchronizing the timing of the clock signal is the same as that of the first embodiment. The following description is omitted for the same parts.
[0044]
In this embodiment, an information processing terminal, a time slot generation circuit, a time division processing modulation circuit, a transmission data processing circuit, a clock generation circuit, a time division processing clock adjustment circuit, a data buffer, a buffer remaining amount monitoring circuit, and a control signal The output circuits include an information processing terminal 55, a time slot generation circuit 62, a time division processing modulation circuit 64, a data processing unit 63, a clock generation circuit 65, a time division processing clock adjustment circuit 66, a data buffer 67, and a buffer remaining amount monitoring circuit. 68 and the control signal output circuit 69.
[0045]
The information processing terminal, the time-division processing demodulation circuit, the reception data processing circuit, the clock generation circuit, the data buffer, the buffer remaining amount monitoring circuit, the control signal output circuit, and the clock adjustment circuit according to claim 8 are respectively composed of the information processing terminal 55, It corresponds to the time division demodulation circuit 71, the data processing unit 74, the clock generation circuit 79, the data buffer 75, the buffer remaining amount monitoring circuit 76, the control signal output circuit 77, and the clock adjustment circuit 78.
[0046]
In this embodiment, it is assumed that the present invention is applied to a communication system as shown in FIG. That is, the plurality of information processing terminals 55 (1), 55 (2), 55 (3) are connected to the communication station 51 and the information processing terminals 58 (1), 58 connected to the respective communication stations 52 via the communication network 25. Communication is made between (2) and 58 (3).
The communication station 51 handles multicarrier signals in order to secure a plurality of independent communication channels used for communication by the plurality of information processing terminals 55 (1), 55 (2), and 55 (3).
[0047]
The communication station 51 is provided with a transmission / reception facility 53 and a modem 54. Each communication station 52 (1), 52 (2), 52 (3) is provided with a transmission / reception facility 56 and a modem 57, respectively.
The data transmitted by the information processing terminal 55 (1) is modulated by the modem 54 and transmitted to the communication network 25 via the transmission / reception equipment 53, and the transmission / reception equipment 56 of the communication station 52 to which the destination information processing terminal 58 is connected. , Demodulated by the modem 57 and input to the information processing terminal 58. The same applies to the information processing terminals 55 (2) and 55 (3).
[0048]
The data transmitted by each of the information processing terminals 58 (1), 58 (2), 58 (3) is modulated by the modulation / demodulation device 57, transmitted to the communication network 25 via the transmission / reception equipment 56, and transmitted to the communication station 51. After being received by the transmission / reception equipment 53 and demodulated by the modem 54, it is input to the destination information processing terminal 55.
[0049]
The modulation and demodulation device 54 of the communication station 51 is composed of a modulation device and a demodulation device. In order to simultaneously process communications of a plurality of information processing terminals 55 as multicarrier signals, a multicarrier modulation device 60 shown in FIG. And a multi-carrier demodulation device 70 shown in FIG.
The multicarrier modulation device 60 shown in FIG. 4 includes a modulation unit 61, a time slot generation circuit 62, and a plurality of data processing units 63 (1), 63 (2), 63 (3),. Although only three data processing units 63 are shown in FIG. 4, the number of data processing units 63 can be increased as necessary.
[0050]
The modulation section 61 includes a time-division processing modulation circuit 64, a clock generation circuit 65, and a time-division processing clock adjustment circuit 66. Each data processing section 63 includes a data buffer 67, a buffer remaining amount monitoring circuit 68, and a control circuit. A signal output circuit 69 is provided.
Further, the modulation section 61, the time slot generation circuit 62, and the plurality of data processing sections 63 (1), 63 (2), 63 (3),... Use the data bus B1, the time slot bus B2, and the control bus B3. Connected through.
[0051]
Signals transmitted from the information processing terminals 55 (1), 55 (2), 55 (3) for data transmission include clock signals CLK1-n (n: 1, 2, 3,...) The data is input to each data processing unit 63 of the multicarrier modulation device 60 as synchronized input data (CLK1-n).
The input data (CLK1-n) is sequentially written and temporarily stored in the data buffer 67 at a timing synchronized with the clock signal CLK1-n. The data stored in the data buffer 67 is read from the data buffer 67 in synchronization with the modulation clock signal CLK2-n, and is input to the time division processing modulation circuit 64 via the data bus B1, and the time division processing modulation circuit The signal is modulated by digital signal processing at a timing synchronized with the modulation clock signal CLK2-n inside the 64. The signal modulated by the time-division processing modulation circuit 64 is output from the modulation unit 61 as transmission data.
[0052]
The time slot generation circuit 62 generates a time slot signal indicating the timing of each communication channel in order to use the communication channel and each bus (B1, B2, B3) in a time-division manner.
The time slot signal output from the time slot generating circuit 62 is applied to each data processing section 63 and modulation section 61 via the time slot bus B2.
[0053]
The data read from each data buffer 67 is input to the time-division processing modulation circuit 64 via the data bus B1 at the timing of the time slot of the corresponding channel.
The modulated clock signal CLK2-n of each channel is independently generated by the clock generation circuit 65. The modulated clock signal CLK2-n of each channel generated by the clock generation circuit 65 is applied to the time-division processing modulation circuit 64 and to each data processing unit 63 via the time slot bus B2.
[0054]
The modulated clock signal CLK2-n input to each data processing unit 63 appears as a discontinuous pulse on each time slot output from the time slot generation circuit 62.
The time-division processing modulation circuit 64 sequentially executes time-division modulation processing of transmission data on a plurality of communication channels in synchronization with each modulated clock signal CLK2-n and time slot.
[0055]
By the way, if the frequency of each clock signal CLK1-n and the frequency of each modulated clock signal CLK2-n are shifted from each other as in the first embodiment, a bit slip may occur.
Therefore, it is necessary to control each modulated clock signal CLK2-n generated by the clock generation circuit 65 so as to be synchronized with each clock signal CLK1-n. To this end, each data processing section 63 is provided with a buffer remaining amount monitoring circuit 68 and a control signal output circuit 69, and the modulation section 61 is provided with a time division processing clock adjustment circuit 66.
[0056]
The buffer remaining amount monitoring circuit 68 monitors the remaining amount of data stored in the data buffer 67 or the remaining amount of the buffer. The control signal output circuit 69 generates a control signal corresponding to the increase or decrease in the remaining amount detected by the buffer remaining amount monitoring circuit 68 in order to control the frequency of the modulated clock signal CLK2-n of the corresponding channel.
The control signal output from the control signal output circuit 69 of each channel is input to the time division processing clock adjustment circuit 66 via the control bus B3 at a timing synchronized with the time slot assigned to each channel.
[0057]
In the example of FIG. 8, the time slots corresponding to the channels CH1, CH2, CH3, CH4, CH5,... Are “00”, “01”, “00”, “10”, “00”,. A 2-bit control signal with the value of appears. A control signal having a value of “01” indicates increasing the frequency of the modulated clock signal CLK2-n, a control signal having a value of “10” indicates decreasing the frequency of the modulated clock signal CLK2-n, and having a value of “00”. The value control signal indicates that the frequency of the modulated clock signal CLK2-n is maintained.
[0058]
That is, in the example of FIG. 8, the frequency of the modulated clock signal CLK2-1 is maintained, the frequency of the modulated clock signal CLK2-2 is increased, the frequency of the modulated clock signal CLK2-3 is maintained, and the frequency of the modulated clock signal CLK2-4 is maintained. Indicates that the frequency of the modulated clock signal CLK2-5 is maintained.
The time-division processing clock adjustment circuit 66 takes in the control signal of each channel from the control bus B3 in synchronization with the timing of each time slot, and independently adjusts the frequency of the modulated clock signal CLK2-n of each channel according to the control signal. The clock generation circuit 65 is controlled by time division processing so as to make fine adjustment.
[0059]
Since such an operation is performed, it is possible to synchronize each modulated clock signal CLK2-n with each clock signal CLK1-n for all communication channels, and to generate a bit slip due to a timing shift in digital signal processing. Can be prevented.
On the other hand, the multicarrier demodulation device 70 shown in FIG. 5 includes a time-division processing demodulation circuit 71, a clock generation circuit 72, a time slot generation circuit 73, and a plurality of data processing units 74 (1), 74 (2), 74 (3). ,... Although only three data processing units 74 are shown in FIG. 5, the number of data processing units 74 can be increased as necessary.
[0060]
Each data processing unit 74 includes a data buffer 75, a buffer remaining amount monitoring circuit 76, a control signal output circuit 77, a clock adjustment circuit 78, and a clock generation circuit 79.
Further, the time-division processing demodulation circuit 71, the time slot generation circuit 73, and the plurality of data processing units 74 (1), 74 (2), 74 (3),. Connected.
[0061]
Since the plurality of information processing terminals 55 (1), 55 (2), 55 (3),... Communicate simultaneously via the modem 54, multi-carrier demodulation is performed via the communication network 25 and the transmission / reception equipment 53. The received data input to device 70 appears as a multi-carrier modulated signal. That is, received signals of a plurality of communication channels appear in a form superimposed on carriers having different frequencies.
[0062]
The clock generation circuit 72 generates demodulated clock signals CLK1-1, CLK1-2, CLK1-3,... Indicating the timing of received data of each communication channel. The frequency of each demodulated clock signal CLK1-n (n: 1, 2, 3,...) Is determined in advance.
The time-division processing demodulation circuit 71 sequentially processes received data input as a multi-carrier modulation signal for each channel by time-division digital signal processing, and converts the received data into each demodulated clock signal CLK1-n input from the clock generation circuit 72. Demodulate synchronously.
[0063]
The time slot generating circuit 73 generates a time slot signal representing the timing of each communication channel.
The received data demodulated for each channel by the time-division processing demodulation circuit 71 is applied as a time-division multiplexed signal to the data buffer 75 of each data processing unit 74 via the data bus B4.
[0064]
Each data processing unit 74 takes in the received data from the data bus B4 at the timing of the time slot allocated to the corresponding channel, and sequentially transfers the received data to the data buffer 75 in synchronization with the corresponding demodulated clock signal CLK1-n. Write to.
The received data temporarily stored in data buffer 75 is read from data buffer 75 in synchronization with clock signal CLK2-n generated by clock generation circuit 79, and is output to corresponding information processing terminal 55. . The clock signal CLK2-n is applied to the information processing terminal 55 together with the received data.
[0065]
In this multi-carrier demodulation device 70, the frequency of clock signal CLK2-n generated by each clock generation circuit 79 is set equal to the frequency of demodulation clock signal CLK1-n generated by clock generation circuit 72 in order to prevent the occurrence of bit slip. Control to synchronize.
For this purpose, each data processing section 74 is provided with a buffer remaining amount monitoring circuit 76, a control signal output circuit 77, and a clock adjustment circuit 78.
[0066]
Each buffer remaining amount monitoring circuit 76 monitors the remaining amount of data stored in the data buffer 75 or the remaining amount of the buffer. The control signal output circuit 77 generates a control signal for adjusting the frequency of the clock signal CLK2-n according to the increase or decrease in the remaining amount detected by the buffer remaining amount monitoring circuit 76. The clock adjustment circuit 78 finely adjusts the frequency of the clock signal CLK2-n according to the control signal output from the control signal output circuit 77.
[0067]
Since such an operation is performed, the clock signals CLK2-n can be synchronized with the demodulated clock signals CLK1-n for all the channels for communication, and the occurrence of bit slips due to a timing shift in digital signal processing can be achieved. Can be prevented.
[0068]
【The invention's effect】
As described above, according to the present invention, when a modulation clock is generated by an internal reference clock and digital modulation processing and digital demodulation processing are performed, clock synchronization is realized without using a clock comparison circuit or a clock recovery circuit. Since the bit slip can be prevented, the configuration of the circuit can be simplified.
[0069]
Also, when connecting to multiple information processing terminals that handle clock signals independent of each other and processing multiple communications using multicarrier signals, clock synchronization is realized by time-division processing, simplifying the circuit configuration. In addition, a circuit configuration with reduced power consumption can be realized.
Therefore, a particularly large effect can be obtained in a multi-carrier modulation device, a multi-carrier demodulation device, or a multi-carrier modulation / demodulation device which simultaneously processes several tens of lines.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a modulation device according to a first embodiment.
FIG. 2 is a block diagram illustrating a configuration of a demodulation device according to the first embodiment.
FIG. 3 is a block diagram illustrating a configuration example of a communication system.
FIG. 4 is a block diagram illustrating a configuration of a modulation device according to a second embodiment.
FIG. 5 is a block diagram illustrating a configuration of a demodulation device according to a second embodiment.
FIG. 6 is a block diagram illustrating a configuration example of a communication system.
FIG. 7 is a time chart illustrating an example of a control signal.
FIG. 8 is a time chart illustrating an example of a control signal.
FIG. 9 is a block diagram illustrating a configuration of a conventional modulation device.
FIG. 10 is a block diagram illustrating a configuration of a conventional demodulation device.
[Explanation of symbols]
10 Data transmission side
11 Information processing terminal
12 Modulation device
13 Transmission equipment
20 Data receiving side
21 Receiving equipment
22 Demodulator
23 Information processing terminal
25 Communication Network
31 Data buffer
32 Modulation circuit
33 Buffer remaining amount monitoring circuit
34 Control signal output circuit
35 Clock adjustment circuit
36 Clock generation circuit
41 Demodulation circuit
42 Data Buffer
43 Clock Generation Circuit
44 Buffer remaining amount monitoring circuit
45 Control signal output circuit
46 Clock adjustment circuit
47 Clock generation circuit
51, 52 communication stations
53 Transmission / reception equipment
54 modem
55 Information processing terminal
56 Transmission / reception equipment
57 Modem
58 Information processing terminal
60 Multi-carrier modulator
61 Modulation section
62 Time slot generation circuit
63 Data processing unit
64 time-division processing modulation circuit
65 Clock generation circuit
66 Time-division processing clock adjustment circuit
67 Data buffer
68 Buffer remaining amount monitoring circuit
69 Control signal output circuit
70 Multi-carrier demodulator
71 Time-division processing demodulation circuit
72 Clock generation circuit
73 Time slot generation circuit
74 Data processing unit
75 Data buffer
76 Buffer remaining amount monitoring circuit
77 Control signal output circuit
78 Clock adjustment circuit
79 Clock Generation Circuit

Claims (8)

Data sent from a predetermined information processing terminal together with a first clock signal is input via a data buffer, and data taken out of the data buffer is synchronized with a second clock signal generated internally by a digital signal. In a synchronization control method for controlling a modulation device that modulates and transmits by processing,
Monitoring the remaining amount of data stored in the data buffer or the remaining amount of the buffer, and automatically adjusting the frequency of the second clock signal according to the detected size of the remaining amount. Synchronous control method. After receiving and demodulating data modulated by digital signal processing, the data temporarily stored in a data buffer and received data read out from the data buffer in synchronization with a clock signal generated by an internal clock generation circuit are determined. In a synchronous control method for controlling a demodulation device that outputs to an information processing terminal,
Monitoring the remaining amount of data stored in the data buffer or the remaining amount of the buffer, and automatically adjusting the frequency of the clock signal according to the size of the detected remaining amount. Control method. Data sent from a predetermined information processing terminal together with a first clock signal is input via a data buffer, and data taken out of the data buffer is synchronized with a second clock signal generated internally by a digital signal. In a modulation device that modulates and transmits by processing,
A buffer remaining amount monitoring circuit that monitors the remaining amount of data or the remaining amount of the buffer stored in the data buffer;
A control signal output circuit that generates a control signal for changing a clock frequency according to the size of the remaining amount detected by the buffer remaining amount monitoring circuit;
A clock generation circuit that generates the second clock signal;
A modulation circuit for adjusting a frequency of the second clock signal generated by the clock generation circuit in accordance with the control signal. After receiving and demodulating data modulated by digital signal processing, the data temporarily stored in a data buffer and received data read out from the data buffer in synchronization with a clock signal generated by an internal clock generation circuit are determined. Demodulation device that outputs to the information processing terminal of
A buffer remaining amount monitoring circuit that monitors the remaining amount of data or the remaining amount of the buffer stored in the data buffer;
A control signal output circuit that generates a control signal for changing a clock frequency according to the size of the remaining amount detected by the buffer remaining amount monitoring circuit;
A clock generation circuit that generates the clock signal;
A demodulating device comprising: a clock adjusting circuit for adjusting a frequency of the clock signal generated by the clock generating circuit in accordance with the control signal. Data sent together with a first set of independent clock signals from a plurality of information processing terminals is input, and the data is modulated by digital signal processing at timing synchronized with a second set of internally generated clock signals. A modulator for transmitting and generating a multi-carrier signal to simultaneously secure a plurality of communication channels corresponding to the plurality of information processing terminals,
A time slot generation circuit that outputs a predetermined sequence of time slots as a timing signal,
A time-division processing modulation circuit that performs time-division modulation processing of a plurality of communication channels that communicate simultaneously,
A plurality of transmission data processing circuits that process data output from a plurality of information processing terminals and provide the processed data to the time division processing modulation circuit,
A plurality of clock generation circuits for generating the second set of clock signals;
Time division processing for automatically adjusting the frequency of each of the second set of clock signals generated by the plurality of clock generation circuits in accordance with a plurality of control signals generated by the plurality of transmission data processing circuits and appearing as time division signals A clock adjustment circuit, and each of the plurality of transmission data processing circuits includes:
The data output from the information processing terminal is input in synchronization with the first set of clock signals and temporarily stored, and the accumulated data is synchronized with the second set of clock signals in the time division processing. A data buffer for the modulation circuit;
A buffer remaining amount monitoring circuit that monitors the remaining amount of data or the remaining amount of the buffer stored in the data buffer;
A control signal output for outputting a control signal for changing the frequency of the second set of clock signals in accordance with the size of the remaining amount detected by the buffer remaining amount monitoring circuit at a timing on a predetermined time slot. Circuit and
And a synchronization device that individually controls the synchronization of the first set of clock signals and the second set of clock signals output from the plurality of information processing terminals for each stream. 6. The modulation device according to claim 5, wherein each of the control signal output circuits outputs a control signal representing three types of states of increase, decrease, and holding of a clock frequency in synchronization with a timing of a time slot assigned in advance. A modulation device characterized by the above-mentioned. 6. The modulation device according to claim 5, wherein the time-division processing clock adjustment circuit outputs a plurality of control signals corresponding to each of a plurality of communication channels from the plurality of control signal output circuits according to a predetermined time slot timing. A modulator configured to acquire and adjust a frequency of the second set of clock signals by time division processing for each communication channel. A demodulation device for demodulating received signals of a plurality of communication channels arriving as a multi-carrier signal which are modulated by digital signal processing, for each communication channel, and outputting the demodulated data of the plurality of channels to a destination information processing terminal.
A time-division processing demodulation circuit for demodulating the received signals of the plurality of communication channels for each channel by time-division processing,
A plurality of reception data processing circuits for processing the reception data demodulated by the time-division processing demodulation circuit for each communication channel and outputting the processed data to a plurality of destination information processing terminals, respectively, in each of the plurality of reception data processing circuits; Is
A clock generation circuit for generating a first set of clock signals representing data output timing for each of the information processing terminals communicating using each communication channel;
The first set of clock signals, in which the received data is fetched and temporarily stored in synchronization with a second set of clock signals representing the timing of demodulation processing of each communication channel, and the stored received data is output by the clock generation circuit. A data buffer that outputs to the information processing terminal in synchronization with
A buffer remaining amount monitoring circuit that monitors the remaining amount of data or the remaining amount of the buffer stored in the data buffer;
A control signal output circuit that outputs a control signal for changing the frequency of the first set of clock signals according to the size of the remaining amount detected by the buffer remaining amount monitoring circuit;
A demodulating device, comprising: a clock adjusting circuit for adjusting a frequency of the first set of clock signals generated by the clock generating circuit in accordance with the control signal.

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