JP7311287B2 - Transmission device and transmission device control method - Google Patents

Description

The present invention relates to a transmission device and a control method for the transmission device.

As a technique for generating a clock signal from a broadcast signal, there is a technique disclosed in Patent Document 1.

In the technique of Patent Document 1, the clock signal is generated using the time information included in the broadcast signal.

Japanese Patent Application Laid-Open No. 2001-028738

By the way, the technique disclosed in Patent Document 1 has a problem that the circuit configuration becomes complicated because a circuit for acquiring time information from the broadcast signal is required. In addition, when the acquired data contains a fluctuation component such as jitter, the clock signal also fluctuates, making it difficult to synchronize other circuits.

Also, there is a problem that data interpolation cannot be performed when the data rate is very large with respect to the clock rate or when the data rate is in a non-integer relationship.

SUMMARY OF THE INVENTION The present invention is intended to solve such problems, and provides a transmission device and a control method for the transmission device that can obtain a clock signal synchronized with a transmission source with a simple circuit configuration. be.

In order to solve the above-mentioned problems, the present invention provides receiving means for receiving a modulated signal, demodulating means for demodulating the signal received by the receiving means to generate digital data, and demodulation by the demodulating means. storage means for storing the obtained digital data; reading means for reading the digital data from the storage means; modulating means for modulating the digital data read by the reading means; a sending means for generating a clock signal and supplying it to the reading means and the modulating means; and the supplying means according to the number of the digital data stored in the storing means. adjustment means for adjusting the frequency of the clock signal to be used as the clock signal; and conversion means provided before or after the storage means for converting the sampling frequency of the digital data by subjecting the digital data to interpolation processing. and wherein, in the interpolation processing, the transforming means transforms the sampling frequency into a non-integer relationship with a signal processing device, and increases the digital data in an axis direction different from the time axis. The sampling frequency is increased or decreased by multiplying the data amount by a non-integer multiple, and the clock signal that operates the signal processing device is kept constant when the data amount is increased by the non-integer multiple. characterized by increasing or decreasing the conversion frequency .
With such a configuration, it is possible to obtain a stable clock signal with a simple circuit configuration. Moreover, according to such a configuration, the sampling frequency can be converted without increasing the clock frequency unnecessarily.

Further, in the present invention, the adjustment means calculates a difference value between the number of the digital data stored in the storage means and a predetermined reference value, and when the difference value is positive, the value and if the differential value is negative, the frequency of the clock signal is decreased in accordance with the value.
According to such a configuration, it is possible to reliably detect the number of digital data stored in the storage means and obtain a clock signal synchronized with the transmission source without missing any data.

Further, according to the present invention, the adjustment means obtains the number of the digital data from the difference value between the write address and the read address of the storage means, and calculates the difference value between the obtained number of the digital data and a predetermined reference value. If the differential value is positive, the frequency of the clock signal is increased according to the value, and if the differential value is negative, the frequency of the clock signal is decreased according to the value. It is characterized by
According to such a configuration, it is possible to reliably detect the number of digital data stored in the storage means having no function of outputting the number of stored digital data, and to obtain a clock signal synchronized with the transmission source. can be done.

Further, the present invention comprises a receiving step of receiving a modulated signal, a demodulating step of demodulating the signal received in the receiving step to generate digital data, and the digital data obtained by demodulation in the demodulating step. in a storage unit, a reading step of reading the digital data from the storage unit, a modulating step of modulating the digital data read out in the reading step, and a signal modulated in the modulating step a transmitting step of transmitting, a supplying step of generating a clock signal and supplying it to the reading step and the modulating step, and the clock generated by the supplying step according to the number of the digital data stored in the storage unit an adjustment step of adjusting the frequency of a signal; and a conversion step of converting a sampling frequency of the digital data by performing an interpolation process on the digital data before or after the storage unit. and in the conversion step, in the interpolation processing, the signal processing device converts the sampling frequency into a non-integer relationship, increases the digital data in a direction different from the time axis, and converts the data amount to a non-integer By doubling, the sampling frequency is increased or decreased, and in the non-integer multiple, the clock signal operating the signal processing device is kept constant while increasing or decreasing the sampling frequency. It is characterized by decreasing
According to such a method, it is possible to obtain a stable clock signal with a simple circuit configuration.

According to the present invention, it is possible to provide a transmission device and a method of controlling the transmission device that can obtain a clock signal synchronized with a transmission source with a simple circuit configuration.

1 is a diagram showing a configuration example of a transmission device according to a first embodiment of the present invention; FIG. FIG. 5 is a diagram showing a configuration example of a transmission device according to a second embodiment of the present invention; FIG. 11 is a diagram showing a configuration example of a transmission device according to a third embodiment of the present invention; FIG. 11 is a diagram showing a configuration example of a transmission device according to a fourth embodiment of the present invention; FIG. 11 is a diagram showing a configuration example of a transmission device according to a fifth embodiment of the present invention; It is a figure which shows the structural example which concerns on deformation|transformation embodiment of this invention.

Next, embodiments of the present invention will be described.

(A) Description of Configuration of First Embodiment of the Present Invention FIG. 1 is a diagram showing a configuration example of a transmission apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the transmission device 10 according to the first embodiment of the present invention includes a demodulation section 11, a storage section 12, a signal processing section 13, a memory 14, a modulation section 15, a reference value output section 16, and a subtraction section 17. , a loop filter 18 , a data voltage converter 19 , an LPF (Low Pass Filter) 20 , a VCO (Voltage Controlled Oscillator) 21 , and clock signal generators 22 and 23 .

Here, the demodulator 11 receives an analog broadcast signal, outputs data (DATA) as a digital signal obtained by performing demodulation processing, and extracts a clock signal included in the broadcast signal. , as a write clock signal (WCLK).

The storage unit 12 is configured by, for example, a FIFO (First In First Out) memory or a RAM (Random Access Memory), and stores data supplied from the demodulator 11 in synchronization with a write clock signal. It is read in synchronization with the read clock signal (RCLK) and supplied to the signal processing unit 13 . The storage unit 12 also notifies the subtraction unit 17 of the number of stored data (Number of DATA).

The signal processing unit 13 reads the data stored in the storage unit 12, performs predetermined signal processing, and outputs the data.

The memory 14 stores data supplied from the signal processing unit 13 , reads data in synchronization with a read clock signal (RCLK) supplied from the modulation unit 15 , and supplies the data to the modulation unit 15 .

The modulator 15 modulates the data supplied from the memory 14 to generate and output a broadcast signal as an analog signal.

The reference value output unit 16 stores a reference value as a reference for the number of data stored in the storage unit 12, and outputs the reference value.

The subtraction unit 17 subtracts the reference value supplied from the reference value output unit 16 from the stored number of data (Number of DATA) supplied from the storage unit 12 and outputs the result.

The loop filter 18 is configured by, for example, an LPF (Low Pass Filter) based on IIR (Infinite Impulse Response) or the like, and smoothes and outputs the data output from the subtraction unit 17 by filtering. In the case of using analog electronic components, for example, a lag-lead filter may be used.

The data voltage converter 19 is composed of, for example, a D/A (Digital to Analog) converter or a PWM (Pulse Width Modulation) converter, and converts a digital signal into an analog signal (a signal whose voltage changes continuously). and output.

The LPF 20 attenuates harmonic components (components generated by switching or the like) contained in the analog signal output from the data voltage converter 19 and outputs an average value of the data voltage converter.

The VCO 21 oscillates at a frequency based on the signal supplied from the LPF 20 and outputs a sine wave or rectangular wave.

The clock signal generator 22 generates a clock signal based on the signal supplied from the VCO 21 and supplies it to the memory 12 as a read clock signal (RCLK).

The clock signal generator 23 generates a clock signal (CLK) based on the signal supplied from the VCO 21 and supplies it to the modulator 15 as a clock signal.

In FIG. 1, the demodulation section 11, the modulation section 15, the data voltage conversion section 19, the LPF 20, the VCO 21, and the clock signal generation sections 22 and 23 are configured as individual electronic circuits, and the rest are configured as logic circuits. be done. Note that the configuration described above is an example, and these may be implemented as an arbitrary combination of electronic circuits, logic circuits, or software.

(B) Description of the operation of the first embodiment of the present invention Next, the operation of the first embodiment of the present invention will be described. When the demodulator 11 receives a broadcast signal, the demodulator 11 demodulates the broadcast signal, which is an analog signal, and converts the resulting signal into digital data as a digital signal (hereinafter referred to as simply referred to as "data") and a clock signal. Data such as video signals included in the broadcast signal is a high-precision clock signal possessed by the head end (for example, a clock signal output from a rubidium oscillator (or a GPS (Global Positioning System) signal or a PTP (Precision Time Protocol) signal). Since the data is transmitted in synchronization with the signal )), the number of data included in the broadcast signal per unit time is constant. However, the clock signal (WCLK) output from the demodulator 11 operates with a different clock signal that uses the clock signal of the demodulator 11 itself, which is different from the clock signal of the transmission source. have a phase difference.

Data output from the demodulator 11 is stored in the memory 12 in synchronization with the write clock signal (WCLK). The storage unit 12 has a capacity capable of storing a predetermined number (for example, 32) of data. The storage unit 12 notifies the subtraction unit 17 of the number of stored data. For example, when 17 data are stored, the subtraction unit 17 is notified of "17".

The reference value output unit 16 stores the reference value of the data stored in the storage unit 12, and outputs the reference value. The reference value can be, for example, a value that is half the number of data that can be stored (for example, "16" if 32 data can be stored). Of course, other values may be used.

The subtraction unit 17 subtracts the reference value output from the reference value output unit 16 from the number of stored data notified from the storage unit 12 and outputs the result. For example, when the number of stored data is "17" and the reference value is "16", "1" (=17-16) is output.

The loop filter 18 performs smoothing processing (low-pass filtering) on the data output from the subtraction unit 17, and outputs the obtained data.

The data voltage converter 19 converts the data (digital signal) supplied from the loop filter 18 into a voltage (analog signal) by D/A conversion or PWM conversion, and outputs the voltage.

The LPF 20 attenuates and outputs harmonic components (components generated by switching or the like) included in the analog signal supplied from the data voltage converter 19 .

The VCO 21 adjusts and outputs the oscillation frequency based on the signal supplied from the LPF 20 . For example, if the signal supplied from the LPF 20 has a positive value, the oscillation frequency is increased according to that value, and if the signal supplied from the LPF 20 has a negative value, the oscillation frequency is increased according to that value. and maintain the same oscillation frequency when the signal supplied from the LPF 20 is "0". As a result, when the number of data stored in the storage unit 12 is larger than the reference value supplied from the reference value output unit 16, the oscillation frequency of the VCO 21 increases, and the number of data stored in the storage unit 12 increases. When the number is smaller than the reference value supplied from the reference value output section 16, the oscillation frequency of the VCO 21 decreases.

The clock signal generator 22 generates a clock signal based on the signal supplied from the VCO 21 and supplies it to the storage unit 12 as a read clock signal (RCLK). The clock signal generator 23 also generates a clock signal (CLK) based on the signal supplied from the VCO 21 and supplies the clock signal (CLK) to the modulator 15 .

The signal processing unit 13 reads data stored in the storage unit 12 in synchronization with a read clock signal (RCLK) supplied from the clock signal generating unit 22 . As described above, the frequency of the read clock signal supplied from the clock signal generating section 22 changes according to the number of data stored in the storage section 12 . More specifically, when the number of data stored in the storage unit 12 is greater than the reference value output from the reference value output unit 16, the frequency increases and the number of data stored in the storage unit 12 increases. is smaller than the reference value output from the reference value output unit 16, the frequency decreases. As a result, the signal processing unit 13 performs reading so that the number of data items stored in the storage unit 12 approaches the reference value.

As described above, the number of data per unit time included in the broadcast signal is constant with the precision of the rubidium oscillator. becomes approximately constant.

The signal processing unit 13 performs predetermined signal processing on the data read from the storage unit 12 and outputs the processed data. Data output from the signal processing unit 13 is stored in the memory 14 .

The modulation unit 15 reads out data from the memory 14 in synchronization with the clock signal (CLK) supplied from the clock signal generation unit 23, performs modulation processing to generate an analog signal, and then outputs it as a broadcast signal. Here, the clock signal output from the clock signal generator 23 is based on the signal supplied from the VCO 21, and as described above, the frequency of the signal output from the VCO 21 is substantially constant. The broadcast signal output from is also controlled to have a constant data rate.

As described above, according to the first embodiment of the present invention, the read clock signal is controlled so that the number of data stored in the storage unit 12 becomes equal to the reference value. can obtain a clock signal synchronized with

(C) Description of Configuration of Second Embodiment of the Present Invention Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram showing a configuration example of a transmission device 10A according to the second embodiment of the present invention. In FIG. 2, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and descriptions thereof are omitted. 2, the signal processing unit 13 is replaced with a sampling frequency conversion unit 31, the memory 14 is replaced with a storage unit 32, and the clock signal generation unit 22 is replaced with a clock signal generation unit 33 in FIG. there is Other than this, it is the same as FIG.

Here, the sampling frequency conversion unit 31 converts the sampling frequency (for example, 115.44 MHz) of the data output from the storage unit 12 to a different sampling frequency (for example, 111 MHz) and outputs it. . More specifically, the sampling frequency conversion unit 31 converts the sampling frequency by interpolation processing and thinning processing and outputs the result. More specifically, in order to convert the sampling frequency of the digital data, the sampling frequency converter 31 converts the digital data in the amplitude axis direction (digital data direction) to increase or decrease the bit width of the digital data. Parallel processing by vector operation may be used instead of increasing or decreasing the bit width. Also, it is of course possible to convert the sampling frequency by increasing or decreasing the data in the direction of the time axis.

The storage unit 32 has the same configuration as the storage unit 12 , writes data in synchronization with the write clock (WCLK) supplied from the clock signal generation unit 33 , and writes data in accordance with the read clock (RCLK) supplied from the modulation unit 15 . Synchronously, the data is read out and supplied to the modulating section 15 .

The clock signal generator 33 generates a read clock (RCLK) based on the signal supplied from the VCO 21 and supplies it to the clock signal generator 33 , generates a clock signal (CLK) and sends it to the sampling frequency converter 31 . A write clock signal (WCLK) is generated and supplied to the storage unit 32 .

In FIG. 2, the demodulation section 11, the modulation section 15, the data voltage conversion section 19, the LPF 20, the VCO 21, and the clock signal generation section 23 are configured as individual electronic components, and the rest are configured as logic circuits. . Note that the configuration described above is an example, and these may be implemented as an arbitrary combination of electronic circuits, logic circuits, or software.

(D) Description of Operation of Second Embodiment of the Present Invention Next, operation of the second embodiment of the present invention will be described. In addition, below, it demonstrates centering around a different part from 1st Embodiment. In the second embodiment, as in the first embodiment, the frequency of the VCO 21 is adjusted so that the number of data items stored in the storage unit 12 is the same as the reference value output from the reference value output unit 16. be. Thereby, the frequency of the VCO 21 is controlled to be constant.

In the second embodiment, data read out from the storage section 12 is supplied to the sampling frequency conversion section 31 . The sampling frequency conversion unit 31 converts the sampling frequency of the data output from the storage unit 12 and outputs the converted data. More specifically, the sampling frequency conversion unit 31 converts 115.44 MHz, which is the sampling frequency of the data read from the storage unit 12, into 111 MHz and outputs the result.

Here, in order to convert 115.44 MHz to 111 MHz, it is necessary to multiply by 26/25. As a method of converting the frequency, for example, there are methods of multiplying by 5, multiplying by 1/2, multiplying by 5, and multiplying by 1/13. In this case, 115.44 MHz becomes 1443 MHz when multiplied by 5, 1/2, and 5, exceeding 1 GHz. When the configuration shown in FIG. 2 is implemented by, for example, an FPGA (Field Programmable Gate Array), if the operating clock frequency of the FPGA is equal to the sampling frequency, the FPGA can handle signals with an operating clock frequency exceeding several GHz. Due to the difficulty, it is not feasible to perform such frequency conversion.

Therefore, in the second embodiment, instead of quintupling the frequency (increasing the number of data in the time axis direction), the amount of data in the amplitude direction is quintupled by interpolation processing. , to increase the sampling frequency. Further, the above-mentioned 1/2 times and 1/13 times can be reduced by reducing the clock signal or by thinning. Thereby, the conversion of the sampling frequency described above can be realized by, for example, an FPGA.

The data whose sampling frequency has been converted by the sampling frequency conversion section 31 is written to the storage section 32 in synchronization with the write clock signal. Since the write clock signal corresponds to the frequency after conversion of the sampling frequency, data is written in the storage section 32 in synchronization with the write clock signal.

The modulation unit 15 reads out data from the storage unit 32 in synchronization with a readout clock signal (RCLK) corresponding to the converted sampling frequency, modulates the data into an analog signal, and then transmits it as a broadcast signal. .

As described above, in the second embodiment of the present invention, even if the sampling frequencies of the input broadcast signal and the output broadcast signal are different, for example, a device such as an FPGA is used to perform conversion processing. be able to.

(E) Description of Configuration of Third Embodiment of the Present Invention Next, a third embodiment of the present invention will be described. FIG. 3 is a diagram showing a configuration example of a transmission device 10B according to the third embodiment of the present invention. In FIG. 3, parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. 3, the connection destination of the subtraction unit 17 is changed from the storage unit 12 to the storage unit 32 as compared with FIG. Also, clock signal generators 51 and 52 are added. The configuration other than these is the same as in FIG.

Here, the subtraction unit 17 subtracts the reference value supplied from the reference value output unit 16 from the value indicating the number of data stored in the storage unit 32 and outputs the result.

The clock signal generation unit 51 generates a read clock signal (RCLK) based on the clock signal (CLK) supplied from the demodulation unit 11 and supplies it to the storage unit 12 to generate and sample the clock signal (CLK). It is supplied to the frequency converter 31 .

The clock signal generator 52 generates a write clock signal (WCLK) based on the signal supplied from the VCO 21 and supplies the write clock signal (WCLK) to the memory 32 .

In FIG. 3, the demodulator 11, modulator 15, data voltage converter 19, LPF 20, VCO 21, and clock signal generators 23, 51 and 52 are configured as individual parts, and the rest are implemented as software. Configured. Of course, other configurations are possible.

(F) Description of the operation of the third embodiment of the present invention Next, the operation of the third embodiment of the present invention will be described. Note that the following description will focus on the portions whose operations are different from those in FIG.

The demodulation unit 11 supplies data (WDATA) obtained by demodulation to the storage unit 12 , generates a write clock signal (WCLK), and supplies the write clock signal (WCLK) to the storage unit 12 . As a result, data is written to the storage unit 12 in synchronization with the write clock signal.

The clock signal generator 51 supplies the read clock signal (RCLK) to the memory 12 based on the clock signal (CLK) supplied from the demodulator 11 . The storage unit 12 reads data in synchronization with the read clock signal and supplies the data to the sampling frequency conversion unit 31 .

The sampling frequency conversion unit 31 converts the sampling frequency of the data supplied from the storage unit 12 by the same processing as in the second embodiment and outputs the converted data.

The storage unit 32 writes the data output from the sampling frequency conversion unit 31 in synchronization with the write clock signal (WCLK) supplied from the clock signal generation unit 52 . Since the write clock signal supplied from the clock signal generator 52 is a clock signal output from the VCO 21 and has a substantially constant frequency, data is written into the storage unit 32 at a constant speed.

The modulation unit 15 reads data from the storage unit 32 based on the read clock signal (RCLK) generated by the clock signal generation unit 23 based on the signal supplied from the VCO 21 . Therefore, the modulation unit 15 reads out a certain amount of data per unit time from the storage unit 32, modulates it, generates an analog signal, and transmits it.

As described above, in the third embodiment of the present invention, the frequency of the signal generated by the VCO 21 is controlled so that the number of data stored in the storage section 32 is constant. The amount of data per unit time supplied to 15 can be made constant synchronously with the transmission source.

(G) Description of Configuration of Fourth Embodiment of the Present Invention Next, a fourth embodiment of the present invention will be described. FIG. 4 is a diagram showing a configuration example of a transmission device 10C according to the fourth embodiment of the present invention. In FIG. 4, parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. 4, the clock signal generator 23 is omitted and the clock signal generator 33 is replaced with the clock signal generator 61, as compared with FIG. The configuration other than these is the same as in FIG.

Here, the clock signal generator 61 generates a read clock signal (RCLK) based on the signal supplied from the VCO 21 and supplies it to the storage unit 12, generates a clock signal (CLK), and converts the sampling frequency. A write clock signal (WCLK) is generated and supplied to the storage unit 32 , and a clock signal (CLK) is generated and supplied to the modulation unit 15 .

In FIG. 4, the demodulation section 11, the modulation section 15, the data voltage conversion section 19, the LPF 20, the VCO 21, and the clock signal generation section 61 are configured as separate electronic circuits, and the rest are configured as logic circuits. . Of course, other configurations are possible. Note that the configuration described above is an example, and these may be implemented as an arbitrary combination of electronic circuits, logic circuits, or software.

(H) Description of Operation of Fourth Embodiment of the Present Invention Next, operation of the fourth embodiment of the present invention will be described. Note that the following description will focus on the portions whose operations are different from those in FIG. 4 is the same as FIG. 2 except that the clock signal generator 61 generates a clock signal (CLK) instead of the clock signal generator 23 and supplies it to the modulator 15 .

The read clock signal (RCLK), the clock signal (CLK), the write clock signal (WCLK), and the clock signal (CLK) output from the clock signal generator 61 are generated based on the signal supplied from the VCO 21. Therefore, each part can stably operate.

As described above, in the fourth embodiment of the present invention, even if the sampling frequencies of the input broadcast signal and the output broadcast signal are different, conversion processing is performed using a device such as an FPGA, for example. be able to.

(I) Description of Configuration of Fifth Embodiment of the Present Invention Next, a fifth embodiment of the present invention will be described. FIG. 5 is a diagram showing a configuration example of a transmission device 10D according to the fifth embodiment of the present invention. 5, parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. 5, the clock signal generator 23 is omitted and the clock signal generator 52 is replaced with the clock signal generator 71, as compared with FIG. Configurations other than these are the same as those in FIG.

Here, the clock signal generation unit 71 generates a write clock signal (WCLK) based on the signal supplied from the VCO 21 and supplies it to the storage unit 32, generates a clock signal (CLK) and sends it to the modulation unit 15. supply.

In FIG. 5, demodulator 11, modulator 15, data voltage converter 19, LPF 20, VCO 21, and clock signal generator 71 are configured as individual components, and the rest are configured as software. Of course, other configurations are possible.

(J) Description of the operation of the fifth embodiment of the present invention Next, the operation of the fifth embodiment of the present invention will be described. Note that the following description will focus on the portions whose operations are different from those in FIG. 5 is the same as FIG. 3 except that the clock signal generator 71 generates a clock signal (CLK) instead of the clock signal generator 23 and supplies it to the modulator 15 .

The clock signal generator 71 generates a write clock signal (WCLK) based on the signal supplied from the VCO 21 and supplies it to the memory 32 , and also generates a clock signal (CLK) and supplies it to the modulator 15 . Since the frequency of the signal output from the VCO 21 is substantially constant, data is read out from the storage unit 32 at a constant frequency, modulated by the modulation unit 15 and transmitted, so the data rate of the signal to be transmitted is becomes constant.

As described above, in the fifth embodiment of the present invention, the frequency of the signal generated by the VCO 21 is controlled so that the number of data stored in the storage unit 32 is constant. The amount of data per unit time supplied to 15 can be constant.

(K) Description of Modified Embodiments The above-described embodiments are examples, and needless to say, the present invention is not limited to the cases described above. For example, whether each component in each of the above embodiments is configured as an individual electronic circuit, configured as a logic circuit, or configured as software is an example, and is limited to the cases described above. not something. Further, it is arbitrary whether each component is configured as a digital component or a digital circuit, or configured as an analog component or an analog circuit.

Further, in each of the above embodiments, the storage units 12 and 32 are, for example, FIFO memories. However, as shown in FIG. ) can also be used. In the configuration example shown in FIG. 6, a part related to the storage unit 12 or the storage unit 32 in FIGS. 1 to 5 is extracted and shown. In the configuration example shown in FIG. 6, for example, when compared with the portion related to the storage unit 12 in FIG. there is In addition, SDR (Single Data Rate), DDR (Double Rate Ram), SDRAM (Synchronous Dynamic Random Access Memory), flash memory, etc. may be used in the same way.

The address counter 81 receives the write clock signal (WCLK) and the write enable signal (WEN) input to the storage unit 82 , generates a write address signal (WADD), and supplies the write address signal (WADD) to the storage unit 82 and the subtraction unit 84 . do.

The address counter 83 generates a read enable signal (REN) and a read address signal (RADD) based on the clock signal (CLK) supplied from the clock signal generator 22 and supplies them to the storage unit 82 and subtraction unit 84 . .

The storage unit 82 writes the write data (WDATA) to the address specified by the write address signal (WADD) supplied from the address counter 81 in synchronization with the write clock signal (WCLK). The storage unit 82 also reads read data (RDATA) from an address specified by a read address signal (RADD) supplied from the address counter 83 in synchronization with the read clock signal (RCLK).

The subtraction unit 84 subtracts the value of the read address signal (RADD) supplied from the address counter 83 from the value of the write address signal (WADD) supplied from the address counter 81 and outputs the result. A value obtained by subtracting the value of the write address signal (WADD) from the value of the read address signal (RADD) indicates the number of data stored in the storage unit 82 .

The processing after the subtraction unit 17 is the same as in FIGS. 1 to 6. FIG. Thereby, the signal output from the VCO 21 is controlled so that the number of data stored in the storage unit 82 is constant.

As described above, even when the storage unit 82 shown in FIG. 6 is used, the same effects as those of the storage units 12 and 32 shown in FIGS. 1 to 5 can be obtained.

10, 10A to 10D transmission device 11 demodulator 12 storage unit 13 signal processing unit 14 storage unit 15 modulation unit 16 reference value output unit 17 subtraction unit 18 loop filter 19 data voltage conversion unit 20 LPF
22, 23 clock signal generation unit 31 sampling frequency conversion unit 32 storage unit 33, 51, 52, 53, 61, 71 clock signal generation unit 81, 83 address counter 82 storage unit 84 subtraction unit

Claims (4)

receiving means for receiving the modulated signal;
demodulation means for demodulating the signal received by the receiving means to generate digital data;
storage means for storing the digital data obtained by demodulation by the demodulation means;
reading means for reading the digital data from the storage means;
a modulating means for modulating the digital data read by the reading means;
transmitting means for transmitting a signal modulated by the modulating means;
supply means for generating a clock signal and supplying it to the readout means and the modulation means;
adjustment means for adjusting the frequency of the clock signal generated by the supply means according to the number of the digital data stored in the storage means;
conversion means provided before or after the storage means for converting the sampling frequency of the digital data by performing interpolation processing on the digital data;
has
In the interpolation processing, the conversion means converts the sampling frequency into a non-integer relationship with a signal processing device, increases the digital data in a direction different from the time axis, and multiplies the data amount by a non-integer. By increasing or decreasing the sampling frequency, and when increasing or decreasing the non-integer multiple, the clock signal that operates the signal processing device is kept constant to increase or decrease the sampling frequency. that let
A transmission device characterized by: The adjustment means calculates a difference value between the number of the digital data stored in the storage means and a predetermined reference value, and when the difference value is positive, the clock signal is generated according to the value. 2. The transmission apparatus according to claim 1, wherein the frequency of the clock signal is decreased in accordance with the difference value when the difference value is negative. The adjustment means obtains the number of the digital data from the difference value between the write address and the read address of the storage means, calculates the difference value between the obtained number of the digital data and a predetermined reference value, and calculates the difference value. is positive, the frequency of the clock signal is increased according to the value, and if the difference value is negative, the frequency of the clock signal is decreased according to the value. Item 1. The transmission device according to item 1. a receiving step of receiving the modulated signal;
a demodulating step of demodulating the signal received in the receiving step to generate digital data;
a storage step of storing the digital data obtained by demodulation in the demodulation step in a storage unit;
a reading step of reading the digital data from the storage unit;
a modulating step of modulating the digital data read in the reading step;
a transmitting step of transmitting the signal modulated in the modulating step;
a supplying step of generating and supplying a clock signal to the reading step and the modulating step;
an adjustment step of adjusting the frequency of the clock signal generated by the supply step according to the number of the digital data stored in the storage unit;
a conversion step of converting a sampling frequency of the digital data by performing an interpolation process on the digital data before or after the storage unit;
has
In the conversion step, in the interpolation processing, the signal processing device converts the sampling frequency into a non-integer relationship, increases the digital data in a direction different from the time axis, and multiplies the data amount by a non-integer. By increasing or decreasing the sampling frequency, and when increasing or decreasing the non-integer multiple, the clock signal that operates the signal processing device is kept constant to increase or decrease the sampling frequency. that let
A method of controlling a transmission device, characterized by: