JP3395600B2 - Data transfer device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device used in a microprocessor or the like and having a serial data transfer function.

[0002]

2. Description of the Related Art FIG. 4 shows a block diagram of a conventional data transfer device. FIG. 5 shows the timing chart.

In FIG. 4, the data transfer device 4 includes a data output register 50, a data register 41, a stop bit receiving register 42, and a stop bit receiving register 4.
3, frame mode selection circuit 44, and information storage register 4
5 and the frame mode selection register 46,
It is connected to the data bus 47. Here, the frame mode selection register 46 is a control register that selects either 1 bit or 2 bits as the number of stop bits in one frame.

The data register 41 has a clock signal 40.
Data is stored on the data input line 48 by the rising edge of 1. The data output register 50 receives the falling edge of the clock signal 401 and receives the data output line 4
The data is output to 9. As a result, data is received at the clock edge opposite to that at the time of transmission. The stop bit reception register 42 stores data from the data input line 48 according to the clock signal 402. Similarly, the stop bit reception register 43 receives the clock signal 40
When 3 is received, the data is stored from the data input line 48.
The frame mode selection register 46 stores data from the data bus 47 according to the write control signal 406 (symbol WE in the drawing) and outputs the frame mode selection signal 405. Upon receiving the frame mode selection signal 405, the frame mode selection circuit 44 receives the stop bit reception register 42.
And the data of 43 are output, and in other cases, the data of the stop bit reception register 42 is output. The information storage register 45 stores the output of the frame mode selection circuit 44 according to the clock signal 404 and outputs the data to the data bus 47.

Here, the clock signals 401, 402, 4
03 and 404 and the write control signal 406 are output by a microprocessor (not shown), and the data bus 47 is connected to the same microprocessor.

With respect to the conventional data transfer apparatus configured as described above, the operation when performing UART communication will be described separately for transmission and reception.

First, the case of transmission will be described. Data to be transmitted is set in advance in the data register 41, and the set data is output to the data output line bit by bit by the clock signal 401. After the data transmission is completed, the stop bits are continuously output to the data output line by the set number (see FIG. 5).

Next, the case of reception will be described. First, the frame mode selection register 46 selects either one stop bit or two stop bits. The data register 41 stores data while shifting the data from the data input line by 1 bit by the clock signal 401.
After the data reception is completed, the stop bit reception register 42
Data is stored from the data input line by the clock signal 402 at the timing (G) shown in FIG. Similarly, the stop bit reception register 43 stores the data from the data input line by the clock signal 403 at the timing (H) shown in FIG. The frame mode selection circuit 44 includes stop bit reception registers 42 and 4
The logical sum of the data of 3 or the data of the stop bit reception register 42 is output. The information storage register 45 stores the output of the frame mode selection circuit 44 at the timing of (I) in FIG. 5 according to the clock signal 404 output from the microprocessor at the end of communication.

Here, the operation when the conventional data transfer device cannot receive normally will be described. <At communication error> in FIG. 5 is a timing chart when the data frame has 2 stop bits and the first stop bit is “L”. After receiving the data, the stop bit reception register 42 stores the "L" stop bit at the timing (G). Next, the stop bit reception register 43 stores the second stop bit at the timing of (H). The frame mode selection circuit 44 outputs a logical product of the stop bit reception registers 42 and 43. As a result, the information storage register 45 stores the "L" data at the timing of (I) in FIG. Since the information storage register 45 retains the error information even after the communication is completed, the microprocessor can determine whether the communication is completed normally by reading the data in the information storage register 45 after the communication is completed. .

[0010]

However, the above-mentioned conventional UART communication can be used only for UART communication, and cannot be used for IC card communication.

That is, the UART communication is generally treated as a communication means having a data format as shown in the conventional example. On the other hand, IC card communication does not use a clock for frame synchronization with a communication partner, and thus can be classified into the category of UART communication.

However, the IC card communication is treated as a communication means different from the original UART communication because of the difference in the data format.

The format of data to be communicated with the IC card communication protocol will be described below.

In the IC card communication, a protocol ATR (hereinafter referred to as ATR) for informing the reader / writer of the communication start from the IC card at the time of starting the communication, and a protocol T = n (for communicating with the reader / writer after the ATR). Currently, n is 0 to 16). T = n is performed in the UART data format, but the ATR is different from the UART. However, ATR
Is transmitted only from the IC card.

FIG. 6 shows a schematic diagram of an ATR format standardized by ISO for IC card communication.

In the UART, the stop bit is transmitted after the data is transmitted (see FIG. 5), but in the ATR format, the stop bit is not transmitted after the data is transmitted, as shown in (J) and (K) of FIG. Then, the resend request data from the reader / writer is received. The reader / writer returns "H" if the data from the IC card can be received normally.
If it is abnormal, "L" is transmitted to the IC card. The data width (1 bit or 2 bits) of the retransmission request data and the reception timing of the retransmission request data are defined by the standard. As described above, it is necessary to realize the ATR format in order to perform IC card communication. However, in the conventional data transfer device shown in FIG. 4, when the first stop bit is "L", "L" data is also stored in the information storage register and it is determined that the communication is abnormal ( (See Fig. 5 Communication error).
However, in the ATR, according to the standard, communication such as when communication is abnormal in FIG. 5 is normal communication. That is, UA in ATR
Do not judge the first stop bit at RT. Thus, in the conventional data transfer device, the ATR
IC card communication cannot be performed because communication cannot be realized.
Further, in order to support all ATR data formats, it is necessary to be able to change the reception timing of the retransmission request data.

It is an object of the present invention to provide a data transfer device capable of coping with a plurality of data communications as described above by providing a small number of circuits and control registers.

[0018]

In order to solve this problem, a data transfer apparatus of the present invention comprises a serial data output means for outputting serial data to a data terminal at a first change timing of a data transfer clock, and a first data output means. Stop bit receiving means for storing and outputting given data at the second change timing of the data transfer clock when the stop bit is in the receiving state, and data transfer when the second stop bit is in the receiving state Logic using second stop bit receiving means for storing and outputting the given data at the second change timing of the clock, the first stop bit receiving means and the second stop bit receiving means Frame mode selection means for performing calculation and outputting the result, output of the frame mode selection means and reception of the second stop bit First selecting means for selecting and outputting the output of the stage, first controlling means for controlling the first selecting means, and information for storing and outputting the output of the first selecting means at the end of data transfer A storage means, and in the extended data communication state, causes the first selection means to selectively output the output of the second stop bit reception means.

In order to solve this problem, the data transfer apparatus of the present invention further comprises first data storage means for storing and outputting the value of the data terminal at a first change timing of the data transfer clock, A second selection unit that selects and outputs either the value of the data terminal or the output of the first data storage unit; and a second control unit that controls the second selection unit, The value obtained from the data terminal is the output of the second selecting means.

Alternatively, in order to solve this problem, the data transfer device of the present invention further comprises second data storage means for storing and outputting the value of the data terminal with a clock obtained by delaying the data transfer clock. , A third selecting means for selecting and outputting either the value of the data terminal or the output of the second data storing means, and a third controlling means for controlling the third selecting means. , The value obtained from the data terminal is the output of the third selecting means.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. 1, 2 and 3.

FIG. 1 is a block diagram showing the configuration of a data transfer device according to the first embodiment of the present invention. FIG. 2 shows a timing chart during normal communication, and FIG. 3 shows a timing chart during abnormal communication.

In FIG. 1, the data transfer device 1 communicates with a data register 11, a stop bit reception register 12, a stop bit reception register 13, a frame mode selection circuit 14, an information storage register 15, a selector 16, a frame mode selection register 17. Mode switching register 1
8, a reception edge switching register 19, a data input register 20, a selector 21, and a data output register 25, and they are connected to a data bus 22. Here, the frame mode selection register 17 is a control register that selects either 1 bit or 2 bits as the number of stop bits in one frame.
Reference numeral 8 is a control register for selecting either UART or IC card communication as the communication format. Also,
The reception edge switching register 19 is a control register that switches the reception timing of input data.

The data register 11 stores the output of the selector 21 at the rising timing of the clock signal 101 which is the data transfer clock. Data output register 2
5 stores the data of the data register 11 in response to the falling edge of the clock signal 101, and the data output line 4
The data is output to 9. The data is output to the data output line 24. As a result, unlike during transmission, during reception, data is received at the opposite edge of the clock. The data input register 20 stores data from the data input line 23 at the falling timing of the clock signal 101. When the selector 21 receives the reception edge switching signal 108, it outputs the data of the data input register 20, and otherwise outputs the data of the data input line 23.
The stop bit reception register 12 stores the output of the selector 21 at the rising timing of the clock signal 102 output when the first stop bit is in the reception state. Similarly, the stop bit reception register 13 stores the output of the selector 21 at the rising timing of the clock signal 103 output when the second stop bit is in the reception state. Here, the rising timing of the clock signal 102 and the clock signal 103 is the clock signal 1
It coincides with the rising timing of 01. Frame mode selection register 17 and communication mode switching register 18
And the receiving edge switching register 19 write the control signal 1
06 (symbol WE in the figure) stores data from the data bus 22, and a frame mode selection signal 105, a communication mode switching signal 107, and a reception edge switching signal 108, respectively.
Is output. When the frame mode selection circuit 14 receives the frame mode selection signal 105, it outputs a logical product of the data in the stop bit reception registers 12 and 13, and otherwise outputs the data in the stop bit reception register 12. When the selector 16 receives the communication mode switching signal 107, it outputs the data of the stop bit reception register 13, and otherwise outputs the data of the frame mode selection circuit 14. The information storage register 15 stores the output of the selector 16 in response to the clock signal 104 output when the error information is received, and outputs the data to the data bus 22.

Here, the clock signals 101, 102, 1
03 and 104 and the write control signal 106 are output by a microprocessor (not shown), and the data bus 22 is connected to the same microprocessor. Further, the data input line 23 and the data output line 24 are respectively connected to data terminals (not shown), and the data transfer device 1
Are connected to a reader / writer (not shown) by the data terminal.

With respect to the data transfer apparatus of the present invention configured as described above, the operation when performing IC card communication will be described separately for normal communication and abnormal communication. (For normal communication) First, IC card communication is selected by the communication mode switching register. This allows selector 1
6 outputs the data of the stop bit reception register 13. Further, the receiving edge switching register 19 allows the data input line 23 or the data input register 20.
Which data is to be output from the selector 21 is selected. The data input register 20 has a clock signal 101.
Data is stored from the data input line 23 by. ATR data to be transmitted is set in advance in the data register 11, and the data set by the clock signal 101 is output to the data output line 24 bit by bit.
Stop bit reception register 1 after completion of ATR data transmission
3 stores the data from the selector 21 by the clock signal 103 at the timing (A) shown in FIG. The selector 16 outputs the data of the stop bit reception register 13, and the information storage register 15 outputs the clock signal 104 output from the microprocessor at the end of communication.
The output of the selector 16 is stored at the timing shown in FIG. In the case of normal communication, since the reader / writer does not issue a resend request, the output of the selector 21 at the timing of FIG. 2A is "H", so the data of the information storage register 15 after the communication is "H". Becomes (In the case of abnormal communication) When the reader / writer cannot normally receive the ATR data transmitted by this data transfer device, it corresponds to a 1-bit or 2-bit data width from the reader / writer at the timing of (C) of FIG. Then, resend request data indicating a communication error is transmitted. Regarding the operation in this case, the retransmission request data width is (1) 1
Bit (2) The case of 2 bits will be described separately. (1) Retransmission request data = 1 bit First, the reception edge switching register 19 is set so that the data in the data input register 20 is output from the selector 21. As a result, it becomes possible to receive data at the same timing as transmission. The operation during the ATR data transmission period in FIG. 3 is the same as that in the case of the above normal communication. In the retransmission request data reception period after the completion of the ATR data transmission, the data input register 20 receives the retransmission request data “L” from the data input line 23 by the clock signal 101 at the timing of the middle of the retransmission request data reception period (FIG. 3E). Is stored. Therefore, the stop bit reception register 13 stores "L" data from the selector 21 by the clock signal 103 at the timing of (D) in FIG. Subsequently, the information storage register 15 stores the output "L" of the selector 16 at the timing of (F) in FIG. (2) Retransmission request data = 2 bits First, the reception edge switching register 19 is set so that the data of the data input line 23 is output from the selector 21. As a result, the stop bit reception register 13
Can receive data at the edge timing opposite to the edge of the transmission clock. The operation during the ATR data transmission period is the same as in the above normal communication and (1). During the retransmission request data reception period after the completion of ATR data transmission, the stop bit reception register 13
The retransmission request data “L” is stored from the data input line 23 by the clock signal 103 at the timing of the middle of the retransmission request data reception period (FIG. 3D). Therefore, the information storage register 15 stores the “L” data through the selector 16 at the timing of FIG.

When an abnormal communication error occurs, the timing of receiving data from the data input line 23 of the stop bit receiving register 13 is changed as described in (1) and (2) above, and the stop bit receiving register 12 is changed. By making it possible to ignore the data of 1, the retransmission request data can be stored in the information storage register 15 as communication error information at an appropriate timing.

Since the information storage register 15 retains the error information even after the communication is completed, the microprocessor determines whether or not the communication is normally completed by reading the data in the information storage register 15 after the communication is completed. be able to.

As described above, according to the embodiment of the present invention, by providing a small number of circuits and control registers and switching the circuits by setting the control registers, the UART and the AT can be controlled.
Both R data formats can be handled, and UAR
IC card communication, which is a data format different from T communication, is possible. Further, in the past, transmission and reception of the ATR format was realized by the microcomputer executing software, and it was necessary to use a very high-performance microcomputer for high-speed communication.
According to the embodiments of the present invention, high-speed communication can be easily realized.

In the above embodiment of the present invention, the data input register 20 stores the value of the data input line 23 at the falling timing of the clock signal 101, but it is obtained by delaying the clock 101. The value of the input line 23 may be stored using the clock.

[0031]

As described above, the data transfer apparatus according to the present invention has the serial data output means for outputting serial data to the data terminal at the first change timing of the data transfer clock, and the receiving state of the first stop bit. First stop bit receiving means for storing and outputting given data at the second change timing of the data transfer clock at
Second stop bit receiving means for storing and outputting the given data at the second change timing of the data transfer clock when receiving the second stop bit, and the first stop bit receiving means Frame mode selecting means for performing a logical operation using the second stop bit receiving means and outputting the result, and selecting and outputting the output of the frame mode selecting means and the output of the second stop bit receiving means. And a first control means for controlling the first selection means, and an information storage means for storing and outputting the output of the first selection means at the end of data transfer. In the data communication state, the first selection means selectively outputs the output of the second stop bit reception means.

According to this structure, in addition to the conventional UART communication, by causing the first selecting means to selectively output the output of the second stop bit receiving means, the UA
IC card communication, which is a data format different from RT communication, is possible. Moreover, since communication is performed by hardware, high-speed communication can be easily realized.

Further, as described above, the data transfer device according to the present invention further includes the first data for storing and outputting the value of the data terminal at the first change timing of the data transfer clock. Storage means, second selection means for selecting and outputting either the value of the data terminal or the output of the first data storage means, and second control means for controlling the second selection means. And the value obtained from the data terminal is the output of the second selecting means.

According to this configuration, the second selecting means selects one of the value of the data terminal and the output of the data storing means, so that communication in a plurality of ATR formats can be realized.

Alternatively, as described above, in the data transfer device according to the present invention, the second data transfer device further stores and outputs the value of the data terminal with a clock obtained by delaying the data transfer clock. Data storage means, third selection means for selecting and outputting any one of the value of the data terminal and the output of the second data storage means, and third control for controlling the third selection means. Means and the value obtained from the data terminal is the output of the third selecting means.

According to this structure, the same effect can be obtained with a structure different from that of the data transfer device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the data transfer device according to the embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the data transfer device according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional data transfer device.

FIG. 5 is a timing chart showing the operation of a conventional data transfer device.

FIG. 6 is a schematic diagram of the ATR format.

[Explanation of symbols]

11 Data register 12, 13 Stop bit reception register 14 Frame mode selection circuit 15 Information storage register 16, 21 selector 17 Frame mode selection register 18 Communication mode switching register 19 Reception edge switching register 20 data input register 22 Data bus 23 Data input line 24 data output line 101, 102, 103, 104 clock signals 105 frame mode selection signal 106 write control signal 107 Communication mode switching signal

Claims (4)

(57) [Claims] 1. A serial data output means for outputting serial data to a data terminal at a first change timing of a data transfer clock, and a second change timing of the data transfer clock when the first stop bit is in a receiving state. Stores and outputs a value obtained from the data terminal at
Stop bit receiving means, and second stop bit receiving means for storing and outputting a value obtained from the data terminal at the second change timing of the data transfer clock when the second stop bit is being received. Frame mode selecting means for performing a logical operation using the first stop bit receiving means and the second stop bit receiving means and outputting the result, an output of the frame mode selecting means and the second stop bit First selecting means for selecting and outputting the output of the receiving means, first controlling means for controlling the first selecting means, and storing and outputting the output of the first selecting means at the end of data transfer. An information storage unit, and in the extended data communication state, causing the first selection unit to selectively output the output of the second stop bit reception unit. Data transfer apparatus according to symptoms. 2. The data transfer device further comprises first data storage means for storing and outputting a value of the data terminal at a first change timing of the data transfer clock, a value of the data terminal and the first data storage means. The second storage means for selecting and outputting any one of the outputs of the data storage means, and the second control means for controlling the second selection means. The data transfer apparatus according to claim 1, wherein the data is output from the second selecting means. 3. The data transfer device further comprises second data storage means for storing and outputting the value of the data terminal with a clock obtained by delaying the data transfer clock, the value of the data terminal and the second data storage means. The data obtained from the data terminal includes a third selection means for selecting and outputting any one of the outputs of the second data storage means and a third control means for controlling the third selection means. The data transfer device according to claim 1, wherein the data is output from the third selecting means. 4. The change of the data transfer clock at the second change timing has a polarity different from that of the change of the data transfer clock at the first change timing. The data transfer device according to claim 3.