JPS6243591B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a teletext receiver that receives information data superimposed on a television signal.

Information data converted into a digital signal is superimposed on a portion of the vertical retrace period of the television signal and transmitted, and the user can display a screen composed of this information data on the cathode ray tube of the receiver as necessary. Recently, teletext services that can be used as a next-generation information service have been attracting attention.

In the receiver of such teletext service,
Generally, a microcomputer is used to process information data such as decoding it and displaying it on a cathode ray tube, but the information data superimposed on a television signal is sent at a high bit rate of several megabits/second. Therefore, it is difficult to directly process this information data in real time on a microcomputer, and conventional teletext receivers are equipped with a buffer memory in which the information data sent is recorded once and then processed. A microcomputer read the contents of this buffer memory, decoded it, and processed it. FIG. 1 shows a block diagram of the conventional teletext receiver described above. In Figure 1, 1 is Chuyuna;
IF circuit, 2 is a detection circuit, 3 is a synchronous separation circuit, 4
is a gate generation circuit, 5 is a clock generation circuit, 6 is a serial-to-parallel conversion circuit, 7 is an address counter circuit, 8
The address switching circuit 9 is a buffer memory, 10 is a central processing unit (hereinafter abbreviated as CPU), 11 is a non-volatile read-only memory (hereinafter abbreviated as ROM),
12 is a display memory, 13 is an address bus, and 14 is a data bus. In the following description, it is assumed that the information data is inserted in the 20th line as shown in FIG. 2A. (However, Fig. 2A shows the case of an odd field, and in the case of an even field, it is inserted in the 283rd line.) The sync separation circuit 3 separates only the sync pulse from the composite video signal, and the gate generation circuit 4 Using the synchronization pulse as a reference, horizontal synchronization pulses are counted to generate a gate signal as shown in FIG. 2B that gates only the 20th line or 283rd line period. (However, the polarity is not limited to B in Figure 2.) The clock generation circuit 5 generates a lock signal synchronized with each bit of information data, and this clock signal causes the serial/parallel conversion circuit 6 to convert the information data into parallel data. do. Further, the address counter circuit 7 counts this clock signal and generates an address signal specifying the address of the buffer memory 9 into which parallel data is to be written. The address switching circuit 8 controls the 20th line and the 20th line by the gate signal.
Only during the period of 283 lines, the buffer memory 9 and the address counter circuit 7 are connected so that the address of the buffer memory 9 is specified by the address signal from the address counter circuit 7, and the buffer memory 9 is placed in a writing state. After writing information data to the buffer memory 9, one field period until the next information data is sent.
The CPU 10 reads the contents of the buffer memory 9 according to the processing procedure recorded in the ROM 11, and when the information data matches the program requested by the receiver during reading, the pattern data in the contents of the buffer memory 9 is displayed. The data is transferred to the memory 12 and reproduced on a cathode ray tube using a well-known method.

As mentioned above, conventional receivers use the buffer memory 9 to temporarily store information data, but memory is generally expensive, so conventional teletext receivers have the disadvantage of high costs. Furthermore, since memory generally consumes a large amount of power, conventional teletext receivers also have the disadvantage of increased power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide a low-cost teletext receiver that eliminates the drawbacks of the conventional teletext receiver described above and does not require the use of a buffer memory.

In order to achieve the above object, the present invention focuses on the fact that there is a margin storage area that is not used for display out of the total storage area of the display memory, and the central processing unit , and the information data is written directly into a storage area in the margin of the display memory.

The present invention will be explained in detail below using FIG.

FIG. 3 is a block diagram showing one embodiment of the present invention. In FIG. 3, 15 and 16 are both buffer circuits, 17 is a timing circuit, and other symbols are the same as in FIG. 1. Before explaining the operation of the present invention, an overview of the display memory will be given. Each bit of the display memory corresponds to a picture element on the screen. The display data for one screen is approximately 200 lines in the vertical (vertical scanning) direction.
Since the image is divided into approximately 250 picture elements in the horizontal (horizontal scanning) direction, the display memory requires a capacity of approximately 50K bits, or approximately 6.3K bytes expressed in bytes. However, the memory capacities generally available on the market are configured in units of 1K, 2K, 4K, and 8K bytes, so 8K bytes of memory are used as display memory, or
Alternatively, a combination of memories with a total capacity of 7K bytes is used. Therefore, when 8K bytes of memory is used as display memory, the actual capacity used for display is approximately 6.3K bytes, so approximately 1.7K bytes is leftover storage space that is not used for display. becomes. Furthermore, when a 7K byte combination of memories is used as a display memory, about 0.7K bytes will similarly be a margin storage area. However, the information data sent once per field is approximately 300 bits, or 30 bits.
It is about 40 bytes, which is enough to be stored in the blank storage area of the display memory. Therefore, the present invention uses the storage area in the margin of the display memory in place of the conventional buffer memory, but as mentioned above, information data is sent at a very high speed, so the CPU is unable to process the data. It is absolutely impossible to receive this and write it to the storage area in the margin of the display memory. Therefore, the present invention provides a period of a line on which information data is superimposed,
The purpose is to stop the CPU and write information data directly to the storage area in the margins of the display memory without going through the CPU. In FIG. 3, the timing circuit 17 synchronizes the gate signal obtained from the gate generation circuit 4 with the clock signal of the CPU 10 (different from the clock signal for acquiring information data described above), and stops the CPU 10. At the same time, the information data converted from serial to parallel by the serial/parallel conversion circuit 6 is supplied to the terminal of the CPU 10 (usually referred to as the halt terminal or hold terminal) for
The display memory 1 to which the information data is written is supplied to the data bus 14 and synchronized with the information data.
The buffer circuit 15 outputs the output of the address counter circuit 7 which outputs the address of the storage area portion of the blank space of 2.
The address bus 13 is supplied via the address bus 13. Here, it is assumed that the buffer circuits 15 and 16 are rendered conductive only during the periods of the 20th line and the 283rd line by the gate signal. Although not shown in FIG. 3, gate signals are also supplied to the write control terminal and chip select terminal of the display memory 12, so that the display memory 12 is selected in the write state during the periods of the 20th line and the 283rd line. shall be

By adopting this configuration, the period of the 20th line and the 283rd line on which information data is superimposed is
The CPU 10 is in a stopped state and the display memory 12 is selected in a write state, data and addresses are outputted by the buffer circuits 15 and 16 which are in a conductive state only during this period, and information data is written directly into the display memory 12. And the CPU
The 21st line or the 10th line where the stoppage of 10 is lifted.
After the 284th line, CPU10 in 1 field period
According to the processing procedure of ROM 11, display memory 12
The information data is read out, decoded, and displayed.

In the above explanation, it is assumed that the screen information data is sent after being decomposed into picture elements, but the present invention can also be applied to the case where the screen information data is sent after being coded. It is clear that this is possible.

As described above, the present invention uses the blank storage area of the display memory 12 without using the conventional buffer memory 9, so that it is possible to reduce the cost and power consumption of the teletext receiver.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional teletext receiver, FIG. 2 is a signal waveform diagram, and FIG. 3 is a block diagram showing an embodiment of the teletext receiver according to the present invention. 4... Gate generation circuit, 6... Serial/parallel conversion circuit, 7... Address counter circuit, 9... Buffer memory, 10... CPU, 12... Display memory, 15, 16... Buffer circuit.

Claims (1)

[Scope of Claims] 1. In a teletext receiver that is equipped with a display memory and a central processing unit and receives information data superimposed on a vertical blanking period of a television signal, the display memory is a first channel used for display. and a second area not used for display, means for stopping the central processing unit and putting the display memory in a writing state during the horizontal period in which information data is superimposed; and during the horizontal period, Address generation means for generating an address corresponding to the second area in synchronization with information data; and first switching means for connecting the address generation means to the address bus during the horizontal period and disconnecting it during other periods. and a serial-to-parallel conversion means for serial-to-parallel conversion of information data during the horizontal period; and a second switching means for connecting the serial-to-parallel conversion means to the data bus during the horizontal period and disconnecting it during other periods. A teletext receiver, characterized in that the central processing unit generates display data from the information data stored in the second area of the display memory and writes it in the first area.