JPS6242554A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6242554A
JPS6242554A JP60182288A JP18228885A JPS6242554A JP S6242554 A JPS6242554 A JP S6242554A JP 60182288 A JP60182288 A JP 60182288A JP 18228885 A JP18228885 A JP 18228885A JP S6242554 A JPS6242554 A JP S6242554A
Authority
JP
Japan
Prior art keywords
film
substrate
transistor
section
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60182288A
Other languages
Japanese (ja)
Inventor
Yasushi Ema
泰示 江間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60182288A priority Critical patent/JPS6242554A/en
Publication of JPS6242554A publication Critical patent/JPS6242554A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto

Abstract

PURPOSE:To form a capacitance section having sufficient capacitance and a transistor Tr having stable characteristics by directly applying a nitride film on a substrate in the capacitance section and shaping an SiO2 film on the substrate in a transistor forming section. CONSTITUTION:A field oxide film 12 and an SiO2 film 20 are shaped to a p-type Si substrate 11. A resist pattern 21 coating a transistor forming section is formed, and an n<+> type layer is shaped through ion implantation. When the film 20 is removed and the surface of the film 12 is removed partially, the surface of the substrate is exposed in a capacitance section, and the surface of the film 12 changed into an n<+> type is gotten rid of, thus generating no inversion. The film 20 is left under the pattern 21, a Tr forming section. When the pattern 21 is removed and a nitride film 22 is grown on the whole surface, the film 22 is formed to a section just above the substrate 11 in a capacitance forming section, the film 20 on the substrate 11 in the Tr forming section and the film 22 on the film 20, thus shaping the capacitance section having excellent characteristics and a transistor.

Description

【発明の詳細な説明】 〔概要〕 ダイナミック・ランダム・アクセス・メモリ(d RA
M )において、トランジスタ形成部に選択的に酸化膜
を形成した後、シリコン窒化膜(以下単に窒化膜という
)を被着することにより容量形成膜を作る。
[Detailed Description of the Invention] [Overview] Dynamic random access memory (dRA
In step M), after selectively forming an oxide film in the transistor forming area, a capacitor forming film is formed by depositing a silicon nitride film (hereinafter simply referred to as a nitride film).

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に関するもので、さらに
詳しく言えば、絶縁耐圧に優れたd RAMを形成する
方法に関する。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a dRAM with excellent dielectric strength.

〔従来の技術〕[Conventional technology]

第2図(a)の平面図と同図のB−B線に沿う断面図で
ある同図(blに示されるd RAMは知られたデバイ
スで、図において、11はp型半導体(シリコン)基板
、12は二酸化シリコン(5iOz )のフィールド酸
化膜、13はn+型領領域14は第1層の多結晶シリコ
ン(ポリシリコン)膜、15は第2層ポリシリコン膜、
16は絶縁膜、17はアルミニウム(1)配線を示し、
AJ配線17はビットライン(データライン)・第2N
のポリシリコン膜はワードライン(アドレスライン)で
、図示のデバイスで1つのメモリセルを構成する。同図
(C)は同図(b)のd RAM等価回路図で、図示の
容量Cは基板と第1層ポリシリコン層によって構成され
る容量部18によって作られる。なお、同図において、
19はトランジスタ形成部である。
FIG. 2(a) is a plan view and a cross-sectional view taken along line B-B in the same figure (d shown in bl) RAM is a known device, and in the figure, 11 is a p-type semiconductor (silicon). A substrate, 12 a field oxide film of silicon dioxide (5 iOz), 13 an n+ type region 14 a first layer polycrystalline silicon (polysilicon) film, 15 a second layer polysilicon film,
16 is an insulating film, 17 is an aluminum (1) wiring,
AJ wiring 17 is a bit line (data line)/2nd N
The polysilicon film is a word line (address line) and constitutes one memory cell in the illustrated device. FIG. 5C is an equivalent circuit diagram of the d RAM shown in FIG. In addition, in the same figure,
19 is a transistor forming section.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前記した容量部においては絶縁耐性が必要である。絶縁
膜は一般に次の3つによって作られるが、その絶縁耐性
は右欄に示す通りである。
The capacitor section described above requires insulation resistance. Insulating films are generally made using the following three methods, and their insulation resistance is shown in the right column.

種類          絶縁性 窒化膜/ 5i02         良5i02  
           不良5i02/窒化膜/ Si
O2良 上記の3番目の構造は、5i02の上に化学気相成長法
(CVD法)で窒化膜を被着し、窒化膜の表面を熱酸化
により 5iOzとして作るのであるが、g膜化の要求
により、5i02膜と窒化膜は成按を制御することによ
りそれぞれ50人の膜厚に、また窒化膜の上のSiO2
膜は10人の膜厚にする。 5i02の誘電率(ε)は
3.9あり、窒化膜のεは7であるので、上記の3層構
造を5i02に換算すると、75人の膜厚に相当する。
Type Insulating nitride film/5i02 Good 5i02
Defective 5i02/Nitride film/Si
In the third structure described above, a nitride film is deposited on 5i02 by chemical vapor deposition (CVD), and the surface of the nitride film is made into 5iOz by thermal oxidation. According to the requirements, the 5i02 film and the nitride film are each made to a thickness of 50 nm by controlling the growth, and the SiO2 film on the nitride film is
The thickness of the membrane shall be 10 people. The dielectric constant (ε) of 5i02 is 3.9, and the ε of the nitride film is 7, so converting the above three-layer structure to 5i02 corresponds to a film thickness of 75 people.

しかし、絶縁膜はより薄い方が有利であるので、上記の
5i02/窒化膜/5i02の3層構造よりも窒化膜/
 5i02の方がより有利である。
However, since it is advantageous for the insulating film to be thinner, the nitride film/
5i02 is more advantageous.

ところが、トランジスタ形成部においては、基板にすぐ
窒化膜を付ける代りにSiO2を付けることが必要であ
る。その理由は、窒化膜の上にSiO2を付けたのでは
、膜が電子、正孔(ホール)をトラップし、しきい値電
圧(V7/プ)がシフトし、また界面準位によってトラ
ンジスタの特性が不安定になり、トランジスタの絶縁膜
は5iOzである必要があり、かつ、シリコン基板の上
に窒化膜を被着し、窒化膜を熱酸化してその後、除去し
てから新たに5i02膜を形成すると゛耐圧性が悪く、
シリコン基板上に順に5i02、窒化膜を成長し、次い
で窒化膜、 5i02の順にエツチングし、次いで熱酸
化を行うと、トランジスタ形成部には絶縁耐圧の良好な
5i02膜が得られることになる。
However, in the transistor formation area, it is necessary to apply SiO2 instead of immediately applying a nitride film to the substrate. The reason for this is that when SiO2 is placed on top of the nitride film, the film traps electrons and holes, the threshold voltage (V7/p) shifts, and the transistor characteristics change due to the interface state. becomes unstable, and the insulating film of the transistor must be 5iOz, and a nitride film is deposited on the silicon substrate, the nitride film is thermally oxidized, and then removed before a new 5i02 film is applied. If formed, the pressure resistance is poor,
By growing a 5i02 film and a nitride film on a silicon substrate, etching the nitride film and 5i02 in this order, and then performing thermal oxidation, a 5i02 film with good dielectric strength can be obtained in the transistor formation area.

次に、d RAMの容量部の等価回路図は第3図に示さ
れ、図において、Coxは絶縁膜の容量、Cdepはシ
リコン基板に形成される空乏層の容量である。
Next, an equivalent circuit diagram of the capacitance section of the dRAM is shown in FIG. 3, where Cox is the capacitance of the insulating film and Cdep is the capacitance of the depletion layer formed in the silicon substrate.

ところが、n+層の濃度が薄いと、容量部の等価回路図
は第4図に示される如く、n+層と5i02膜の界面空
乏層Cnが存在し、等価的にCoxより小なるCnが表
に出ることになり、十分な容量が得られない。そこで、
n+層の濃度を十分に大にするために、不純物を十分に
打ち込むと、フィールド酸化11*12の表面がn+型
になり、それが反転するとフィールド酸化Ill!12
の下に電流の路(pa th)が形成される問題がある
However, when the concentration of the n+ layer is low, the equivalent circuit diagram of the capacitive part is shown in Figure 4, where there is an interfacial depletion layer Cn between the n+ layer and the 5i02 film, and Cn, which is equivalently smaller than Cox, appears on the surface. Therefore, sufficient capacity cannot be obtained. Therefore,
When enough impurities are implanted to increase the concentration of the n+ layer, the surface of the field oxide 11*12 becomes n+ type, and when it is reversed, the field oxide Ill! 12
There is a problem in that a current path is formed under the .

本発明はこのような点に鑑みて創作されたもので、絶縁
耐圧に優れ、十分な容量をもったd RAMを製造する
方法を提供することを目的とする。
The present invention was created in view of these points, and an object of the present invention is to provide a method for manufacturing a dRAM having excellent dielectric strength and sufficient capacity.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明実施例の断面図である。 FIG. 1 is a sectional view of an embodiment of the present invention.

第1図において、半導体基板にd RAMを形成するに
おいて、容量部18には基板11の上に直接窒化膜を被
着し、トランジスタ形成部には基板の上にSiO2膜を
形成し、その上に窒化膜を被着する。
In FIG. 1, when forming a dRAM on a semiconductor substrate, a nitride film is directly deposited on the substrate 11 in the capacitor part 18, and a SiO2 film is formed on the substrate in the transistor formation part, and then a SiO2 film is deposited on the substrate. A nitride film is deposited on the surface.

〔作用〕[Effect]

上記方法によって作られたd RAMにおいては、容量
部では基板に直接窒化膜を被着したので、薄い窒化膜を
用いて十分な容量が得られ、トランジスタ形成部には、
基板の上に5i02膜を作り、その上に窒化膜を被着す
るので、絶縁耐圧が高く、かつ、特性の安定したトラン
ジスタが形成されるのである。
In the dRAM made by the above method, the nitride film is directly deposited on the substrate in the capacitor part, so a sufficient capacitance can be obtained using a thin nitride film, and in the transistor forming part,
Since a 5i02 film is formed on the substrate and a nitride film is deposited on it, a transistor with high dielectric strength and stable characteristics is formed.

〔実施例〕〔Example〕

以下、図面を参照して本発明実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図(alに示される如く、半導体基板例えばp型シ
リコン基板11にフィールド酸化膜12とS+02膜2
0を通常の技術で形成する。
As shown in FIG.
0 using conventional techniques.

次に、同図(blに示される如く、トランジスタ形成部
19を覆うレジストパターン21を形成し、ボロンイオ
ン(B+)と砒素イオン(As”)を順にイオン注入し
n+型層13を形成する。n+型層13を濃度が十分に
高いものとするために、As+のドーズ量はlXl0”
5/値2以上とする。
Next, as shown in FIG. 1, a resist pattern 21 is formed to cover the transistor forming portion 19, and boron ions (B+) and arsenic ions (As'') are sequentially implanted to form an n+ type layer 13. In order to make the n+ type layer 13 sufficiently high in concentration, the As+ dose is lXl0''
5/Value should be 2 or more.

次に、同図(C1に示される如く、例えばウェットエツ
チングでSiO2膜20を除去し、かつ、フィールド酸
化膜120表面を2000人程度除去すると、容量部1
8では基板表面が露出し、また前記したAs+のイオン
注入でn+型になったフィールド酸化膜の表面が除去さ
れ、前記した反転は発止しなくなる。レジストパターン
の下、すなわちトランジスタ形成部19には5i02膜
20が残っている。
Next, as shown in FIG.
In step 8, the substrate surface is exposed, and the surface of the field oxide film, which has become n+ type due to the As+ ion implantation, is removed, and the above-described inversion no longer occurs. The 5i02 film 20 remains under the resist pattern, that is, in the transistor forming portion 19.

次に、同図(dlに示される如(、レジストパターン2
1を除去し、全面に窒化膜22を成長すると、容量形成
部18では基板のすぐ上に窒化膜22が、またトランジ
スタ形成部19では基板の上に5iOz Dm!20が
、5i02膜20の上に窒化膜22が形成され、特性に
優れた容量部とトランジスタが形成される。
Next, as shown in the same figure (dl), resist pattern 2
1 is removed and a nitride film 22 is grown on the entire surface, a nitride film 22 of 5iOz Dm! is formed immediately on the substrate in the capacitor formation part 18, and a nitride film 22 of 5iOz Dm! is grown on the substrate in the transistor formation part 19. 20, a nitride film 22 is formed on the 5i02 film 20, and a capacitor portion and a transistor with excellent characteristics are formed.

以後は、通常の技術で第1層ポリシリコン層14、第2
層ポリシリコン層15を形成し、絶縁膜16を全面に被
着し、絶縁1!!i16に電極窓を形成した後A117
を形成しd RAMを完成する。
Thereafter, the first polysilicon layer 14 and the second polysilicon layer 14 are formed using normal techniques.
A layer polysilicon layer 15 is formed, an insulating film 16 is deposited on the entire surface, and an insulating layer 1! ! After forming the electrode window on i16, A117
dRAM is completed.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように、本発明によれば、容量部は基板
の上に直接窒化膜を、またトランジスタ形成部には基板
の上に順に5i02膜と窒化膜を形成することにより、
薄い絶縁膜で十分な容量をもった容量部と特性の安定し
たトランジスタが形成され、d RAMの良好な特性が
得られる効果がある。
As described above, according to the present invention, a nitride film is formed directly on the substrate in the capacitive part, and a 5i02 film and a nitride film are sequentially formed on the substrate in the transistor formation part.
A capacitor portion with sufficient capacity and a transistor with stable characteristics are formed using a thin insulating film, which has the effect of obtaining good characteristics of the dRAM.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)ないしくdlは本発明実施例の断面図、第
2図(alはd RAM平面図、t′b)は同図(a)
のB−B線に沿う断面図、(C)はta+のd l?A
Mの等価回路図、第3図は第2図のd RAMの容量部
の等価回路図、第4図はn+型層の濃度が低い場合の第
2図のd IIAHの容量部の等価回路図である。 第1図と第2図において、 11はシリコン基板、 12はフィールド酸化膜、 13はn+型層、 14は第1層のポリシリコン膜、 15は第2層のポリシリコン膜、 16は絶縁膜、 17はi配線、 18は容量部、 19はトランジスタ形成部、 20は SiO2膜、 代理人 弁理士  井 桁 貞 − d−RAM’G、禾オ■ 第2図
Figures 1 (a) to dl are cross-sectional views of the embodiments of the present invention, and Figure 2 (al is d RAM plan view, t'b) is the same figure (a).
A cross-sectional view taken along line B-B of , (C) is d l? of ta+. A
Fig. 3 is an equivalent circuit diagram of the capacitive part of d RAM in Fig. 2, and Fig. 4 is an equivalent circuit diagram of the capacitive part of d IIAH in Fig. 2 when the concentration of the n+ type layer is low. It is. 1 and 2, 11 is a silicon substrate, 12 is a field oxide film, 13 is an n+ type layer, 14 is a first layer polysilicon film, 15 is a second layer polysilicon film, and 16 is an insulating film. , 17 is the i-wiring, 18 is the capacitance section, 19 is the transistor formation section, 20 is the SiO2 film, Agent: Patent Attorney Sada Igeta - d-RAM'G, Kawao■ Figure 2

Claims (1)

【特許請求の範囲】 一導電形の半導体基板(11)にフィールド酸化膜(1
2)と素子形成領域上に酸化膜(20)を形成する工程
、 前記基板(11)のトランジスタ形成部(19)をレジ
ストパターン(21)で覆い、容量部(18)に基板と
反対導電型の不純物を拡散し、基板と反対導電型層(1
3)を形成する工程、 容量部(18)の酸化膜(20)とフィールド酸化膜(
12)の表面をエッチングで除去し、フィールド酸化膜
に拡散された前記不純物を除去する工程、レジストパタ
ーン(21)を除去し、全面にシリコン窒化膜を被着し
、次いで容量部(18)に容量を、またトランジスタ形
成部(19)にトランジスタを形成することを特徴とす
る半導体装置の製造方法。
[Claims] Field oxide film (1) on semiconductor substrate (11) of one conductivity type
2) and a step of forming an oxide film (20) on the element formation region, covering the transistor formation part (19) of the substrate (11) with a resist pattern (21), and forming the capacitance part (18) with a conductivity type opposite to that of the substrate. Diffusion of impurities into a layer of conductivity type opposite to that of the substrate (1
3) forming the oxide film (20) of the capacitive part (18) and the field oxide film (
Step 12) of removing the impurities diffused into the field oxide film by etching the surface of the resist pattern (21), depositing a silicon nitride film on the entire surface, and then removing the impurities diffused into the field oxide film. A method for manufacturing a semiconductor device characterized by forming a capacitor and a transistor in a transistor forming portion (19).
JP60182288A 1985-08-20 1985-08-20 Manufacture of semiconductor device Pending JPS6242554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60182288A JPS6242554A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60182288A JPS6242554A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6242554A true JPS6242554A (en) 1987-02-24

Family

ID=16115659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60182288A Pending JPS6242554A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6242554A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990007602A1 (en) * 1988-12-27 1990-07-12 Asahi Kasei Kogyo Kabushiki Kaisha Extensible non-woven fabric and its production method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990007602A1 (en) * 1988-12-27 1990-07-12 Asahi Kasei Kogyo Kabushiki Kaisha Extensible non-woven fabric and its production method

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