JPS61216447A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To connect a semiconductor substrate 1 and a first conductive layer 3 at the shortest distance, to increase the speed of a device and to improve the degree of integration thereof by removing one parts of the first conductive layer and an insulating layer, forming a stepped section and applying a second conductive layer onto the semiconductor substrate and the first conductive layer while covering the stepped section. CONSTITUTION:An insulating layer 2 and a first conductive layer 3 are applied onto a semiconductor substrate 1 in succession, one parts of the first conductive layer 3 and the insulating layer 2 are removed to shape a stepped section 5, and a second conductive layer 6 is applied onto the semiconductor substrate 1 and the first conductive layer 3 while covering the stepped section 5. That is, the gate 3 and the substrate 1 are connected by the wiring layer 6 applied while covering the stepped section 5. The wiring layer 6 is wired at the shortest distance, thus improving the degree of integration.

Description

[Detailed Description of the Invention] [Summary] The present invention is suitable for connecting a conductive layer on an insulating layer and a substrate, for example, between a gate and a substrate (source region) of a Mis (metal-insulator-semiconductor structure) device, or Memory cells for DRAM (dynamic random access memory)!
When making a connection between the lower electrode of a storage capacitor and the substrate (source region), etc., a step is formed that exposes both parts to be connected, and a conductive layer is applied thereto to make the connection. This enables integration.

[Industrial application field]

The present invention relates to a method for forming a wiring structure of an old S device.

The old S structure is most commonly used for logic and memory integrated circuits. In recent years, as the scale of these functions has increased, integrated circuits have been required to be extremely highly integrated and densely packed.

Various improvements have also been made to the wiring structure for higher integration.

[Conventional technology]

FIGS. 3(1) and 3(2) are a plan view and a cross-sectional view, respectively, showing a wiring structure connecting a gate and a substrate of a conventional MIS device.

The figure shows an example of connection in a one-layer structure.

In the figure, 31 is a semiconductor substrate, 32 is an insulating layer, 33 is a field oxide film that defines an element region, and 34 is a wiring layer that also serves as a gate electrode and connects the gate and the substrate.

The connection between the wiring layer 34 and the substrate 31 is through the contact hole 35.
It is done in.

In this case, the wiring layer is detoured in a U-shape, which hinders high integration.

Figures 4 (1) and (2) are MIs according to other conventional examples, respectively.
FIG. 2 is a plan view and a cross-sectional view showing a wiring structure connecting a gate and a substrate of an S device.

The figure shows an example of a two-layer structure.

In the figure, 41 is a semiconductor substrate, 42 is an insulating layer, 43 is a field oxide film that defines an element region, 44 is a gate electrode, and 45 is a wiring layer that connects the gate and the substrate. ' Wiring layer 45 is connected to substrate 41 and gate 44 through contact holes 46 and 47, respectively.

In this case as well, the wiring layer is detoured in an L-shape, which hinders high integration.

FIG. 5 is a sectional view showing a wiring structure connecting a lower electrode of an information storage trench capacitor of a conventional DRAM memory cell to a substrate.

In the figure, 51 is a semiconductor substrate, 52 is an insulating layer, 53 is a field oxide film that defines an element region, 54 is a gate electrode, and 55 is a lower electrode of a capacitor, which is a first polycrystalline silicon (
A polySi layer 56 is a capacitor dielectric and is a thin silicon dioxide (SiOz) layer formed by thermally oxidizing the polySi layer 55.
) layer, 57 is the counter electrode of the capacitor and is the second poly-SiN layer.
, 58 are contact holes connecting the substrate 51 and the first poly-Si layer 55 of the lower electrode.

In ultra-large scale integrated circuits, such trench capacitors are used to achieve high integration, but it is difficult to form contacts in contact holes 58 that are suitable for high integration.

[Problem that the invention seeks to solve]

Conventionally, when connecting a first conductive layer on an insulating layer and a substrate,
For example, when connecting between the gate and substrate of an MIS device, or between the lower electrode of the information storage capacitor of a memory cell and the substrate, the two parts to be connected are separated by a distance, making it difficult to achieve high integration. It was hindering me.

[Means for solving problems]

To solve the above problem, an insulating layer 2 and a first
conductive layers 3 are sequentially deposited, a portion of the first conductive layer 3 and the insulating layer 2 is removed to form a step 5, and a step 5 is formed on the semiconductor substrate 1 and the first conductive layer 3, covering the step 5. Second
This is achieved by a method for manufacturing a semiconductor device, which includes the step of depositing a conductive layer 6.

The step 5 may be formed by opening the insulating layer 4 and exposing the surfaces of the semiconductor substrate 1 and the first conductive layer 3.

[Effect]

The present invention includes a semiconductor substrate 1 and a first conductive layer 3 formed by patterning on an insulating layer 2 deposited on the substrate 1.
After exposing a portion or the entire surface, the second conductive layer 6 is selectively deposited on the exposed portion to connect the semiconductor substrate l and the first conductive layer 3 over the shortest distance, thereby increasing the speed of the device. , which enables high integration.

〔Example〕

FIGS. 1(1) and 1(2) are a plan view and a cross-sectional view, respectively, showing the wiring structure connecting the gate and substrate of the HIS device according to the present invention.

In the figure, 1 is a semiconductor substrate, which is a Si substrate, 2 is an insulating layer, which is an SiO2 layer, 3 is a first conductive layer, which is a gate electrode made of polySt, 4 is a cover insulating layer, which is a SiO2 layer, 5 is a step, and 6
is a second conductive layer and is a wiring layer that connects the gate and the substrate.

Note that 11 is a p-type silicon (St) substrate, 12 is a field oxide film that defines an element region, 13 is an n-type source region,
14 is an n+ type drain region.

Connection between the gate 3 and the substrate 1 is made by a wiring layer 6 deposited over the step 5.

The wiring layer 6 is deposited over the step 5 by selective epitaxial growth of St. In this case, the single crystal does not grow on the cover insulating layer 4, but on the Si of the substrate 1, and the single crystal grows on the gate 3.
Poly-St grows on the poly-Si.

Epitaxial growth was performed using trichlorosilane (SiHCls) as a reactive gas and phosphin (P) as a dopant.
The reaction vessel is depressurized to 0.1 Torr using H3) and thermally decomposed at 800°C.

Alternatively, it may be grown undoped and then doped later using ion implantation or the like.

Further, the wiring layer 6 can also be formed by selective growth of tungsten (!A).

In this case, the wiring layer 6 is wired at the shortest distance, making it possible to achieve high integration.

FIG. 2 is a sectional view showing a wiring structure connecting the lower electrode of the information storage trench capacitor and the substrate of the DRAM memory cell according to the present invention.

In the figure, 1 is a semiconductor substrate, which is a Si substrate, 2 is an insulating layer, which is a SiO□ layer, 3 is a first conductive layer, which is a lower electrode of a capacitor made of a first poly-Si layer, 5 is a step, and 6 is a second This is a wiring layer made of a Si layer that connects the lower electrode and the substrate as a conductive layer, and is grown to cover the step 5 in the same manner as in FIG.

In addition, 12 is a field oxide film defining an element region, and 13 is an n-type source region.

21 is a capacitor dielectric, which is a thin SiO2 layer formed by thermal oxidation of the Si wiring layer 6 grown on the lower electrode 3.
It is a layer.

22 is a second poly-Si layer which is a counter electrode of the capacitor.

In this case as well, the wiring layer 6 is wired at the shortest distance, making it possible to achieve high integration.

[Effects of the Invention] As described in detail above, according to the present invention, when connecting a conductive layer on an insulating layer and a substrate, both parts to be connected are connected with the shortest distance between them. Enables high integration of devices.

[Brief explanation of drawings]

FIG. 1 (11 and (2)) are a plan view and a cross-sectional view, respectively, showing the wiring structure connecting the gate and substrate of the MIS device according to the present invention, and FIG. 2 is an information storage trench capacitor of a DRAM memory cell according to the present invention. 3(l) and (2) are a plan view and a sectional view, respectively, showing the wiring structure connecting the gate and substrate of a conventional MIS device. , Figures 4 (1) and (2) respectively show MI according to other conventional examples.
A plan view and a cross-sectional view showing the wiring structure connecting the gate and the substrate of the S device, and FIG. 5 is a cross-sectional view showing the wiring structure connecting the lower electrode of the information storage trench capacitor of the conventional DRAM memory cell and the substrate It is a diagram. In the figure, 1 is a semiconductor substrate, which is a Si substrate, 2 is an insulating layer, which is a 5tCh layer, 3 is a first conductive layer, which is a gate electrode made of a first poly-Si layer, or the lower electrode of a capacitor, and 4 is a cover insulating layer. 5iOz layer, 5 is a step, and 6 is a second conductive layer, which is a wiring layer that connects the gate or the lower electrode and the substrate. 11 is a p-type St substrate, 12 is a field oxide film that defines the element region, and 13 is an n-type St substrate.
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Claims (4)

[Claims] (1) Sequentially depositing an insulating layer (2) and a first conductive layer (3) on a semiconductor substrate (1), and depositing a part of the first conductive layer (3) and the insulating layer (2). forming a step (5) by removing the step, and depositing a second conductive layer (6) on the semiconductor substrate (1) and the first conductive layer (3) to cover the step (5). A method for manufacturing a semiconductor device, characterized in that: (2) The semiconductor according to claim 1, characterized in that the second conductive layer (6) is selectively grown on the semiconductor substrate (1) and the first conductive layer (3). Method of manufacturing the device. (3) Covering the semiconductor substrate (1) and the first conductive layer (3) formed by patterning on the first insulating layer (2) deposited on the semiconductor substrate (1). and the second insulating layer (
4), exposing the surfaces of the semiconductor substrate (1) and the first conductive layer (3) and forming an opening in the second insulating layer (4), and forming a second conductive layer in the opening. A method for manufacturing a semiconductor device, comprising the step of depositing a conductive layer (6). (4) The method for manufacturing a semiconductor device according to claim 3, characterized in that the second conductive layer (6) is selectively grown in the opening.