JPS6240797B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to nonvolatile semiconductor memory.

[Technical background of the invention]

Generally speaking, among PROMs (programmable read-only memories), EPROMs (erasable PROMs), which can be erased by the user using ultraviolet rays and electrically rewritten, have recently become very popular as memory for microcomputers due to their convenience. . Figure 1 shows a part of a conventional example of such an EPROM, and 1 ₀ to 1 _o each represent an insulated gate field effect transistor (e.g.
Row decoder using MOS-FET), 2 ₀ ~
2 _o is a row buffer circuit also using MOS-FETs, and 3 ₀ to 3 _o are row lines of a memory cell array 4 using nonvolatile semiconductor memory elements. The row decoders ₁₀ to _1o above are address data respectively.
A ₀ to A _i are input, and one row line is selected and driven by the combination of "1" and "0" of this data A ₀ to A _i , and this selected row line becomes active. status (“1” level). That is, when the address data A ₀ to _{A i} are all "0", row line ₃₀ is selected, A ₀ = "1", A ₁ to
When A _i =“0”, row line ₃₁ is selected. Note that in each row buffer circuit ₂₀ to _2o , 5
is a write circuit that supplies a write voltage (a high voltage of 20 to 25 V, for example, a so-called program pulse) to the corresponding row lines ₃₀ to _3o when writing to the memory cell array 4.

[Problems with background technology]

By the way, when erasing the memory contents of the memory cell array 4, it takes a considerable amount of time (approximately 30 minutes), and moreover, the memory contents of all memory cells of the memory cell array 4 are erased. For this reason, conventionally, even when it is desired to rewrite only a part of the memory contents of the memory cell array 4, it is necessary to erase the contents of all the memory cells and then write to all the memory cells again. As mentioned above, the erasing time alone is disadvantageous in that it requires a long time.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
It is an object of the present invention to provide a nonvolatile semiconductor memory in which not only a part of a memory cell array can be rewritten easily and in a short time, but also the yield rate of non-defective products at the manufacturing stage can be improved.

[Summary of the invention]

In order to achieve the above object, this invention includes:
A non-volatile semiconductor in which a spare memory cell is provided in a part of a memory cell array, and a spare decoder is provided using a non-volatile semiconductor memory element in which address data for selecting this memory cell can be written. Memory is provided.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 2, 10 is a memory cell array using nonvolatile semiconductor memory elements that can be erased by ultraviolet rays and can be electrically rewritten;
In addition to the normally used main memory cell area M, it has a spare memory cell area S (for example, two rows of memory cells) that is partially used for rewriting _.
R _o is a row line of the main memory cell area, and R' ₁ and R' ₂ are row lines of the spare memory cell area S. Decoders ₁₀ to 1o and row buffer circuits _{20 to 2o} similar to those shown in FIG. 1 are provided corresponding to row lines _R0 to _R0 of the main memory cell area M, and spare memory cells Spare row decoders 11 and 12 and spare row buffer circuits 13 and 14 are provided corresponding to row lines R' ₁ and R' ₂ in area S. In the spare row decoders 11 and 12, 2(i+1) non-volatile semiconductor memory elements such as floating gate memory cell transistors T ₀ -T _i , T' ₀ -
T' _i are connected in parallel, and address data A ₀ -A _i and ₀ - _i are applied to these gates. Also, a depletion type transistor _T whose gate and source are connected between the connection line 15 of the transistors T 0 to _{T i} and T' ₀ to T' _i and the power supply V _c
A series connection circuit of _D and an enhancement type transistor T _E is inserted, and an enhancement type transistor T' _E is inserted between the connection line 15 and the power supply terminal 16. A signal R/ (R/ ₁ in the decoder 11, R/ 2 in the decoder 12) which becomes 0V when writing an address is applied to the gate of the transistor T _E , and a signal R/ (R/ 1 in the decoder 11 and R/ ₂ in the decoder 12) is applied to the gate of the transistor T _' Signal /P (/P ₁ in decoder 11, decoder 1
2, /P ₂ ) is applied.

On the other hand, the spare row buffer circuits 13 and 14 are
The configuration is similar to that of normal buffer circuits ₂₀ to _2o .

Further, between the decode output lines 6 ₀ - 6 _o of the normal row decoders 1 ₀ - 1 _o and the ground terminal, there are connected the drains and drains of two transistors T _A and T _B , respectively.
Each gate of the transistor T _A group is connected to the output terminal of the spare row buffer circuit 13 by a signal line 7, and each gate of the transistor T _B group is connected to the spare row buffer circuit 14.
It is connected to the output end of the signal line 8 by a signal line 8.

Note that 16 is a column decoder for selecting a column line of the memory cell array 10, and illustration of other peripheral circuits is omitted. Further, the memory shown in FIG. 2 is manufactured by an N-channel process.

Next, the operation of the nonvolatile semiconductor memory with the above configuration will be explained. In normal writing, input data is set, row lines _R0 to _R0 of the main memory cell area M are selected by the row decoders ₁₀ to _1o , and the write circuits of the buffer circuits ₂₀ to _2o (see FIG. (see 5)
A write voltage V _P is applied to the main memory cell area M to write input data into the memory cells of the main memory cell area M.

Next, when part of the written content is to be rewritten as described above, an address that requires rewriting is specified using address data, and this address is assigned to a row line of the spare memory cell area S. That is, for example, when rewriting the memory contents of the memory cell of row line _R0 , the address data _A0 to _Ai inputs are set to "0" and _{the 0} to _i inputs are set to a high voltage (for example,
25V), the R/ ₁ input is set to “0”, the / _P1 input is set to a high voltage (for example, 25V), and a high voltage (for example, 25V) program pulse is applied to the power supply terminal 16, the transistor T _E is turned off. , transistor
T′ _E is turned on, and floating gate transistors T′ ₀ to T′ _i to which ₀ to _i inputs are applied
A high voltage is applied to the drain and gate of each floating gate, and electrons are injected into each floating gate. As a result, the transistors T' ₀ to T' _i become cut-off when the gate input voltage is in the range of 0 to V _c , and A ₀ to A _i = "0" on the row line R' ₁ .
address has been assigned. Therefore, after this, A ₀ ~A _i = "0", ₀ ~ _i =
If you set “1” (V _c ), R/ ₁ = “1”, /P ₁ = “0” and enter the read state, the spare row decoder 1
Since the decode output of 1 is "1" and the row line R' ₁ is selected, the write voltage V _P is applied to the write circuit (see FIG. ₁ , 5) of the spare row buffer circuit 13 corresponding to this row line R' 1. By applying the row line
It is possible to newly write input data separately given to the memory cell _R'1 , and equivalently, it is possible to rewrite the memory contents of the memory cell connected to the row line _R0 of the main memory cell area M. In other words, when addressing A ₀ to A _i =“0” is made to the memory cell array 10 that has been partially rewritten without erasing the entire memory contents of the memory cell array 10, the spare row The decoder 11 and the spare row buffer circuit 13 automatically select the row line R' ₁ of the spare memory cell area S, and at this time, the "1" output of the spare row buffer circuit 13 is applied to the gate via the signal line 7. The transistor T _A is turned on, and the selection operation of the row line R ₀ of the main memory cell area M by the row decoder 10 is prohibited.

Similarly, the spare row decoder 12 and the spare row buffer circuit 14 also adjust the above A ₀ to _{A i} =
By assigning an address other than "0" to the row line _R'2 of the spare memory cell area S and performing writing, the memory cells in the main memory cell area M having the same address as this assigned address can be rewritten.
This can be done easily and in a short time without completely erasing the memory cell array.

In the above embodiment, two rows of spare memory cells are provided, but the invention is not limited to this. Three or more rows of memory cells are provided, and correspondingly, the spare row decoders 11 and 1 are provided.
2, spare row buffer circuits 13, 14, signal line 7,
8. By adding transistors T _A and T _B , the rewrite capacity can be increased. In addition, when providing a plurality of (j) rows of spare memory cells, the signal lines 7 and 8 and the transistors T _A and T _B are connected to one each in each of the row decoders 1 ₀ to 1 _o .
In order to use a single circuit, the outputs P ₁ to P _j of each spare row buffer circuit are led to a NOR gate 30 as shown in FIG. Signal line 32
It may also be possible to send it to That is, this signal line 32 corresponds to the signal line 7 or 8.

Note that the memory cell array 1 in the above embodiment
0 and the spare row decoders 11 and 12 may be floating gate transistors or other transistors having charge trapping means in the gate insulating film, such as SiO ₂ MNOS (metal nitride oxide semiconductor) transistors in which Si ₃ N ₄ (silicon nitride) is provided between a silicon oxide (silicon oxide) film and a polysilicon layer, fuse-blown memory cells, or a combination of these. Available for use. This invention is particularly effective in the case of a fuse blowing type PROM. With the fuse type, once writing is done, it cannot be rewritten. Therefore, even if it becomes necessary to rewrite the memory contents of some memory cells, a separate fuse blowing type
It is necessary to newly write to PROM. Every time you change some memory contents, you have to use a new one. At times like this,
If the functions shown in the present invention are provided, even in a fuse blowing type PROM, the stored contents of only a portion of the memory cell can be rewritten, and there is no need to use a different one each time a portion is rewritten.

Further, in the above embodiment, spare memory cells are provided for the memory cells in the row line direction of the main memory cell area, but spare memory cells may be provided for the memory cells in the row line direction of the main memory cell area. In this case, a spare column decoder may be provided to select a column line in the spare memory cell area, and the selection output of this spare column decoder may be used to inhibit the selection output of the column decoder corresponding to the main memory cell area. .

As described above, according to the nonvolatile semiconductor memory of the above embodiment, a spare memory cell area is provided in addition to the main memory cell area as a memory cell array, and a row line or a column line of this spare memory cell area is selected. A spare row decoder or a spare row decoder using a non-volatile semiconductor memory element is provided, and an address decoder corresponding to a memory cell that requires rewriting in the main memory cell area is written into the spare row decoder or spare column decoder. The selective output of the spare row decoder or column decoder inhibits the selective output of the row decoder or column decoder corresponding to the main memory cell area.

Therefore, the user can easily rewrite only a portion of the memory contents of the memory cell array without erasing all of the memory contents, which significantly reduces the relatively long time conventionally required for erasure. This makes it even more convenient to use EPROM.

Also, on the manufacturer's side, if some of the memory cells, for example, one memory cell, cannot be written to during EPROM manufacture, this EPROM is treated as a defective product, but according to the present invention, the defective memory By writing (address programming) into a spare decoder so as to select a spare memory cell in a spare memory cell area instead of a cell, this EPROM can be treated as a good product and the yield can be improved. In this case, an ultraviolet erasable memory element is used in the spare decoder as well, and a device is devised to prevent the contents of the spare decoder from being erased when the memory cell array is irradiated with ultraviolet light. That is, the preliminary decoder section is covered with a metal such as aluminum that does not transmit ultraviolet rays so as to prevent irradiation of the memory element with ultraviolet rays.

The present invention provides for switching to a spare memory cell.
Since a floating gate type non-volatile memory element that constitutes the memory cell is used, the method for writing data to the non-volatile memory element for switching may be the same as the method for writing data to the above-mentioned memory cell. Therefore, the probability of failure is extremely low.

That is, in the past, polysilicon fuse elements, for example, were cut with a laser beam, but this had the disadvantage that it took a long time to align the sights when cutting the fuse, resulting in a long test time. Further, when cutting, polysilicon splashes and there is a risk of adversely affecting other elements in terms of reliability. Furthermore, when an excessive current is applied to the polysilicon fuse element to cause it to break, a circuit is required to apply the excessive current to the polysilicon fuse element, and droplets fly off when the fuse element is fused, as described above.

As described above, switching to a spare cell in a floating gate type nonvolatile memory element has the advantage that test time is shortened and other elements are not adversely affected. Recently, non-volatile semiconductor memory that can be erased by ultraviolet light has been sealed in a plastic package and is being sold as One Time PROM, which cannot be erased by ultraviolet light once written to.
In other words, a floating gate MOSFET is used as a memory cell and is sealed in plastic that does not transmit ultraviolet rays. In such a one-time PROM, there is no need to particularly cover non-volatile memory cells with A or the like for switching to spare memory cells.

〔Effect of the invention〕

As described above, the present invention not only enables partial rewriting of a memory cell array using nonvolatile semiconductor memory elements easily and in a short time, but also
It is possible to provide a nonvolatile semiconductor memory that can improve the yield rate of non-defective products at the manufacturing stage.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a conventional nonvolatile semiconductor memory, FIG. 2 is a configuration explanatory diagram showing an embodiment of a nonvolatile semiconductor memory according to the present invention, and FIG. 8 and transistors T _A , T _B
FIG. 4 is a circuit diagram showing a modification of a related part. 1 ₀ to 1 _o ... row decoder, 5... writing circuit,
6 ₀ to 6 _o ...Decode output line, 10...Memory cell array, 11, 12...Spare row decoder, 16...Column decoder, _R0 to _Ro , _R'1 , _R'2 ...Row line, _T0 to T _i ,
_T'0 to _T'i ...Floating gate type transistor, M...Main memory cell area, S...Spare memory cell area.

Claims (1)

[Claims] 1. A memory cell array using a data-erasable first nonvolatile semiconductor memory element and having a main memory cell area and a spare memory cell area that is used by switching with a part of the main memory cell area;
A row decoder and a column decoder that select a row line and a column line of the main memory cell area by address input, and a second nonvolatile semiconductor memory element having the same structure as the first nonvolatile semiconductor memory element. switching address storage means for storing an address for switching a part of the main memory cell area to the spare memory cell area; and a second non-volatile storage means for storing data stored in the memory cell array. erase prevention means for preventing erasure of storage addresses in the semiconductor memory device; a write circuit that supplies a write voltage when writing data to the memory element connected to the corresponding row line and column line; and a write circuit that supplies a write voltage when writing data to the memory element connected to the corresponding row line and column line; 1. A non-volatile semiconductor memory comprising prohibition means for prohibiting establishment of a selected output of a row decoder or a column decoder.