JPS6312387B2 - - Google Patents
Info
- Publication number
- JPS6312387B2 JPS6312387B2 JP15039381A JP15039381A JPS6312387B2 JP S6312387 B2 JPS6312387 B2 JP S6312387B2 JP 15039381 A JP15039381 A JP 15039381A JP 15039381 A JP15039381 A JP 15039381A JP S6312387 B2 JPS6312387 B2 JP S6312387B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor memory
- memory element
- insulated gate
- gate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- XUFQPHANEAPEMJ-UHFFFAOYSA-N famotidine Chemical group NC(N)=NC1=NC(CSCCC(N)=NS(N)(=O)=O)=CS1 XUFQPHANEAPEMJ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 101100524639 Toxoplasma gondii ROM3 gene Proteins 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- ICSAXRANXQSPQP-VUKDEKJYSA-M sodium;(5r,6s)-6-[(1r)-1-hydroxyethyl]-7-oxo-3-[(2r)-oxolan-2-yl]-4-thia-1-azabicyclo[3.2.0]hept-2-ene-2-carboxylate Chemical group [Na+].S([C@@H]1[C@H](C(N1C=1C([O-])=O)=O)[C@H](O)C)C=1[C@H]1CCCO1 ICSAXRANXQSPQP-VUKDEKJYSA-M 0.000 description 3
- 102100031584 Cell division cycle-associated 7-like protein Human genes 0.000 description 2
- 101000777638 Homo sapiens Cell division cycle-associated 7-like protein Proteins 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特に同一半導体基
板に絶縁ゲート型不揮発性半導体記憶素子を用い
て構成される回路が２つ以上形成される絶縁ゲー
ト型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an insulated gate semiconductor device in which two or more circuits each using an insulated gate nonvolatile semiconductor memory element are formed on the same semiconductor substrate.
従来、同一半導体基板に絶縁ゲート型半導体記
憶素子を用いて構成される回路が２つ以上形成さ
れるものの例として、同一半導体基板に中央処理
装置（以下CPUと記す）と半導体記憶素子とを
持つマイクロコンピユータ用半導体装置がある。 Conventionally, as an example of a circuit in which two or more circuits each using an insulated gate type semiconductor memory element are formed on the same semiconductor substrate, a central processing unit (hereinafter referred to as CPU) and a semiconductor memory element are formed on the same semiconductor substrate. There are semiconductor devices for microcomputers.
第１図は従来のマイクロコンピユータ用半導体
装置の一例のブロツク図である。 FIG. 1 is a block diagram of an example of a conventional semiconductor device for a microcomputer.
この半導体装置は、外部からの情報内容を入力
する入力回路と外部に情報内容を出す出力回路を
持つ入出力（Ｉ／Ｏ）部１と、情報内容を読出し
たり、書込んだりする半導体記憶素子を持つ
RAM２と、情報内容を読出す読出し専用半導体
記憶素子部であるROM３と、入出力部１、
RAM２、ROM３を制御する制御信号を発生す
るCPU４より成り、CPU４には命令デコーダ５
が内蔵されている。命令デコーダ５はRAM２及
びROM３を構成する半導体記憶素子の情報内容
を読出す事により制御信号を発生する機能を持
ち、この命令デコーダ５に用いられる半導体記憶
素子はROM３を構成する読出し専用半導体記憶
素子と同じ働きをして、一般に同じ構造を持つ。 This semiconductor device includes an input/output (I/O) section 1 having an input circuit for inputting information contents from the outside and an output circuit for outputting the information contents to the outside, and a semiconductor memory element for reading and writing the information contents. have
RAM2, ROM3 which is a read-only semiconductor memory element section for reading out information contents, input/output section 1,
It consists of a CPU 4 that generates control signals to control RAM 2 and ROM 3, and the CPU 4 has an instruction decoder 5.
is built-in. The instruction decoder 5 has a function of generating a control signal by reading the information contents of the semiconductor memory elements constituting the RAM2 and ROM3, and the semiconductor memory element used in this instruction decoder 5 is a read-only semiconductor memory element constituting the ROM3. and generally have the same structure.
前記の命令デコーダ５及びROM３を構成する
半導体記憶素子に情報内容を書込むには、半導体
装置製造過程で書込む方法が従来一般化してい
る。しかし、情報内容を書き換える場合、その都
度半導体装置の製造過程で書込まなければならな
いという欠点があつた。 In order to write information contents into the semiconductor memory elements constituting the instruction decoder 5 and ROM 3, a method of writing during the semiconductor device manufacturing process has conventionally been common. However, when rewriting the information content, it has the disadvantage that it must be written during the manufacturing process of the semiconductor device each time.
これに対して、最近ROMを不揮発性半導体記
憶素子で形成する１チツプ・マイクロコンピユー
タが発表されている。不揮発性半導体記憶素子に
は、一般に広く知られているものとして、
MNOS構造のものと浮遊ゲートを有する
FAMOS構造のものとが有る。MNOS構造の不
揮発性半導体記憶素子は電気的書込・消去が可能
であるという性質、FAMOS構造の不揮発性半導
体記憶素子は電気的書込み、紫外線照射による消
去が可能であるという性質を有する。 In contrast, a one-chip microcomputer in which the ROM is formed from a nonvolatile semiconductor memory element has recently been announced. Non-volatile semiconductor memory elements are generally known as:
MNOS structure and floating gate
There is also one with FAMOS structure. A non-volatile semiconductor memory element having an MNOS structure has the property that it can be electrically written and erased, and a non-volatile semiconductor memory element having a FAMOS structure has the property that it can be electrically written and erased by ultraviolet irradiation.
以上述べたように不揮発性半導体記憶装置素子
をROMに用いる事により情報内容を書き換える
場合、その都度半導体装置の製造過程で書込まな
ければならないという欠点が解消される。しか
し、CPUの半導体記憶素子の読出し情報内容を
書換える場合、前記と同様に製造過程で書込まな
ければならないという欠点がある。この欠点を解
消する方法として、CPUとROMの半導体記憶素
子に上記の不揮発性半導体記憶素子に用いる方法
がある。 As described above, when rewriting information contents by using a nonvolatile semiconductor memory device element as a ROM, the disadvantage that the information must be rewritten each time during the manufacturing process of the semiconductor device can be overcome. However, when rewriting the read information content of the semiconductor memory element of the CPU, there is a drawback that the writing must be done during the manufacturing process, as described above. As a method to overcome this drawback, there is a method of using the above-mentioned nonvolatile semiconductor memory element in the semiconductor memory element of the CPU and ROM.
しかし、CPUとROMに浮遊ゲートを有する
FAROM構造を用いると、紫外線照射により消
去する場合、CPUとROMのFAROMに蓄積され
ている情報内容の消去が同時に行なわれ、CPU
とROMの一方の情報内容を保存し、かつ、他方
の情報内容を消去する事は困難である。これに対
し、CPUとROMにMNOS構造を用いると、消去
する場合CPUとROMの一方の情報内容を保存
し、他方を消去する事は可能である。しかし、
MNOS構造をマトリツクス状に配列した場合、
電気的書込み及び消去するため２つ以上の選択用
の絶縁ゲート型半導体素子をそれぞれのMNOS
構造に接続する必要がある。このため大容量でマ
トリツクス状に配列するのに適さないという欠点
があつた。 But with floating gates in CPU and ROM
When using the FAROM structure, when erasing information by UV irradiation, the information stored in the FAROM of the CPU and ROM is simultaneously erased, and the CPU
It is difficult to save the information content of one of the ROMs and erase the information content of the other. On the other hand, if the MNOS structure is used for the CPU and ROM, it is possible to save the information content of one of the CPU and ROM and erase the other. but,
When MNOS structures are arranged in a matrix,
Each MNOS selects two or more insulated gate semiconductor devices for electrical programming and erasing.
Must be connected to a structure. For this reason, it has the disadvantage that it has a large capacity and is not suitable for arranging in a matrix.
本発明の目的は上記欠点を除去し、同一半導体
基板に不揮発性半導体記憶素子を用いる回路が２
つ以上ある場合、それぞれ独立して読出し、書
込、消去することが可能で、かつ高集積度に形成
することが可能な半導体装置を提供する事にあ
る。 An object of the present invention is to eliminate the above-mentioned drawbacks, and to enable two circuits using non-volatile semiconductor memory elements on the same semiconductor substrate.
The object of the present invention is to provide a semiconductor device that can be read, written, and erased independently of each other when there are more than one, and that can be formed with a high degree of integration.
本発明の半導体装置は、浮遊ゲートを有し電気
的書込み可能で紫外線で消去可能な第１の絶縁ゲ
ート型不揮発性半導体記憶素子と、電気的書込み
可能で紫外線照射で消去されず電気的消去可能な
第２の絶縁ゲート型不揮発性半導体記憶素子とを
同一半導体基板に含んで構成される。 The semiconductor device of the present invention includes a first insulated gate nonvolatile semiconductor memory element having a floating gate, electrically writable and erasable with ultraviolet rays, and electrically writable and electrically erasable without being erased by ultraviolet irradiation. and a second insulated gate type nonvolatile semiconductor memory element on the same semiconductor substrate.
本発明の実施例について図面を用いて説明す
る。 Embodiments of the present invention will be described with reference to the drawings.
第２図は本発明の一実施例の断面図である。 FIG. 2 is a sectional view of one embodiment of the present invention.
Ｐ型半導体基板１１にN+型のソース及びドレ
イン領域１２〜１７を設け、基板表面にSiO2膜
１８〜２１を設ける。 N + type source and drain regions 12-17 are provided on a P-type semiconductor substrate 11, and SiO 2 films 18-21 are provided on the substrate surface.
第１の絶縁ゲート型不揮発性半導体記憶素子
M1は、SiO2膜１８の上に浮遊ゲートFGを設け、
その上にSiO2膜２２を設け、更にその上に金属
層２８を設けて形成したゲート電極G1と、N+型
のソース領域１２、ドレイン領域１３にそれぞれ
設けたソース電極S1、ドレイン電極D1とから成
る。 First insulated gate nonvolatile semiconductor memory element
M1 has a floating gate FG on the SiO 2 film 18,
A gate electrode G 1 is formed by providing an SiO 2 film 22 thereon and a metal layer 28 thereon, and a source electrode S 1 and a drain electrode are provided in the N + type source region 12 and drain region 13 , respectively. Consists of D 1 .
この素子M1はFAROM構造で電気的書込み可
能で、紫外線照射で消去可能である。この素子
M1への書込みは、ゲート電極G1に高電圧を印加
し、ドレイン電極D1−ソース電極S1間に電圧を
印加して浮遊ゲートFGにキヤリアを注入するこ
とにより行なわれる。消去は紫外線を照射して浮
遊ゲートFGに蓄積されている電荷を放出させる
ことにより行なわれる。 This element M1 has a FAROM structure and is electrically writable and erasable by ultraviolet irradiation. This element
Writing to M 1 is performed by applying a high voltage to the gate electrode G 1 and applying a voltage between the drain electrode D 1 and the source electrode S 1 to inject carriers into the floating gate FG. Erasing is performed by irradiating ultraviolet rays to release the charges accumulated in the floating gate FG.
第２の絶縁ゲート型不揮発性半導体記憶素子
M2は、SiO2膜２０の上に窒化シリコン膜２３を
設け、その上に金属層２６を設けて形成したゲー
ト電極G2とN+型ソース領域１５、ドレイン領域
１６にそれぞれソース領域S2、ドレイン領域D2
とを設けて構成される。 Second insulated gate nonvolatile semiconductor memory element
M 2 is a gate electrode G 2 formed by providing a silicon nitride film 23 on a SiO 2 film 20 and a metal layer 26 thereon, and a source region S 2 in an N + type source region 15 and a drain region 16, respectively. , drain region D 2
It is composed of:
この素子M2はMNOS構造で、電気的書込み可
能で、紫外線照射しても消去されず、電気的消去
可能である。ゲート電極G2と半導体基板１１と
の間に高電圧を印加することにより書込み可能で
ある。M2D，M2Sは、上記のMNOS構造の素子
M2がマトリツクス状に配列されている場合の選
択読出し、書込みを行うための選択読出し書込み
用半導体素子である。M2DはＮ型ソース領域１
４、ドレイン領域１５、ゲートG2Sで構成され、
M2DはＮ型のソース領域１６、ドレイン領域１
７、ゲートG2Dで構成される。素子M2，M2Sとは
Ｎ型領域１５を素子M2とM2DとはＮ型領域１６
を共用している。従つて、電極S2，D2も共通で
ある。 This element M2 has an MNOS structure, is electrically writable, is not erased by ultraviolet irradiation, and is electrically erasable. Writing is possible by applying a high voltage between the gate electrode G2 and the semiconductor substrate 11. M 2D and M 2S are the elements of the above MNOS structure
This is a selective read/write semiconductor element for selective read/write when M2 is arranged in a matrix. M2D is N-type source region 1
4. Consists of drain region 15 and gate G2S ,
M2D is an N-type source region 16, drain region 1
7. Consists of gate G 2D . Elements M 2 and M 2S are N-type regions 15, and elements M 2 and M 2D are N-type regions 16.
are shared. Therefore, electrodes S 2 and D 2 are also common.
以上のようにして、同一の半導体基板１１に浮
遊ゲートを有し、電気的書込み可能で消去可能な
第１の絶縁ゲート型不揮発性半導体記憶素子M1
と、電気的書込み可能で紫外線照射で消去されず
電気的消去可能な第２の絶縁ゲート型不揮発性半
導体記憶素子M2とを含んだ半導体装置が得られ
る。 As described above, the first insulated gate nonvolatile semiconductor memory element M 1 which has a floating gate on the same semiconductor substrate 11 and is electrically writable and erasable
and a second insulated gate nonvolatile semiconductor memory element M 2 that is electrically writable and not erased by ultraviolet irradiation but is electrically erasable.
第３図は第２図に示す一実施例の書込み消去後
の電気的特性を示す特性曲線図である。 FIG. 3 is a characteristic curve diagram showing the electrical characteristics of the embodiment shown in FIG. 2 after writing and erasing.
ゲート電圧VGに対するドレイン・ソース間電
流IDSは書込み及び消去により図示したように移
動する。 The drain-source current I DS with respect to the gate voltage V G moves as shown in the figure due to writing and erasing.
第２図に示した一実施例の半導体装置におい
て、選択読出しを行なう場合には、素子M2のゲ
ート電極G2に読出し電圧を印加して素子M2Sを導
通させ、素子M2Dで選択・非選択を制御する。選
択書込みを行なう場合、ゲート電極G2に書込み
電圧を印加し、素子M2Sを非導通にして、素子
M2Dで選択・非選択を制御する。このように
MNOS構造を用いる場合、１記憶素子は絶縁ゲ
ート型半導体を三つ必要とする。これに対して
FAMOS構造では一つで良い。 In the semiconductor device of the embodiment shown in FIG. 2, when selective reading is to be performed, a read voltage is applied to the gate electrode G2 of the element M2 to make the element M2S conductive, and the element M2D is selected and read. Control deselection. When performing selective writing, a write voltage is applied to the gate electrode G2 , the element M2S is made non-conductive, and the element M2S is made non-conductive.
Control selection/non-selection with M 2D . in this way
When using the MNOS structure, one memory element requires three insulated gate semiconductors. On the contrary
In the FAMOS structure, one is enough.
同一半導体基板にROMが２個以上ある場合、
または命令デコーダとROMが有る場合、記憶素
子の数（即ち記憶容量）が大きい回路部には
FAMOS構造、記憶素子の数が小さい回路部に
は、MNOS構造を用いる事により、互いに独立
に消去でき、しかも高集積度の半導体装置を得る
事が可能になる。 If there are two or more ROMs on the same semiconductor board,
Or, if there is an instruction decoder and ROM, the circuit part with a large number of storage elements (i.e. storage capacity)
By using the FAMOS structure or the MNOS structure for a circuit section with a small number of memory elements, it becomes possible to erase data independently of each other and to obtain a highly integrated semiconductor device.
上記実施例ではＮチヤンネル型絶縁ゲート型半
導体素子で説明したがＰチヤンネル型でも同様で
あることは明らかである。 In the above embodiment, an N-channel type insulated gate type semiconductor device was explained, but it is clear that the same applies to a P-channel type.
以上詳細に説明したように、本発明によれば、
読出し専用記憶素子を用いた回路部が２つ以上同
一半導体基板に設けられ、それぞれ独立して読出
し、書込み、消去する事が可能で、かつ高集積度
に形成する事が可能になるという半導体装置を得
ることができるのでその効果は大きい。 As explained in detail above, according to the present invention,
A semiconductor device in which two or more circuit parts using read-only memory elements are provided on the same semiconductor substrate, each can be independently read, written, and erased, and can be formed with a high degree of integration. The effect is great because you can get
第１図は従来のマイクロコンピユータ用半導体
装置の一例のブロツク図、第２図は本発明の一実
施例の断面図、第３図は第２図に示す一実施例の
書込み、消去後の電気的特性を示す特性曲線図で
ある。
１…入出力部、２…RAM、３…ROM、４…
CPU、１１…Ｎ型半導体基板、１２〜１７…Ｎ
型領域、１８〜２２…SiO2膜、２３…窒化シリ
コン膜、２５〜２８…電極、Ａ…ソース電極、Ｂ
…ドレイン電極、D1，D2…ドレイン電極、G1，
G2，G2D，G2S…ゲート電極、M1…第１の絶縁ゲ
ート型不揮発性半導体記憶素子、M2…第２の絶
縁ゲート型不揮発性半導体記憶素子、M2D，M2S
…選択読出し書込み用半導体素子。
FIG. 1 is a block diagram of an example of a conventional semiconductor device for a microcomputer, FIG. 2 is a sectional view of an embodiment of the present invention, and FIG. 3 is an electrical diagram of the embodiment shown in FIG. 2 after writing and erasing. FIG. 1...Input/output section, 2...RAM, 3...ROM, 4...
CPU, 11...N type semiconductor substrate, 12-17...N
Mold region, 18-22... SiO 2 film, 23... Silicon nitride film, 25-28... Electrode, A... Source electrode, B
...Drain electrode, D 1 , D 2 ...Drain electrode, G 1 ,
G 2 , G 2D , G 2S ... gate electrode, M 1 ... first insulated gate type nonvolatile semiconductor memory element, M 2 ... second insulated gate type nonvolatile semiconductor memory element, M 2D , M 2S
...Semiconductor element for selective reading/writing.
Claims (1)
で消去可能な第１の絶縁ゲート型不揮発性半導体
記憶素子と、電気的書込み可能で紫外線照射で消
去されず電気的消去可能な第２の絶縁ゲート型不
揮発性半導体記憶素子とを同一半導体基板に含む
ことを特徴とする半導体装置。1. A first insulated gate nonvolatile semiconductor memory element having a floating gate, electrically writable and erasable with ultraviolet rays, and a second insulated gate that is electrically writable and not erased by ultraviolet irradiation but electrically erasable. 1. A semiconductor device comprising a type nonvolatile semiconductor memory element on the same semiconductor substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56150393A JPS5851568A (en) | 1981-09-22 | 1981-09-22 | Semiconductor device |
| US06/420,028 US4527259A (en) | 1981-09-22 | 1982-09-20 | Semiconductor device having insulated gate type non-volatile semiconductor memory elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56150393A JPS5851568A (en) | 1981-09-22 | 1981-09-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5851568A JPS5851568A (en) | 1983-03-26 |
| JPS6312387B2 true JPS6312387B2 (en) | 1988-03-18 |
Family
ID=15496002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56150393A Granted JPS5851568A (en) | 1981-09-22 | 1981-09-22 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4527259A (en) |
| JP (1) | JPS5851568A (en) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6062162A (en) * | 1983-09-16 | 1985-04-10 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US4652926A (en) * | 1984-04-23 | 1987-03-24 | Massachusetts Institute Of Technology | Solid state imaging technique |
| US4665503A (en) * | 1985-01-15 | 1987-05-12 | Massachusetts Institute Of Technology | Non-volatile memory devices |
| US4780750A (en) * | 1986-01-03 | 1988-10-25 | Sierra Semiconductor Corporation | Electrically alterable non-volatile memory device |
| US4758869A (en) * | 1986-08-29 | 1988-07-19 | Waferscale Integration, Inc. | Nonvolatile floating gate transistor structure |
| US5034786A (en) * | 1986-08-29 | 1991-07-23 | Waferscale Integration, Inc. | Opaque cover for preventing erasure of an EPROM |
| JPS63237580A (en) * | 1987-03-26 | 1988-10-04 | Toshiba Corp | Semiconductor device and manufacture of the same |
| JPH01128472A (en) * | 1987-11-13 | 1989-05-22 | Toshiba Corp | Semiconductor nonvolatile memory |
| JPH021988A (en) * | 1987-12-03 | 1990-01-08 | Texas Instr Inc <Ti> | Electrically programmable memory cell |
| US4957877A (en) * | 1988-11-21 | 1990-09-18 | Intel Corporation | Process for simultaneously fabricating EEPROM cell and flash EPROM cell |
| WO1990015412A1 (en) * | 1989-06-08 | 1990-12-13 | Sierra Semiconductor Corporation | A high reliability non-volatile memory circuit and structure |
| US5153143A (en) * | 1990-02-26 | 1992-10-06 | Delco Electronics Corporation | Method of manufacturing CMOS integrated circuit with EEPROM |
| US5014098A (en) * | 1990-02-26 | 1991-05-07 | Delco Electronic Corporation | CMOS integrated circuit with EEPROM and method of manufacture |
| US5097449A (en) * | 1990-03-15 | 1992-03-17 | Vlsi Technology, Inc. | Non-volatile memory structure |
| JP2755781B2 (en) * | 1990-04-23 | 1998-05-25 | 株式会社東芝 | Semiconductor memory device and method of manufacturing the same |
| JPH05211338A (en) * | 1991-10-09 | 1993-08-20 | Mitsubishi Electric Corp | Non-volatile semiconductor device |
| US6288419B1 (en) | 1999-07-09 | 2001-09-11 | Micron Technology, Inc. | Low resistance gate flash memory |
| US7012296B2 (en) * | 1999-09-17 | 2006-03-14 | Renesas Technology Corp. | Semiconductor integrated circuit |
| US7190023B2 (en) * | 1999-09-17 | 2007-03-13 | Renesas Technology Corp. | Semiconductor integrated circuit having discrete trap type memory cells |
| JP4058219B2 (en) | 1999-09-17 | 2008-03-05 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit |
| US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3916268A (en) * | 1969-01-21 | 1975-10-28 | Gen Electric | Device for storing information and providing an electric readout from a conductor-insulator-semiconductor structure |
| US3924246A (en) * | 1974-05-15 | 1975-12-02 | Isotronics Inc | Ultraviolet-transmitting window |
| US4103312A (en) * | 1977-06-09 | 1978-07-25 | International Business Machines Corporation | Semiconductor memory devices |
-
1981
- 1981-09-22 JP JP56150393A patent/JPS5851568A/en active Granted
-
1982
- 1982-09-20 US US06/420,028 patent/US4527259A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5851568A (en) | 1983-03-26 |
| US4527259A (en) | 1985-07-02 |
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