JPS62107500A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To raise an access speed at the time of a memory is operated and to make unnecessary trimming process required for fuse melting, etc., by chang ing over a preliminary memory with a part of the main memory by a latch circuit. CONSTITUTION:The address of a detected false memory is supplied from an address terminal 30 and stored into a ROM 31. By the supply of an electric power source voltage Vdd, the contents of the ROM 13 are read to an address signal line 32 and a latch control signal line 33. Thus, latches 34, 35 36 in an address decoder 37 and a preliminary decoder 38 are started, the decoder is changed over and the program of the decoder 38 is executed. During the energizing, the changing-over condition is continued, the faulty memory address is inputted at the time of usual operation then, the decoder 38 is started and a preliminarily memory 39 is selected. Consequently, it is not necessary to compare addresses, the access speed is raised and the fuse melting, etc., are not necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device with high performance and high reliability and redundant functions.

Conventional technology The redundancy function of replacing spare memory with a defective part of the main memory is attracting attention as an effective countermeasure for large-capacity semiconductor memories. In general, semiconductor memories with a spare memory switching function are made of polysilicon. It has a fuse for switching the circuit configuration formed by, etc. Normally, this fuse is trimmed during electrical inspection in the sliced state during the manufacturing process, so that spare memory switching information can be stored in each memory chip on the slice. Conventional techniques are mainly divided into two types depending on the method of trimming the fuse. The first trimming method is to blow a polysilicon fuse by passing a current through it, and a conventional example using this method is shown in FIG. During trimming, the address of the defective memory is input from the address input terminal through the address buffer 1, the fuse trimming control circuit 2 is operated, and the fuse 4 corresponding to the address is selected by turning on and off the trimming MOS transistor 3. can be fused. During normal memory operation, the comparator circuit 6 compares the input address and the defective address stored by the fuse, and if they match, the memory selection timing clock is transmitted to the memory selection gate 7 by the clock switching gate 6. Spare memory 8 is selected. If there is a mismatch, the memory selection gate 7 that selects the spare memory 8 does not operate, and the memory selection gate 7 that selects the main memory 9 does not operate the address decoder 1.
is selected corresponding to the output of o.

As a second trimming method, there is a method in which a polysilicon fuse or the like is directly blown out using a laser beam. Conventionally, semiconductor memory devices using this method have connected polysilicon fuses to address decoders 1o and memory selection gates 7.
The internal pressure is such that the circuit can be switched directly using laser light.

Problems to be Solved by the Invention However, these two systems each have their own problems. In the first method, since the area of the MOS transistor 3 for selectively trimming the fuse 4 is large, the chimp area increases when the number of spare memories is increased or when the number of target addresses is large. There are drawbacks that lead to Furthermore, during normal memory operation, extra time is required for address comparison, resulting in a problem of slow access speed. In addition, in the case of the second method, laser trimming generally needs to be performed independently of the electrical inspection in the sliced state, and furthermore, the defective address data collected during the electrical inspection is used as the position data of the trimming point in the slice. The drawback is that the manufacturing process is extremely complicated since it is not necessary to correspond to each of the above chips. Furthermore, problems 1 to 1 common to the conventional examples of the above two systems include damage to devices near the fuse when the fuse is blown, and damage to reliability due to destruction of the surface protective film, etc.

Conventional semiconductor memories having a spare memory and a switching function have respective drawbacks as explained in the above two conventional examples. The present invention aims to solve the following three problems including these problems. First, it has a function that allows online switching of spare memory during electrical inspection, regardless of whether it is in a sliced state or in a sealed package state. Second, the spare memory switching circuit does not cause any inconvenience in terms of operating speed or other characteristics of a semiconductor memory. Thirdly, there are no problems such as deterioration of reliability.

Means for Solving the Problems The present invention provides a main memory and a spare memory forming a redundant circuit, a non-volatile memory constructed of semiconductor non-volatile memory transistors on the same substrate, and a signal output from the non-volatile memory. The operation is set according to the
Further, the semiconductor memory device has a latch circuit having a circuit switching function for replacing a part of the main memory with the spare memory.

According to the present invention, the spare memory is selected by the function of the latch circuit and used as a part of the main memory.
The high-speed operation characteristics of the memory function can be used without any loss. Further, the semiconductor memory device of the present invention is effective in simplifying the structure as in the conventional example.

Embodiment In one embodiment of the present invention, the transistor is an N-channel MOS type transistor, and the nonvolatile transistor is:
Although the case where an N-channel MNO3 type transistor is used will be described in detail, there is no difference in the effect 1 function even if a transistor of other conductivity type or a nonvolatile transistor is used.

An example is shown in FIG. The address of the defective main memory detected by electrical inspection during the manufacturing process is supplied from the address terminal 30, and the non-volatile memory I731K memory 1
Keep it at 7. During normal use, the contents of the nonvolatile memory are automatically transferred to the address signal line 3 immediately after supplying the power supply voltage Vdd.
2 and the latch control signal line 33. As a result, the latches 34, 36, and 36 built in the address decoder 37 and the spare decoder 38 are activated, and the decoder corresponding to the defective main memory address is disconnected and the program of the spare decoder 38 is executed. 1 child F with no trace of electricity
] The state of changing address decoder i'' is maintained, and in normal memory operation, when a defective memory address is input, the spare decoder 38 is activated and the spare memory 39 is selected. be done.

The circuit operation will be explained in detail step by step. When programming a defective address, a negative voltage VPI is applied from the program control auxiliary terminal 41 to the gates of the MNO8 type transistors 42 and 43 to put the MNO8 type transistors into an erased state. Next, a defective address code is inputted from the address input terminal, and is supplied to the gate of the MOS transistor 45 in the nonvolatile memory 31 through the address buffer 44.

At this time, a positive voltage VPW is applied to the program control auxiliary terminal 41.
By applying MOS transistor(s) 46
is turned on, and at this time, if the MOS transistor 46 connected in series with these transistors is on, the channel potential of the MNO8 type transistor 42 is Vss (circuit reference voltage).
level, and vPw is applied between the gate and channel, resulting in a write state. When the MOS transistor 45 is off, the voltage between the gate and channel is Vpw.
Since V and B are applied, writing is not performed and the erased state is maintained. If VPW is applied to the program control auxiliary terminal 41, the MNO3 type transistor 43 becomes unconditionally in the write state. The MOS transistor 47 in this operating state has a load function. As described above, the MNO5 type transistor 42 is programmed in accordance with the address, and information as to whether the programming operation has been performed is stored in the MNO5 type transistor 43. The programmed information is fixed in this semiconductor memory as non-volatile data. These fixed information are read by setting the address read control signal line 61 to a high level for a certain period of time determined by the resistor 49 and capacitor 60 at the same time that the power supply voltage VDD is supplied to the semiconductor memory. It will be done. At this time, the program control auxiliary terminal 41 is fixed at the VSS level by the resistor 48, the MNO3 type transistor in the erased state is on, and the one in the written state is off. While the address read control signal line 61 is at high level, the MOS transistors 52 and 64
is turned on, and the MNO
The state of type 3 transistors 42 and 43 is the address signal line 3.
2. It is output to the latch control line 33.

If writing is being performed, the programmed address is output to the address signal line 32 and a high level is output to the latch control line 33. If programming is not being performed, the address signal line 32 and latch control line 33 are all low level. becomes. When the latch control line 33 is at a high level, latches 34, 36, and 36 provided in the address decoder 37 and the spare decoder 38 are set as necessary.

These latches 34, 35, and 36 are automatically reset at the moment of energization, and are set when a high level is input to the input (S) terminal even momentarily thereafter, and a higher level than the true value output terminal Q is set. This is a general latch circuit in which a low level is output from the complement output terminal Q. If an address code for selecting the address decoder 37 is supplied to the address signal line 32, the output of the initial low level 37 at the Q terminal of the latch 34 becomes high level (level). A high level is supplied to the latch control line 33, the output of the AND gate 66 becomes high level, and the latch 34 is set.

Since a high level is output from the Q terminal of this latch 34, the output of this address decoder 37 is always fixed at a low level, and the address decoder 37 will no longer be able to select the main memory. On the other hand, the auxiliary decoder 38 simultaneously receives signals from the address signal line 32 and the latch control line 33, and switches internal latches, thereby being configured as a decoder that takes over for the address decoder 37. The spare decoder 38 is provided with a plurality of latches corresponding to the number of address lines, one for each pair of address signal line inputs n and signal lines An having a negative phase relationship, and further uses a spare decoder. A latch 35 is built in to store whether or not to do so. Assuming that the negative phase signal line ^n is at high level and the signal line An is at low level, the latch 36 is set and the ant game 1 to which the signal line input n is input is quasi-i. If the 9 gates are closed, it is equivalent to the negative phase signal line ^n signal not being supplied. By selecting one of all address line pairs supplied in this manner, an address decoder having the same contents as address decoder 3 is constructed. When the spare decoder 38 is not used, the latch control line 33 is at a low level, the latch 35 remains in the initial reset state, and a high level is output from the terminal, so the output of the spare decoder 38 is fixed at a low level. The address decoder and spare decoder programmed as described above do not require any special operations such as address comparison described in the conventional example when operating this semiconductor memory, so the address decoder and spare decoder programmed as described above do not require any special operations such as address comparison described in the conventional example, There is no adverse effect on the circuit speed from when a memory is selected by the address decoder until its contents are outputted to the data output terminal through the data input/output control S5 and the output sofa 57. Naturally, the same thing can be said about writing data into the memory from the data input terminal 59.

Since programming the non-volatile memory is completely controlled electrically, it can be performed simultaneously with the electrical inspection based on the sliced state in the final diffusion process. Further, if the program control auxiliary terminal 41 is taken out as a terminal of the package, the program can be introduced into the inspection process at the time of shipment, which is the final stage of the manufacturing process.

Executing an electrical program on nonvolatile memory does not cause any physical or chemical damage to this semiconductor memory, and in particular does not cause any damage to the surface protective film that serves to prevent contaminants from entering from the outside. It does not affect its functionality.

FIG. 2 shows the dependence of the drain current (In) on the gate voltage (VG) of the MNOS transistor used in the example. Reference numeral 20 in FIG. 2 indicates the characteristics after a predetermined negative voltage (VPI) is applied to the gate of the MNOS transistor with respect to the substrate. 21 is the characteristic after applying a predetermined positive voltage (VPW) to the gate with respect to the channel. The former shows the characteristics of an MNOS type transistor in an erased state, and the threshold voltage shows a negative value. The latter exhibits write state characteristics and has a threshold voltage higher than that of a normal enhancement type MoS transistor.

An MNOS type transistor is an ordinary MOS (Metal) transistor in which the gate oxide film part of the transistor is formed of a thin oxide film (Si02) and a nitride film (5i5N4).
-N(N1tr:Lde) -0(0w1de)
-3 (Sem1conductor) structure semiconductor device, which exhibits the above-mentioned threshold voltage change by transferring charges into and out of traps existing at the interface between the nitride film and the oxide film, and the trapped charges do not leak. As long as the characteristics do not change, it has practically semi-permanent retention characteristics.

Effects of the Invention The effects of the present invention can be found in the points described below. First, the circuit of the present invention, which switches and uses spare memory, is suitable for high-speed operation and is effective against gender differences in speed, such as access time, in semiconductor memories.
- Second, programming of defective memory addresses can be executed at the same time as normal electrical inspection, and it can also be programmed while sealed in a package, so there is a high degree of freedom, and the programming process is significantly shorter than before. [It can be rationalized.

Third, compared to conventional fuse trimming methods such as blowing out polysilicon fuses, it is possible to realize a semiconductor memory device of superior reliability and high quality.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a characteristic diagram of an MNOS type transistor, and FIG. 3 is a circuit configuration diagram of a conventional device. 1... Address buffer, 2... Fuse trimming control, 3... MOS transistor, 4... Trimming fuse, 5...
...Address comparison, 6...Clock switching gate, 7...Memory selection gate, 8...
...Spare memory, 9...Main memory, 1o...
...Address decoder, 11...Data input/output control, 12...Output Hanofa, 13
......Input cover, 20...Characteristic line of MNO8 type transistor in erased state, 21...
Characteristic line of MNO3 type transistor in write state, 3o
...Address terminal, 31...Nonvolatile memory, 32...Address signal line, 33...
... Latch control line, 34, 36° 36 ... Latch, 37 ... Address decoder, 38 ...
...Spare decoder, 39 ...Spare memory, 4
0...Main memory, 41...Program control auxiliary terminal, 42.43...MNO5 type transistor, 44...Address buffer, 45,
48.47...MOS transistor, 48.4
9...Resistor, 50...Capacitor, 5
1... Address read control signal line, 52, 5
3.54...MOS transistor, 55...
...Data input/output control, 56...
Incoming Kahanofa, 57... Outgoing Kahanofa, 68.
...Data output terminal, 69...Data input terminal O Name of agent Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3

Claims (1)

[Claims] a main memory and a spare memory forming a redundant circuit on the same substrate, a nonvolatile memory configured by semiconductor nonvolatile memory transistors, and an operation set in response to a signal output from the nonvolatile memory;
A semiconductor memory device comprising a latch circuit having a circuit switching function for replacing a part of the main memory with the spare memory.