JPS6237753A - Control system for buffer memory - Google Patents

Abstract

PURPOSE:To avoid the deterioration in efficiency due to a replacement by carrying out an access for the retrieval of an address conversion table word when the PTW is registered to a TLB as well as the registration of said table word only with a cache memory for instructions. CONSTITUTION:An instruction buffer memory part 1 contains an instruction cache 2 and an instruction TLB 3. An operand buffer memory part 4 contains an operand TLB 6. A control part 7 retrieves both TLB 3 and 6 to obtain a real address. However the part 7 gives an access to a real memory to obtain an address conversion table and then starts a paging part 8 to obtain a real page address in case the retrieval of the TLB fails. The part 8 uses the cache 2 to perform the real memory access for the retrieval of the address conversion table word and registers the address conversion word to a cache memory with the cache 2 only. Thus it is possible to avoid the deterioration of the using efficiency of the buffer memory due to the replacement caused by the irregularity of addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a control method for a buffer memory in an information processing device, and relates to a method for controlling a buffer memory in an information processing device.
(ookasideBuffer) This relates to a control method for indexing and registering address translation table words in the event of a mistake.

Conventional technology Conventionally, when a TLB miss occurs, the paging unit performs a 7-etch of the address translation table word directly from the memory without using a cache, or the address translation table 7-word of the instruction is The address translation table load of the operand is indexed and registered for the cache for ``Obera〉'1, the character for use...''U), and is solved by the t-6 invention 1. Among the conventional methods mentioned above, when TLB misses -21-
6. The method of indexing and registering the address translation table word in the memory, -1゛Access time is shorter than when the translation table word is in the cache. It means it's long.

Next, the disadvantage of the method of having address translation table words in the cache, that is, indexing and registering the TLB miss in the operand cache when it is an operand, and the instruction cache when it is an instruction, is that the operand is In many cases, the word length is longer than that of an instruction, and because the words are scattered, the address translation table word is quickly replaced if the operands are not registered in the cache.

This method also has the disadvantage that the same address translation table word is registered in both the operand cache and the instruction cache, reducing cache usage efficiency.

The present invention has been made in view of the above-mentioned conventional circumstances,
It is therefore an object of the present invention to eliminate the above-mentioned disadvantages inherent in the tlE technology.

Means for Solving the Problems In order to achieve the above object, the buffer memory control method according to the present invention includes an operand buffer memory section consisting of an operand cache TLB, and an instruction cache section consisting of an instruction cache and TLB. a buffer memory section, a paging section that indexes the address translation table word only in the instruction cache in the event of a miss when indexing the TLB for address translation; the operand buffer memory section; and the instruction buffer memory section. and a control section that controls the paging section and performs the registration only on the instruction cache when registering address translation table words.

Embodiment Next, a preferred embodiment of the present invention will be comprehensively explained with reference to the drawings and in comparison with a conventional example.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which only the instruction buffer memory section has an interface for indexing and registering address translation table words. FIG. 2 is a block diagram showing a conventional device for an embodiment of the present invention, in which an interface for indexing and registering address translation table words is provided for the instruction buffer memory section and the operand buffer memory section. There is. This is because the indexing and registration of each address translation table word for instructions and operands is performed for each buffer memory.

In FIGS. 1 and 2, reference numbers 1 and 8 respectively indicate a buffer memory section for instructions, a buffer memory section 4 for operands, a control section 7, and a paging section 8. The instruction buffer memory section l includes an instruction cache 2 and an instruction TLB.
3, and the operand buffer memory section 4 has an operand cache 5 and an operand TLB 6. 9 is an interface between the instruction buffer memory section 1 and the control section 7, IO is an interface between the instruction buffer memory section 1 and the paging section 8, 11 is an interface between the control section 7 and the paging section 8, and 12 is a control section. 13 is an interface between the operand buffer memo 9 section 4 and the control section 7; 14H is an interface between the operand buffer memory section 4 and the paging section 8; In FIGS. 1 and 2, only the interfaces related to indexing and registration of address translation table words are shown.

The control unit 7 has a function of activating the paging unit 8 using a TIJB miss report, and a function of loading a block of data from the main memory to the corresponding cache upon receiving a cache miss report. The control unit 7 uses the interface 9 for the island stand where address conversion is performed, and the TLB 3.6
(3 is the TLB for instructions, 6 is the TLB for operands) to obtain the real address. However, if there is a mistake in indexing the TLB, access the real memory and access the address translation table to obtain the real page address. Activate the paging section 8.

The paging unit 8 performs a series of address conversions as shown in FIG. PJ)BkL (Page left base register) i P'J:D This is an address indicating the starting location of the (page table directory), and is owned by the paging section itself. Basing part 8, PI) BR
P'L'DW (page table directory word) address 3 is obtained by adding the effective virtual space number to , and the instruction cache 2 in the instruction buffer memory section l is indexed using the interface lO to obtain PTIJw. P.T.
DW HPT This is an address indicating the starting address of the page table. The p'rw (page table word) address is obtained by adding the page number to the p'rw (page table word) address in the p'rw (page table word) address in the p'rw (page table word) address in the p'rw (page table word) address in the p'rw (page table word) address in the p'rw (page table word) address.
Get TW. The control unit 7 adds the intra-page relative address to this P'IW to obtain a real memory address, and the address conversion ends. If the paging section 8 accesses the instruction cache memory 2 to obtain the PTDW 6 or PTW and misses, it accesses the king memory through the control section 7 and the interface 12 and retrieves the missed PTD.
The apron including DW4 or P'l'W is block loaded and registered in the instruction cache 2 in the instruction buffer memory l using the interface 9. It is better to have as few cache misses as possible at this time. This is because the access time to the cache memory n
Since the access time to the MoIJ is very fast, when the paging section accesses the instruction cache memory, there is a high probability of a hit and the address translation can be performed more quickly.

Here, we will explain why it is good to access the instruction cache memory. In the operand cache memory, operands are longer than instructions and have more branches, so there is a high possibility that the registered PTDW 5PTW will be replaced soon. For this,
The power of instructions is continuous on the king memory, and the replacement frequency is less than that of operands, so if all PTDWs or PTWs are PTDW4 or PTW when block loading, there is a possibility that all of them will be hinted. Therefore, it can be seen that it is efficient to register and index PT'DW and PTW (both address translation table words) in the cache memory only for the instruction cache memory.

As described in detail, according to the present invention, address irregularities that tend to occur in operand buffers are avoided by indexing and registering address translation table words PTDW and PTW only in the instruction buffer memory. The effect is that the inefficiency of use due to replacement due to the nature of the data is avoided, and the stored PTDW and PTW blocks are made more effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
Figure 3 is a block diagram showing a conventional device for the present invention.
The figure shows the process of address translation performed by the paging section 8 when a TLB error occurs. 1--Buffer memory for instructions, 2... Cache for instructions, 3--TLB for -O instructions, 4-- Buffer memory for operands, 5-- Cache for ``fist/life'' operands, 6... TLB 17 for operands. ...Control unit, 8@...Basing unit, 9.Fist/instruction buffer memory - interface between control unit, 10...Instruction buffer memory inter-bathing unit interface,
1lII...Interface between control unit and paging unit,
1211...Control unit-King memory interface, 13
---Operand buffer/-a IJ~Nil
fllll Inter-section interface, 14... - Operand buffer memory ~ Paging section interface Patent applicant: NEC Corporation Representative Patent attorney: Yutabe Kumagai

Claims (1)

[Claims] There is an operand buffer memory section consisting of an operand cache and TLB, an instruction buffer memory section consisting of an instruction cache and TLB, and when there is a miss when indexing the TLB, the real memory is accessed and the address translation table word is indexed. And the resulting PTW is TL
In an information processing system, the operand buffer memory section and the instruction buffer memory section each have an address. When the paging unit is requested to register the PTW in the TLB due to a miss while indexing the TLB for conversion, the instruction cache memory is used for real memory access from the paging unit to index the address translation table word. The buffer memory control method is characterized in that address translation table words are registered in the cache memory only in the instruction cache memory.