JP2502811B2 - Physical cache device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache device capable of effectively speeding up memory access in a computer system, and more particularly to a physical cache device for retrieving data using a physical address.

[0002]

2. Description of the Related Art In recent years, in order to execute instructions in a computer system at high speed, some of instructions and data in a memory are placed in a cache device realized by a high-speed device to accelerate effective memory access. Has been done.
The cache device can be roughly classified into a logical cache and a physical cache depending on whether a logical address or a physical address is used as an address tag for determining a cache hit / miss. Particularly in the physical cache, there is a problem that an address conversion overhead occurs because the physical address is used for the cache search. As a conventional physical cache device that solves this problem, for example, "Architecture, of the N.S. 325.
32. Microprocessors "Di Alpert, Jay Levy, Bee Maytal, Ai. Triple E. International. Conference. on. Computer.
Design, 1987, pp. 168-172 ("Archit
ect ure of the NS32532 Microprocessor ”, D. Alper
t, J. Levy, B. Matal, IEEE International Conferenc
e Computer Design 1987, pp. 168-172).

In this physical cache device, a direct map method is adopted, and an index for performing a cache search is placed within a page where a physical address and a logical address match, so that cache search and address conversion are performed in parallel. The address conversion overhead is reduced.

[0004]

However, the above configuration has a problem that a cache device having a capacity larger than the page size cannot be realized.

In view of the above problems, it is an object of the present invention to provide a physical cache device which can be accessed at high speed and has no limitation in cache capacity.

[0006]

In order to achieve the above object of the present invention, a physical cache device of the present invention comprises a cache which uses a physical address as tag information and a first physical page number which converts a logical page number into a physical page number. Address translation means; second address translation means for translating a portion of the index designated across the page boundary that overlaps the address translation target address into a physical address index; and a portion that does not overlap the address translation target address of the index and the second An entry search unit for searching a cache entry by the physical address index converted by the address conversion unit, and the physical address converted by the first address conversion unit and the physical address index and entry converted by the second address conversion unit Tag of the entry searched by the search means By comparing the information and has a determination means for determining a cache hit / miss.

[0007]

In the physical cache device of the present invention having the above-mentioned structure, the address conversion by the first address conversion means and the second address conversion means, and the cache by the entry search means utilizing the part of the index which is not the target of the address conversion are carried out. Searching at the same time. As a result, the address conversion overhead is eliminated and the cache capacity is not limited.

[0008]

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of a physical cache device according to a first embodiment of the present invention. As shown in FIG. 1, as a component, 1 is an address translation table (hereinafter referred to as TLB) that performs address translation as a first address translation unit, and 2 is a direct method cache having a physical address as tag information and an entry search unit. Built-in.
Reference numeral 3 is an index converting unit as second address converting means, 4 and 5 are comparators as determining means, and 6 is an AND gate which takes a logical sum and constitutes a part of the determining means.

With respect to the present embodiment configured as described above, the related operations of the constituent elements will be described below. In this embodiment, a paging type virtual memory system having a page size of 4 KB is assumed. The TLB 1 converts the upper 20-bit logical address VA (0:19) of the logical address into the 20-bit physical address PA (0:19). Since the page size is 4 KB, the lower 12-bit logical address VA (20:31) of the logical address and the lower 12-bit physical address PA (20:31) of the physical address are the same. The cache 2 is a physical cache having a line size of 32 bytes and a total number of lines of 256 and a capacity of 8 KB. The index conversion unit 3 has the same number of entries as the total number of lines in the cache 2, and each entry holds the tag information PTAG19 corresponding to the physical address PA19.

The cache access operation will be described below. When the logical address VA (0:31) is given, the higher logical address VA (0:19) is input to the TLB1 for conversion into a physical address. At the same time, a logical address VA (19:26) is used to perform a cache search.
8 bits of are also input to the cache side. The entry of the index conversion unit 4 is determined by the 8 bits of the logical address VA (19:26) and the corresponding tag information PTA is determined.
G19 is obtained. This tag information PTAG19 and 7 of the logical address VA (20:26) that is not the address conversion target
The entry conversion means determines the cache entry of the cache 2 with 8 bits including the bits. TLB
1. The physical address PA (0:19) obtained from 1 and the tag information PTAG (0:18) of the entry determined and the tag information PTAG 19 obtained from the index conversion unit 3
A cache hit / miss hit can be determined by comparing with. That is, the comparator 5 compares the physical address PA19 and the tag information PTAG19 with the physical address PA19.
(0:18) and the tag information PTAG (0:18) are compared by the comparator 4, and the output of each comparator is AND gate 6
Hit / miss is determined by taking the logical sum with. If there is a hit, the latch 9 is turned through and data is obtained. If it is a mishit, entry place is performed as in a normal physical cache. At this time, the corresponding entry of the index conversion unit 3 also has the physical address PA19.
Update with. With the above-described operation, the cache entry can be searched with a small overhead of pulling the index conversion unit 3, and a direct map type physical cache having a capacity larger than the size of the virtual storage page can be realized.

(Second Embodiment) FIG. 2 is a block diagram showing the configuration of a physical cache device according to a second embodiment of the present invention. As shown in FIG. 2, components having the same functions as those in FIG. 1 are designated by the same reference numerals to show their components. Reference numeral 1 is a TLB that performs address conversion as address conversion means, 4 is a comparator as determination means, 7 and 8 are selectors as selection means, 9 is a latch, and 22 is a direct method cache composed of a plurality of caches. Similar to the one embodiment, it incorporates an entry search means.

The operation of the present embodiment configured as described above will be described below. In this embodiment, a paging type virtual memory system having a page size of 4 KB is assumed. The TLB 1 converts the upper 20-bit logical address VA (0:19) of the logical address into the 20-bit physical address PA (0:19). Since the page size is 4 KB, the lower 12-bit logical address V of the logical address
A (20:31) and the lower 12-bit physical address PA (20:31) of the physical address are the same. The cache 22 is a physical cache having a line size of 32 bytes and a total number of lines of 256 and a capacity of 8 KB, and has a two-sided structure of 128 lines. An entry is simultaneously selected for each surface by 7 bits of the logical address VA (20:26) which is not translated.

The cache access operation will be described below. When the logical address VA (0:31) is given, the higher logical address VA (0:19) is input to the TLB1 for conversion into a physical address. At the same time, a logical address VA (19:26) is used to perform a cache search.
8 bits of are also input to the cache side. Logical address VA (20:26) for 2 sides of each 128 entries
The entry determined by the 7 bits is simultaneously determined, and the tag information of each surface is output to the selector 8 and the data information is output to the selector 7. At this time, the logical address VA19 which is the address conversion part of the index is not used.

The physical address PA19 obtained by the address conversion by the TLB1 determines one of the two candidates output from the two faces of the cache 22 to the selectors 7 and 8. At this stage, the cache entry is decided. By comparing the physical address PA (0:18) of the physical addresses obtained from the TLB1 with the tag information PTAG (0:18) of the determined entry, cache hit / miss hit can be determined. If there is a hit, the latch 9 is turned through and data is obtained. If it is a mishit, entry replacement is performed as in a normal physical cache. However, the entry replacement is performed only on one of the two faces of the cache 22 which is determined by the PA 19.

With the above-described operation, candidates are narrowed down in advance by using the selector, and the use of the physical address is delayed as much as possible, whereby cache entry search without causing address translation overhead can be performed, and the virtual memory can be stored. A direct map type physical cache with a capacity larger than the page size can be realized.

(Third Embodiment) FIG. 3 is a block diagram showing the arrangement of a physical cache device according to the third embodiment of the present invention. As shown in FIG. 3, components having the same functions as those of the first and second embodiments are designated by the same reference numerals. Reference numeral 1 is a TLB that performs address translation as first address translation means, 3 is an index translation unit that performs address translation as second address translation means, and 4, 5
Is a comparator, 6 is an AND gate, and comparators 4, 5 and AN
The D gate 6 constitutes the judging means. The selectors 7, 9 are latches, and 22 is a direct method cache as selecting means.

With regard to the present embodiment configured as described above, the related operations of the constituent elements will be described below. In this embodiment, a paging type virtual memory system having a page size of 4 KB is assumed. The TLB 1 converts the upper 20-bit logical address VA (0:19) of the logical address into the 20-bit physical address PA (0:19). Since the page size is 4 KB, the lower 12-bit logical address VA (20:31) of the logical address and the lower 12-bit physical address PA (20:31) of the physical address are the same. The cache 22 is a physical cache having a line size of 32 bytes and a total number of lines of 256 and a capacity of 8 KB.
It has a two-sided structure of 8 lines. Each surface has a logical address VA (20: 2) that is not translated.
Entries are simultaneously selected by 7 bits of 6). The index conversion unit 3 has the same number of entries as the total number of lines in the cache 22, and holds the tag information PTAG19 corresponding to the physical address PA19 in each entry.

The cache access operation will be described below. When the logical address VA (0:31) is given, the higher logical address VA (0:19) is input to the TLB1 for conversion into a physical address. At the same time, a logical address VA (19:26) is used to perform a cache search.
8 bits of are also input to the cache side. Logical address VA (20:26) for 2 sides of each 128 entries
The entry determined by the 7 bits is simultaneously determined, and the tag information of each surface is output to the selector 8 and the data information is output to the selector 7.

On the other hand, at the same time, the logical address VA (19: 2
The entry of the index conversion unit 4 is determined by 8 bits of 6) and the corresponding tag information PTAG 19 is obtained.
This tag information PTAG 19 determines one of the two candidates output from the two faces of the cache 22 to the selectors 7 and 8. At this stage, the cache entry is decided. The physical address PA (0:19) obtained from the TLB 1 and the tag information PTAG (0:18) of the entry determined and the index conversion unit 3
Cache hit / miss hit can be determined by comparing with the tag information PTAG19 obtained from.
That is, the physical address PA19 and the tag information PTAG1
9 by the comparator 5, the physical address PA (0:18) and the tag information PTAG (0:18) are compared by the comparator 4, and the output of each comparator is ORed by the AND gate 6, Determine hit / miss. If there is a hit, the latch 9 is turned through and data is obtained. If it is a mishit, entry replacement is performed as in a normal physical cache. However, the entry replacement is performed on the physical address P of the two faces of the cache 22.
There is only one face determined by A19. At this time, the corresponding entry of the index conversion unit 3 is also updated with the physical address PA19.

By the above-mentioned operation, the cache entry can be searched without waiting for the address translation, and the direct map type physical cache having a capacity larger than the size of the virtual memory page can be realized. Although the direct map cache has been described through the first to third embodiments, the method of reducing the address translation overhead in the present invention is also effective in other cache configuration methods such as the set associative method.

[0021]

As is apparent from the above description, the physical cache device of the present invention is provided with the first and second address translation means and the entry search means, and performs the address translation and the cache search at the same time to obtain the cache capacity. It is possible to realize a physical cache without the overhead of address translation without giving any restrictions to the above, and its practical effect is great in high-speed access and improvement in operability.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a physical cache device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a physical cache device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a physical cache device according to a third embodiment of the present invention.

[Explanation of symbols]

 1 TLB 2 cache 3 index conversion unit 4,5 comparator 6 AND gate 7 and 8 selector

Claims (2)

(57) [Claims] 1. A cache using a physical address as tag information, a first address converting means for converting a logical page number into a physical page number, and a portion overlapping an address conversion target address of an index designated across a page boundary. Second address conversion means for converting to a physical address index, and entry search means for searching a cache entry by a portion of the index that does not overlap the address conversion target address and the physical address index converted by the second address conversion means A cache hit by comparing the physical address translated by the first address translation unit with the physical address index translated by the second address translation unit and the tag information of the entry retrieved by the entry retrieval unit. / Judgment hand to judge miss hit A physical cache device having stages. 2. A plurality of caches having a physical address as tag information, a first address conversion means for converting a logical page number into a physical page number, and an address conversion target address of an index designated across a page boundary. Second address conversion means for converting a portion into a physical address index, entry search means for searching a cache entry by a portion that does not overlap the address conversion target address of the index, and physical address obtained by the second address conversion means Selection means for selecting one from a plurality of caches by an index, the physical address converted by the first address conversion means, the physical address index converted by the second address conversion means, and the entry search means. Via the selection means A physical cache device having a judging unit for judging cache hit / miss hit by comparing with tag information of a selected entry.