JPS6237739A - Sorting processor - Google Patents

Abstract

PURPOSE:To apply both ordinal descending and ascending sorting processes, and to attain both ordinal descending and ascending multi-key sorting processes to each of plural keys by performing the control to decide the need for inversion of bits via a bit inverting means. CONSTITUTION:The input information supplied from an input data terminal 13 via a bit inverting circuit 10 is stored in a register A, etc. of a unit 6 of a descending sorting processor 15. Then this input information is compared with the advance information stored in a register 9 from a memory 2 by a comparator 3. Then a switching circuit 7 is controlled according to the contents of a flag register 4 which are set by the result of comparison of the comparator 3. The contents of a register 8 or the register 9 are transferred to the unit 6 at the next stage to undergo the ascending sorting process. The control signal applied to an inverse control terminal 11 is inverted to '1' from '0' through an exclusive OR gate of the circuit 10. Thus the input bit given through an input data terminal is also inverted. In the same way, the processor 15 performs a ascending sorting process. Thus both descending and ascending sorting processes are possible. Furthermore the multi-key sorting process is possible in both ordinal descending and ascending ways to each key if the multi-key control is applied to the circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a sort processing device for character strings and numerical data, and in particular, sorting target data for each other and for multiple areas within the data in ascending order or The present invention relates to a configuration of a sort processing device that sorts in descending order.

(2) Conventional techniques and their problems Sorting is a process of rearranging a given set of data in a predetermined order. Sorting processing in electronic computers means that data given as numerical values or character strings is
Since the computer internally represents the binary code of "0" or "1", given data is compared with each other based on the numerical meaning of the binary code, and the magnitude relationship of each data is determined. This is to rearrange data in ascending order (from smallest to largest) or descending order (from largest to smallest).

Generally, the data to be sorted is called record 1:
A record can be divided into a portion where data is compared to determine the size relationship and a portion where no comparison is performed. If this record is limited to character strings or positive integers (unsigned integers), by comparing the key part of the record expressed in binary code with the tenth digit having an advantage, It is possible to determine the size relationship between records to be sorted.

Even if it is something other than a character string or a positive integer, such as a real number, it can be converted into a character string or a positive integer by an appropriate conversion process without impairing the magnitude relationship.

Conventionally, such sorting processing was performed using a memory device (memory).
When executed on a general-purpose computer with a central processing unit (CPU) as the core, data transfer between memory and CPU and comparison within the CPU are sequential processes, and data transfer between two data at a time. Due to reasons such as only being able to compare
If the number of records to be sorted is large,
There was a problem in that the time required for processing was extremely long.

As a conventional technique for solving the problem regarding the sorting processing time, there is a method in which a dedicated sorting processing device is used to compare the data to determine the size relationship and to transfer the data in parallel to increase the speed. Patent application 1988-188
It is known from No. 368 and Special No. 19n Sho 59-163519.

FIG. 1 is a configuration diagram of a sorting processing device that is an example of the prior art. This device includes a first memory 1 and a second memory 2 for holding data to be compared, and a comparator 3.
, a unit 6 consisting of a flag register 4 and an input/output circuit 5 for holding the determination result obtained by the ratio ratio unit 3? It has a configuration in which several jj are connected in one-dimensional cascade. In this apparatus, mutual comparison and transfer of data can be performed simultaneously in a plurality of units.1 According to the operating principle described below, sorting processing can be performed in a time proportional to the number of records.

FIG. 2 is a diagram showing the principle of operation of the sort processing device shown in FIG. 1. As an example, among numerical data of digits from "0" to "9", r3J, r6J, r5J.

The operation is shown when six records, r2j, r4J, and rlJ, are sorted in descending order. In FIG. 2, only the first memory 1, second memory 2, and flag register 4 in FIG. 1 are simply shown, and other circuits are omitted.

In performing the sorting process, this apparatus first initializes the contents of the first memory 1 and the second memory 2 of all units. This is an example of sorting in descending order, and in this case, "0", which is the minimum value of data, is set. This device performs sorting processing using an input operation that inputs records sequentially and an output operation that outputs records sequentially. - times of input operations, each unit transfers data to the right and compares two pieces of data. In this case, the data to be transferred is the smaller of the two data held in the first and second memories. At this time, one record is input to the sort processing device in synchronization with the data transfer, and either the first memory 1 or the second memory 2 of the leftmost unit is emptied by the transfer. to be kept in memory. (Tl to T6) When all six records have been input by repeating this manual operation, the data is sequentially transferred to the adjacent left unit by the output operation. At this time, the data to be transferred is the larger of the two data in the unit, and "0" is input to the rightmost unit. (T7~T12
) As described above, data is input sequentially by repeating the input operation, and by executing the output operation when the data input is completed, records that have been sorted sequentially are retrieved in descending order starting from the maximum value. In the example of the sorting process described here, the sorting process can be performed with the number of input operations and the number of output operations equal to the number of records.

When sorting in ascending order using this conventional sort processing device, as an initial setting, the first memory 1 of all units
and “9” as the maximum value of the data in the second memory 2.
is set, and during input operations, the larger of the two pieces of data compared in each unit is transferred to the right, and during output operations, the smaller of the two pieces of data compared on each unit is transferred to the right. Transfer to the left. Therefore, in the case of descending sorting and ascending sorting, this conventional sort processing device has the problem of changing the initial setting value of each unit and reversing the size of transferred data during input operation and output operation. There was a problem that had to be solved. For this reason, −
The control circuits of the dimensionally connected comparison and transfer units become complicated, leading to problems such as an increase in the circuit scale of the sort processing device and a decrease in the operating speed of the entire device.

(3) Purpose of the Invention The purpose of the present invention is to provide a sort processing device with a structure that allows sorting in either descending or ascending order, and to provide a plurality of keys in a record so as to perform input and output operations. It is an object of the present invention to provide a sort processing device capable of performing multi-key sorting in which each of a plurality of keys is sorted in ascending order or descending order by synchronously controlling bit inverting means.

(4) Structure of the Invention (4-1) Features of the Invention and Differences from the Prior Art The present invention provides a data input/output section of a sort processor with bit inverting means for inverting bits of input or output data under control. The most important feature is that In order to perform descending sort and ascending sort with a conventional sort processing device, −
The control circuit of the -dimensionally connected comparison and transfer unit is complicated because the initial setting values for each of the multiple dimensionally connected units are changed, and the size of the data to be transferred during input and output operations is changed. This is a factor that increases the circuit scale of the sort processing device and limits the operating speed of the entire device.

In the sort processing device based on the present invention, since the unit that performs the comparison transfer processing is limited to either ascending order sorting or descending order sorting, the control becomes more complicated than in the conventional sort processing device. As a result, the amount of circuitry can be reduced and the operating speed can be improved.

Furthermore, conventional sort processing devices sort records with long data length by dividing records into multiple pieces of data and repeating input or output operations on the divided data. By controlling the bit inverting means, multiple keys can be set in a record and the records can be sorted in descending or ascending order for each key, which was almost impossible to achieve with conventional sort processing devices. It has become possible to implement multi-key sorting.

(4-2) Examples Hereinafter, the present invention will be explained in detail with reference to Examples. Third
FIG. 1 is an overall configuration diagram of a sort processing device for explaining the present invention in detail. In this example, in order to sort data with a long record length, the record is divided into multiple pieces of data.
This shows a case where an input operation or an output operation is performed using divided data as a unit. In the figure, 7 is a transfer data switching circuit, 8 is a register A, 9 is a register B, 10 is a bit inversion circuit, 11 is an EXOR gate that takes an exclusive OR,
12 is an inversion control terminal for controlling a bit inversion circuit; 13 and 14 are input terminals and output terminals for data to be sorted; and 15 is a descending sort processor. Switching circuit 7 and registers 8 and 9
form a transfer circuit.

The descending order sort processor 15 has a repeating structure of units 6 that perform data comparison and transfer processing, and is dedicated to descending order sorting. Therefore, when performing sorting in each unit,
Memory A, which is a first memory, and memory B, which is a second memory, are both initialized to all "O"s. Here, all "O" means setting all bits of the memory to the theoretical value "0". At this time, the flag register 4 is also initialized to the theoretical value "O" at the same time.

The input and output operations in this descending sort processor consist of two phases: transfer and comparison. In the transfer phase of the input operation, transfer data from the left is sent to register A or register B. At this time, memory A
Alternatively, the corresponding data in memory B is sent to the right via the switching circuit 7, and data is read from the memory corresponding to register B or register A on the opposite side. In the comparison phase, two pieces of data set in register A and register B are compared, and the values of register A and register B are written to memory A and memory B. After repeating the input operation consisting of the transfer phase and the comparison phase and completing the input of the Lou code,
The comparison result for the code is set in the flag register 4. When the input of the roux code is completed, the next record is input based on the value of the newly set flag register.

Once all records have been input, it's time to perform the output operation. In the transfer phase of the output operation, transfer data from the right direction is set in register A or register B. At this time, the corresponding data in memory A or memory B is sent to the left via the switching circuit 7, and data is read from the memory corresponding to register B or register A on the opposite side. The comparison phase in output operations is the same as in input operations. As described above, during an input operation, each unit controls the switching circuit 7 based on the value of the flag register 4 to transfer the smaller one of register A8 and register B9 to the right. During the output operation, the switching circuit 7 is controlled based on the value of the flag register 4, and the larger one of the registers A and B is transferred to the left in the same way as during the input operation. By repeating these input operations and output operations, results sorted in descending order are obtained.

When performing descending order sorting in the sort processing apparatus according to the embodiment of the present invention shown in FIG. Set to “1”.

The bit inversion circuit 10 applies an EXO to each bit of the transfer data.
The R gate is loaded and inversion/non-inversion control is performed for each bit. FIG. 4 is a diagram showing the input/output relationship of the EXOR gate. Since the output of the EXOR gate is the exclusive OR of two inputs, if one input is used as an inversion control terminal, it is possible to control inversion/non-inversion of the other input terminal.

Since the data to be sorted by this sorting processing device is a character string or a positive integer, by performing bit reversal, it takes the complement of '1''. The magnitude relationship can be reversed. Therefore, after inverting each bit of input data,
By inputting the data to the descending order sorting processor 15 and inverting the bits of the obtained output again, the data can be sorted in ascending order.

Next, in the sort processing device shown in this embodiment, multiple keys are set in the record, and for each of the multiple keys,
Multi-key sorting, which sorts in ascending or descending order, will be explained using a specific example.

FIG. 5 is an example of sorting 4-digit decimal positive integers in descending order of the thousands digit, ascending order of the hundreds digit, and descending order of the tens digit and - digit. In this example, each number is represented by one byte, and input/output operations such as comparison and transfer are performed in units of one byte. The inversion control signal C is synchronized with the input/output operation of each digit, and the thousands digit is a logical value "0", the hundreds digit is a logical value "1", the tens digit is a logical value "0", and the negative digit is a logical value "0". Invert logic value “0” control terminal 1
Give from 2. As a result, in the input record, only the hundredth place is bit-inverted by the bit inverting circuit 10 to become a complement number. In the figure, each digit is expressed in hexadecimal, so by bit reversal, it can be changed to 1 (oooi in binary).
> is E (1110 in binary notation), 2 is D, 3 is C
has been converted to Each record after this inversion processing is input to a descending order sorting processor 15 and sorted in descending order. The obtained result is input again to the bit inversion circuit 10, and only the hundreds digit is inverted based on the inversion control signal C, thereby reproducing the bit pattern of each record. As shown above, multiple areas are set within the data to be sorted by dividing the data to be sorted into multiple parts and controlling the bit inverting means in synchronization with the input or output operation of each of the divided records. Multi-key sorting can be easily performed by sorting each area in ascending or descending order independently of other areas.

In this embodiment, the case is shown in which the descending sort processor 15 and the bit inverting circuit are combined, but even if an ascending sort processor that can only perform ascending sorting is used instead of the descending sort processor, the inversion control signal Ascending/descending sorting and multi-key sorting can be easily performed by reversing the logical value (0, 1) of ``total side''.

(5) Effects of the Invention As explained above with reference to the embodiments, the sort processing device of the present invention has an input/output unit that inputs and outputs records to a sort processor that can sort in either descending order or ascending order. By being equipped with a bit inversion means that inverts data bits under control, it is possible to sort in either descending or ascending order, and by providing multiple keys in a record, it is possible to perform input and output operations. By synchronously controlling the bit inverting means,
The goal is to realize multi-key sorting in which each of multiple keys is sorted in ascending or descending order.

In order to perform descending sort and ascending sort with a conventional sort processing device, it is necessary to change the initial setting values for each of the multiple units connected in the − dimension, and to change the size of the data to be transferred during manual operation and output operation. must be changed. For this reason, the control circuit of the unit becomes complicated, the amount of circuitry of the sort processing device increases, and this becomes a factor that limits the processing speed. In the present invention, since a sorting processor for either descending sorting or ascending sorting is sufficient, there are advantages in that the amount of circuitry in the sorting processing device can be reduced and the processing speed can be improved.

Furthermore, conventional sorting processing devices require complicated circuits.
This has the advantage that multi-key sorting, which has been difficult to achieve, can be achieved with only a small amount of additional circuitry.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional sort processing device, and Figure 2 is a diagram of a conventional sort processing device.
FIG. 3 is a diagram of the configuration of the sorting device which is an embodiment of the present invention, and FIG. 4 is a diagram of the EXOR gate constituting the bit inverting circuit shown in FIG. 3. FIG. 5 is an explanatory diagram of the operation of sorting processing for a plurality of keys by the sorting processing device of FIG. 3. 1... first memory, 2... second memory, 3...
... Comparator, 4... Flag register, 5... Input/output circuit, 6... Unit, 7... Switching circuit,
8...Register A. 9...Register B, 10...Bit inversion circuit, 1
1... EXOR gate, 12... Inversion control terminal,
13... Input data terminal, 14... Output data terminal, 15... Descending sort processor.

Claims (1)

[Claims] (1) A memory that holds two pieces of data, a comparator that determines the magnitude relationship between the data held in the memory, and a comparator that determines the size relationship between the two pieces of data held in the memory. a sorting processor having a one-dimensional array structure of comparison transfer units having at least a transfer circuit for transferring either one of the two data to the right or to the left; In a sort processing device capable of sorting in either ascending order or descending order, the sort processing device is configured to be a sort processing device specified in descending order or ascending order, and data to be sorted is input or output to the sort processing device. The bit reversing means has a function of inverting each bit of the data to be sorted expressed in binary code when performing the sorting process, and the bit reversing means performs the bit reversing operation. A sort processing device characterized in that it is configured to be able to perform sorting in either ascending order or descending order.