JPS6278627A - Sorting processor - Google Patents

Abstract

PURPOSE:To perform the input of data through an end of a sorting processor and the output of data through the other end in parallel with each other, by supplying the record after giving an identifier to a comparison/transfer circuit. CONSTITUTION:A comparison transfer circuit 10 contains a 1-dimensional array of plural comparison/transfer units 6. An identifier adding circuit 11 is provided to the input/output part of the circuit 10 to give an identifier that identifies whether the record to be sorted is supplied from the unit 6 at the most left or right end. Thus the record containing an identifier is supplied to the circuit 10 via the circuit 11. As a result, it is possible to carry out an operation to supply the record to be sorted to the unit 6 at an end, an operation to deliver the sorting result through the unit 6 at the other end and the comparison and the transfer of each unit 6 synchronously with each other.

Description

[Detailed Description of the Invention] [Industry - Field of Application] The present invention relates to a sort processing device for character strings and numerical data, and particularly to a sort processing device having a one-dimensional array structure of a plurality of comparison and transfer units. , relates to the configuration of a data input/output circuit.

[Conventional technology]

Sorting is a process of rearranging a given set of data in a predetermined order. Sorting processing in electronic computers is because data given as numerical values or character strings is expressed inside the computer as a binary code of 110 II or "1", so it is difficult to understand the numerical meaning of the binary code. Compare the given data with each other based on
This is to rearrange the data in H order (order from smallest to largest) or descending order (order from largest to smallest) depending on the size relationship of each data.

Generally, the data to be sorted can be divided into one code and record, and a part in which the data phase 77 is compared to determine the magnitude relationship, and a part in which no comparison is made. If this record is limited to character strings or positive integers (unsigned integers), by comparing the key part of the record expressed in binary code, giving priority to the upper digits, It is possible to determine the size relationship between records to be sorted. Even if it is a real number or the like other than a character string or an IF integer, it can be sorted through appropriate conversion processing without compromising the magnitude relationship, just like a character string or a positive integer.

Conventionally, such sorting processing was performed using a memory device (memory).
When executed on a general-purpose electric rHI computer configured with a central processing unit (cpU) as the core, memory and CP tJ
If the number of records to be sorted is large due to reasons such as data transfer between data transfers, comparisons within the CPU being sequential processing, and the ability to compare only two pieces of data at a time, However, there was a problem in that the time required for processing was extremely long.

As a conventional technique to solve the problem of sort processing time, there is a method that uses a dedicated sort processing device to compare data to determine the size relationship and to transfer data in parallel to increase speed. For example, patent application 1988-188
No. 368.

FIG. 6 is a block diagram of a conventional sorting processing device (hereinafter referred to as a sorter). This sorter has a first memory 1 and a second memory for holding data to be compared.
The memory 2) has a configuration in which a plurality of units 6 each consisting of a comparator 3, a flag register 4 for holding the determination result obtained by the comparator, and an input/output circuit 5 are linearly connected. In this sorter, mutual comparison and transfer of data can be performed simultaneously in multiple units, so that sorting processing can be performed in a time proportional to the number of records according to the operating principle described below.

Fig. 7 is a diagram showing the operating principle of the sorter shown in Fig. 6, in which numerical data of digits 3, 6,
5, 2, 4. ．． This shows the operation when six records of 1 are sorted in descending order. In FIG. 7, only the first memory 1, second memory 2, and flag register 4 in FIG. 6 are simply shown, and other circuits are omitted.

In performing the sorting process, first, the contents of the first memory 1 and the second memory 2 of all units are initialized. This is an example of sorting in descending order.
In this case, 0, which is the minimum value of data, is set as the initial value. This sorter is capable of manually sorting records sequentially.
Sort processing into rows with an output operation that outputs records sequentially. - In each unit, transfer data to the right and compare two pieces of data using input operations. In this case, the data to be transferred is stored in the first and second memories ]2,2
This is the smaller of the two data held in . At this time, one record is input to the sorter in synchronization with the data transfer, and either the first memory 1 or the second memory 2 of the leftmost unit l- is emptied by the transfer. to be kept in memory. (-i"1 to 1゛6) When all six records have been input by repeating this manual operation, the data is sequentially transferred to the adjacent left unit by the output operation. At this time, the data to be transferred is the larger one of the two data in unit 1-,
The rightmost unit 1- is input with O, which is the same value as the initial value. (From 1゛7・~T-1-1 By repeating the input operation, input the data sequentially, and execute the output operation when the data input is completed, the records that have been sorted from 1 to Can be retrieved in descending order.

In the example of the sorting process described here, the sorting process can be performed with the number of input operations and the number of output operations equal to the number of records.

[Problem that the invention seeks to solve]

When sorting in four orders using the sorter shown in Fig. 6, the maximum value of data is set to 9 in the first memory and second memory of all units as an initial setting, and at the time of input operation, Of the two pieces of data compared in each unit, the larger one is transferred to the right, and during output operation, the smaller one of the two pieces of data compared in each unit is transferred to the left. Become. Therefore, in this sorter, there is a problem that the initial values for each unit must be changed between descending sort and 4-order sort 1, and transfer during input and output operations. There was a problem in which the size of the data had to be reversed.

The sorter shown in FIG. 6 can sort up to twice the number of units of records by one sorting process at a transfer rate of the sorter. When sorting a large number of records that exceed twice the number of units, Japanese Patent Application No. 59-163519 discloses a method in which this sorter is repeatedly used to partially sort the records, and then the whole is sorted by a merge operation. has been proposed. [However, if this sorter is used repeatedly, input operations and output operations must be performed sequentially as shown in Figure 7, so the sum of input operation time and output operation time is It becomes necessary. At this time, data 1 is sent from one end of the sorter to which the comparison transfer unit is connected in a one-dimensional array.
Since input/output is being performed, unit 1-, which is far from the end where input/output is being performed, performs comparison and transfer of initial values that are not originally required.

Therefore, in one sorting process, on average, half of the units operate in vain during the processing time, and when performing repeated sorting processes using this sorting processing device, the unit The effective utilization rate of 1~ is approximately 1−/
A problem arises in which the number decreases to 2.

An object of the present invention is to improve the throughput to 1 by synchronizing and parallelizing the data input from one end of the sort processing device and the data output from the other end, so that data can be processed continuously in ascending or descending order. An object of the present invention is to provide a sort processing device for sorting.

[Means and effects for solving the problem] The present invention provides sorting targets from either the leftmost or rightmost unit in the input/output section of a comparison and transfer circuit having a one-dimensional array structure of comparison and transfer units. An identifier material Zi means is provided for providing an identifier for identifying whether a record has been input.

By inputting records to which an identifier has been assigned by the present identifier assigning means to the comparison and transfer circuit, it is possible to manually input the records to be sorted into the unit 1- at one end, and output the sort results from the unit at the other end. , comparison and transfer operations of each unit 1- can be performed synchronously.

Further, the present invention provides a bit reversing means in the input/output section of the saw 1 processing device, and inputs/outputs records to be sorted while controlling the pin 1 reversing means, thereby performing input operations for continuous sort processing. and output operations in parallel, and between successive sort operations, sort 1 in ascending or descending order
The structure is such that one direction can be set arbitrarily.

〔Example〕

FIG. 1 is an overall configuration diagram of a saw processing apparatus for explaining an embodiment of the present invention. In this embodiment, in order to sort data with a long record length, a record is divided into a plurality of pieces of data, and an input operation or an output operation is performed using the divided data as a command. In the figure, 1 to 4 are the same as in FIG. 6, 7 is a transfer data switching circuit, 8 is a register A, 9 is a register B, 10 is a comparison transfer circuit, 11 is an identifier assignment circuit, and 12 is a bit inversion circuit. It is.

The comparison and transfer circuit 10 includes one of the plurality of comparison and transfer units 6.
This circuit has a dimensional array structure and rearranges records by synchronously comparing and transferring records between each comparison and transfer unit. The comparison and transfer unit 6 has a memory A1 and a memory B2 for storing two records inside the unit, and a comparator 3 determines the magnitude relationship between the two stored records, and stores the determination result. Switching port depending on the contents of flag register 4! !
87, it has a function of transferring either one of the two records to the right or to the left based on the size relationship.

FIG. 2(,) shows a specific configuration of the identifier material IT circuit 11. As shown in FIG. In the figure, 13 is the control terminal CI, 14 is the control terminal C2,
15 is an inverter circuit that inverts and outputs the human logic value;
16 is a P-channel 1-transistor configured in the CMO8 circuit, and 17 is also an N-channel transistor. In this circuit, by setting the logical values of the control terminals CI and C2 in combination, the output terminal Y) can be set to high impedance. , can be set to either logical value 0 or 1. FIG. 2(b) shows the relationship between the logical values of the control terminals C1 and C2 and the output terminal I).

FIG. 3(a) shows a specific configuration of the bit inversion circuit 12. In the figure, 18 is an inversion control terminal CA for controlling the pill inversion operation, and 19 is a FOR gate i- which takes an exclusive OR. In this figure, only the inversion circuit for pin 1 is shown, and the switching circuit for realizing bidirectional data transfer is omitted. Data input/output terminal for this circuit - F l'l 1
．． , t o (7) As shown in FIG. 3(b), when the control terminal CΔ has a logic value O, the operation is non-inverted, and when the control terminal CΔ has the logic value 1, the operation is inverted.

Figures 2(a) and 3(a) show the identification r and p circuits and bit inverting circuits provided in the data input/output section at the left end of the saws 1 to 6 shown in Figure 1. Yes, but.

The same applies to the circuit provided in the data input/output section at the right end.6 Next, the operation of the bidirectional sort processing apparatus shown in FIG. 1 will be explained.

FIG. 4 is an example in which three sets of record strings each consisting of six records are successively sorted. In this example, the bit inverting circuit shown in FIG. In the same figure, only the memories of the three units constituting the comparison and transfer circuit 10 and the contents of the memories are schematically shown.
-j circuit 11 and bit inversion circuit 12 are omitted. The record column to be sorted is “5, 3, 2, 9゜1
, 7 II; “6, 4, 8, 2, 7, 3”: ”
4° 3.8, 4, 2.6'', the first and third record strings are sorted in descending order, and the second one-note string of [1] is sorted in ascending order.

(1) Initial state (To): Assuming that the comparison and transfer circuit 10 sorts the records in descending order for the input/output of records from the left end, the explanation of the conventional sorting processing device shown in FIG. As described above, in each unit (3 units) 6, of the two stored records, the smaller record is transferred to the right, and the larger record is transferred to the left. 1 Before performing the sorting process, each unit 1-6
The memory AI and memory B2 are both initialized to A110. In the figure, the content of the name memory indicated by x-y (x+y is an integer) is an identifier where X indicates which end of the comparison/transfer circuit, left or right, the record was input from, and y indicates the value of the record body. ing. In the figure, the identifier and the record body are shown separately for convenience of explanation, but in each unit 6, the identification f- is also included in the record body and comparison and transfer are performed at the same time.

(2) Rightward transfer (Tl to T6): Input the first set of six records. At this time, each input record has an identification -f- indicating that the input is from the left.
, II I 11. Therefore, the first input record, 5, is displayed as "l-5". The records input to the comparison and transfer circuit 10 are compared in each unit 6.
Transfer the smaller one to the right. The state in which input of the first set of record strings is completed is r6.

(3) Left direction transfer (r7 to 'I'12): When the input from the left direction is completed f, transfer is made to the left direction ti. At this time, each unit 1-6 compares two records,
Transfer the larger record to the left. With this operation, the first set of 1 noni I from the left end of the comparison and transfer circuit 10 is
- Sort and output the record strings in descending order, and sequentially input the second set of record strings from the right end. The record manually entered from the right end has the identifier 410! Give +.

(4) Rightward transfer ('I' 13-T 18):
When the leftward transfer shown in (3') is completed, the rightward transfer is now performed. At this time, in each unit 1 to 6,
(2) (7) As in the case of rightward transfer, two records are compared, and the record with the smaller result is transferred rightward. With this operation, the second set of record strings are sorted in ascending order from the right end of the comparison and transfer circuit 10 and are sequentially output, and the third introduction record string is sequentially input from the left end. At this time,
The third set of records input from the left end has the identification f-tt 1. as in the case of (2). It is given IT and inputted to the comparison and transfer circuit 10.

(5) Leftward transfer (TI9 to R24): When the rightward transfer in (4) is completed, the leftward transfer is now performed.

At this time, each unit 6 compares the two records in the same manner as in the case of leftward transfer in (3), and transfers the larger record to the left.

With this operation, the third set of record strings from the left end of the comparison and transfer circuit 1.0 are sorted 1 to 1 in descending order and outputted sequentially.

In this example of sort processing, there are three sets of records to be sorted, so the input at the time of the last leftward transfer is the input of a record to be sorted that is not originally required, so the identifier 110
Any character string with IT and 7 will suffice.

In the example in the figure, the human power from the last right end is 〇-〇''.

By repeating the rightward transfer and leftward transfer shown in 1-1 (1) to (5) below, the result of sorting the first set of record strings in descending order in the leftward transfer in (3) is obtained, and ( 4)
The result of sorting the record strings of the second set in ascending order is obtained by the rightward transfer in (5), and the result of sorting the record strings of the third set in descending order is obtained by the leftward transfer of (5).

As shown in this example, by assigning an identifier to the comparison and transfer circuit 10 and inputting the record, the operation of outputting the sort result from either the left or right terminal and the operation of inputting the next record to be sorted are performed in parallel. becomes possible.

FIG. 5 shows an example in which all three sets of record strings are sorted in descending order using the bidirectional sort processing device shown in FIG. In this example, of the bit inverting circuits 12 provided at both ends of the comparison and transfer circuit 10, the left side performs a non-inverting operation and the right side performs an inverting operation.

Further, in FIG. 5, only the comparison transfer circuit 1.0 and the bit inversion circuit 12 on the right side are schematically shown. The record columns to be sorted are the same as in the explanation of Figure 4,
“5, 3, 2, 9, 1.7”; “6, 4, 8, 2, 7.
3”; There are three sets: “4, 3, 8, 4°2.6”.

In this example, by controlling the bit inverting circuit 12, all the record strings can be sorted in descending order with the same operation as in the case of FIG.

(1) Initial state ('[”O): Similar to FIG. 4, the comparison transfer circuit 10 transfers the smaller record of the two records to the right in each unit 1-6, and transfers the larger record to the left. Set to transfer to.Same as the initial settings,
Memory A, 1 and memory B2 of each unit 6 are both A
, 1 ] is set to 0.

(2) Rightward transfer (Tl to T6): Identifier II indicating that the input is from the left to the first set of six Renids 1. IT is given and inputted from the left end of the comparison and transfer circuit 10. When input from the left, the bit inverting circuit 12 is in a non-inverting state, and the input record becomes the input to the wise comparison and transfer circuits 1 and 0 as is. The state in which input of the first set of record strings is completed is 1-6.

(3) Leftward transfer (T7 to T12): The six records of the second set are given an identifier II OIT indicating that they are input from the right, and are input from the right end of the comparison and transfer circuit 10. 1 When input from the right direction, the input record is inverted by the bit inversion circuit 12 and input to the comparison and transfer circuit 10 . With this operation, the first set of record strings are sorted in descending order from the left end of the comparison and transfer circuit 10 and are sequentially output, and the second set of record strings are sequentially input from the right end.

(4) Right direction transfer (1"13 to T18): When the left direction shown in (3) has been completed, this time it is transferred to the right direction. It is given an identifier 1111+ indicating that the input is from the left direction, and is input to the comparison and transfer circuit 10. When the input is from the left direction, the bit inversion circuit 12 is in a non-inversion state, and the input record is compared and transferred as it is. Input to the circuit IO. With this operation, from the right end of the comparison transfer circuit 10, the bit-inverted second set of 1 =
The 1-code string is output in ascending order. By inverting the bits of this output again and outputting it, the magnitude relationship of the records is reversed and a result is obtained in which the records are sorted in descending order. In parallel with this output, the 17-code string of the 73rd introduction is sequentially input from the left end. At this time, the third silk record, which is manually produced from the left end,
As in the case of (2), the identifier LL i I+ is assigned and input.

(5) Left direction transfer (T19-T24): (4
) has been transferred to the right, it is now transferred to the left. With this operation, the third set of record strings are sorted in descending order from the left end of the comparison and transfer circuit 10 and are sequentially output.

By repeating the rightward transfer and leftward transfer shown in (1) to (5) above, the result of sorting the first set of record strings in descending order in the leftward transfer of (3) is obtained, and (4) The result of sorting the second set of record strings in descending order is obtained by the rightward transfer in ), and the result of sorting the third set of record strings in descending order is obtained by the leftward transfer of (5).

In the above explanation, an example was shown in which the unit 6 constituting the comparison and transfer circuit 10 in FIG. 1 transfers a small record to the right and a large 1 code to the left. Even if the circuit 10 is configured to transfer a small 1-node code to the right and a large record to the left, the human power from the left end (right end) and the right end (
A bidirectional saw 1~ that performs output from the left end) in parallel is possible. At this time, by controlling the bit inverting circuits 12 provided at both ends of the comparison and transfer circuit 10, the sorting direction of {circle around (2)} order or descending order can be set.

〔Effect of the invention〕

As explained above, the source processing device of the present invention includes a comparison and transfer circuit having a one-dimensional array structure of a plurality of comparison and transfer units, an identifier assigning circuit, and a bit inverting circuit. By adding and inputting it to the comparison and transfer circuit, record input and sort result output can be performed in parallel in synchronization with the transfer operation of the comparison and transfer circuit. Furthermore, by inputting and outputting records to be sorted while controlling the bit inversion circuit, the sorting process can be performed continuously, and the ascending/descending order of the successive sorting processes can be arbitrarily set. As a result, when this sorting processing device is used repeatedly to sort large records, there is an advantage that the effective operating rate can be improved approximately twice as compared to the conventional saw 1 processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a saw 1-processing device which is an embodiment of the present invention, FIG. 2 is a diagram illustrating the configuration and operation of the identification hand Lj circuit shown in FIG. 1, and 3rd tq l: 1 A diagram explaining the configuration and operation of the bit inverting circuit shown in FIG. 1, FIGS. 4 and 5 are diagrams explaining the operation of the saw processing device shown in FIG. 1, and FIG. FIG. 7 is a diagram showing the operating principle of the conventional saw 1 through the processing device shown in FIG. 1... first memory, 2... second memory, 3...
- Comparator, 4... Flag register, 5... Input/output circuit, 6... Units 1-17... Switching circuit, 8...
...Register A, 9...Register B, 10...
Comparison transfer circuit, 11...Identifier assignment circuit, 12...
Bit inversion circuit. (') ----J Figure 3) Dimensions of 1.
tfll! h p t-t-t-to)-ノ7rak''''
[Jizuta 4 ″′sai 2〆nanji 2

Claims (2)

[Claims] (1) A memory that holds two pieces of data, a comparator that determines the magnitude relationship between the data held in the memory, and one of the two pieces of data based on the size relationship determined by the comparator. data is input from one end of the one-dimensional array and rearranged, and the rearranged data is transferred to one end of the one-dimensional array. When inputting and outputting data to the one-dimensional array, the sorting processing device that outputs data from An identifier assigning means is provided, and the identifier assigning means assigns an identifier, and by inputting data from either the leftmost end or the rightmost end of the comparison transfer unit, continuous sorting processing output operations and A sorting processing device characterized in that it is configured to be able to process input operations in a superimposed manner. (2) The sorting device according to claim 1 further includes bit inverting means for inverting or non-inverting each bit of the data to be sorted that is displayed in binary values, and the identifier assigning means is used to assign an identifier to the sorting device. At the same time, by controlling the bit inverting means to invert the bits of the data to be sorted and input/output the data to be sorted to a one-dimensional array, the sorting direction can be independently set in ascending or descending order between successive sorting processes. A sorting processing device characterized in that it is configured to be configurable.