RU2028664C1 - Concurrent data processing device - Google Patents

Abstract

FIELD: automatic control and computer engineering. SUBSTANCE: device has first and second storage and comparison units for associative flags, logic vector storage unit, operational unit, multiple coincidence analyzing unit, number-of-ones counting unit. EFFECT: enlarged functional capabilities due to search for logical vector-lines by distinctive attributes through cyclic search for logical vector-columns and counting of number of ones in arbitrarily specified vector-column. 5 dwg

Description

 The invention relates to automation and computer technology and can be used, for example, for parallel data processing in solving information retrieval problems, managing databases and knowledge bases, tasks on graphs, problems arising in the development and management of expert systems, and digital data processing tasks arbitrary dimension.

 Known methods and devices for parallel processing partially or fully retained one of the main features of data processing on machines of the Fonneimann type - interaction with RAM is carried out using cells of a limited length (usually up to 32 bits). Bitwise (or vertical) processing is applied either in a limited volume, or as, for example, in associative memory only for solving a narrow class of problems.

The disadvantages of these methods include:
- the complexity of technical implementation;
- the complexity of the structure of computing devices that make it difficult to analyze all kinds of computing situations and situations that control the calculation process;
- the need to develop separate devices for solving a narrow class of problems;
- the complexity and high complexity of the software and mathematics.

 In the article Kulik B.A. High-speed IPS based on operations with logical vectors // US and M, 1989, N 4, pp. 14-19. A data processing method is proposed in which the main computational operations are carried out with strings in (0,1) - alphabet (logical vectors) of arbitrary dimension limited by the size of the rectangular space of associative features (bit matrix memory). Moreover, as the main operations with these vectors, elementary logical operations are used: AND, OR, NOT, EXCLUSIVE OR, checking the logical vector for the presence or absence of units. Using the algorithms proposed in this article, using this method, you can quickly search for information in arbitrary list, matrix and tabular data structures.

 This processing method can be implemented using a specially designed device for addressing by the contents of the memory block, which allows solving, using the parallel processing method, many search tasks, graph tasks, image processing tasks, etc. In this case, the coefficient of increase in speed in comparison with the speed of solving similar problems on traditional computers is n / m, where m is the dimension of the processed words, n is the vertical dimension of the data structure (list, matrix, table, etc.). The architecture of the device involves bitwise processing of matrix memory in two coordinates. In accordance with this, this device in conjunction with the control unit is proposed to be called a biassociative machine (BM).

 The disadvantage of this method and device is that it is difficult to implement cycles of subsequence (i.e., cycles in which only marked lines are to be processed), as well as such digital data processing algorithms that require the calculation of the sums of elements of numerical vectors. In addition, when implementing certain types of tasks of artificial intelligence (expert systems, knowledge bases, etc.), this device slowly implements the calculation of weighting coefficients (or probabilistic characteristics), given or calculated associative features of the system.

 The aim of the proposed technical solution is to expand the class of solved problems of parallel processing carried out using single parallel logical operations on logical vectors of arbitrary dimension.

 The goal is achieved by the fact that in the device containing the first and second blocks for storing and comparing associative signs, a memory block of logical vectors, an operation block, a subunit of a multiple coincidence analyzer and a subunit of a vertical adder are additionally introduced. Moreover, the information inputs of the first and second blocks of storage and comparison of associative signs are the first and second inputs of the device search argument, respectively, and the outputs are the first and second address inputs of the logical vector memory block, the inputs of the job modes of the first and second blocks of storage and comparison of associative signs and memory blocks of logical vectors are respectively the first, second and third inputs of setting device modes, inputs of the initial installation of the first and second blocks relations and comparisons of associative features are connected to the first input of the initial installation of the device, the second input of the initial installation of which is connected to the input of the operational unit of the same name, the first and second outputs of the logical vector memory block are connected respectively to the first and second information inputs of the operational unit, the output and input of the operation code of which are respectively the information output and the fourth input of setting the operation mode of the device; a subunit of the multiple coincidence analyzer and a subunit are introduced an vertical adder, one of the inputs of the analyzer operating mode setting being the fifth input of the device operating mode setting, and the other connected to the corresponding output of the operating unit, the third information input of which is connected to the first information output of the analyzer, the second output of which is connected to the first address input of the memory unit, and the inputs of the job operating modes, the information input and the input of the initial installation of the vertical adder are connected to the corresponding outputs of the operating unit, while the info The vertical output of the vertical adder is the fourth information input of the operation unit, and the first information output of the multiple coincidence analyzer is the second information output of the device.

 Thus, it is possible to carry out fast implementation of loops along the marked lines of a block of matrix memory of logical vectors through the use of a multiple-coincidence analyzer, as well as the quick implementation of a number of digital processing algorithms, calculation of weighting coefficients or probabilistic characteristics of associative features by introducing a vertical adder.

 Identified distinguishing features in this combination were not found in previously known sources, ensure the achievement of the goal and can be qualified as "significant differences".

 In FIG. 1 shows a functional diagram of a parallel data processing device; figure 2 is a functional diagram of an operating unit; in FIG. 3 is a functional diagram of a multiple coincidence analyzer; in FIG. 4 is a functional block diagram of a vertical adder; in FIG. 5 is a timing chart of the operation mode setting signals.

A device for parallel data processing contains blocks 1 ₁ and 1 ₂ for storing and comparing associative signs, a block 2 for logical vector memory, an operation block 3, a subunit 4 of the analyzer of multiple matches, a subunit 5 of the vertical adder, output 5 ₁ , inputs 6 ₄ -6 _{6 of the} job operating mode, input 7 ₁ initial installation. Blocks 1 ₁ , 1 ₂ , 2 fully correspond to the prototype both in circuit and in functional terms.

 In comparison with the prototype, the operational unit 3 introduced minor circuit (switching) changes due to the connection of subunits 4 and 5 to it, but functionally corresponds to the prototype.

 Subunit 4 of the multiple coincidence analyzer functionally coincides with the device of the same name listed in the book by T. Kohonen, Associative storage devices (M .: Mir, 1982, p.167, Fig. 3.8). It is logically connected with block 3 (figure 2 and 3).

 Sub-block 5 of the vertical adder functionally corresponds to the summing group counter, the description and diagram of which are given in the book. Handbook of Integrated Circuits / Ed. Tarabrina B.V. M .: Energy, 1981, p. 701, 704, fig. 5-190.

The presence of subunits 4 and 5 determined two new commands that are sent from the control unit to block 3 (see Fig. 2) to input 6 ₆ . The first of them provides fast implementation of loops along marked lines of memory of logical vectors. We denote this command by the RDC. It initializes the operation of subunit 4.

 The second command counts the number of units in the column vector, we denote it by Cl. It initializes the work of subunit 5. In connection with the appearance of two new commands, the decoder 23 also expands in output, one of its outputs goes to the input of subunit 5, and the other to input 4 of subunit 4 (Fig. 2).

The multiple coincidence analyzer implemented in sub-block 4 (FIG. 1) and represented by the circuit in FIG. 3 contains:
- an inverter 31, to the input of which a BRC signal is received and thereby directs an information vector read from any column of the memory of 2 logical vectors, either through a two-input assembly of AND-OR 32 elements and BRC operations are performed, or through a two-input assembly of AND-OR elements 33 and from its exit directly to the operation unit 3:
- register-shifter 35, in which information, shifting towards the higher bits, is compared in the comparison circuit 38;
- a comparison circuit 38 compares information from the shift register 35 with information from the input 11;
- an address counter 37, which, when the information in the comparison circuit 38 does not match, increases the contents of the address by one at each clock cycle and, referring to address register 36 and address decoder 34, selects the next row vector, etc.

 It should be noted that subunit 4 is included in the discharge chains of column vectors of block 2.

The vertical adder implemented in subunit 5 (Fig. 1), and represented functionally by a circuit (Fig. 4), contains:
a receive register 40 for receiving a logical vector;
- register-shifter 41, which performs a shift in the direction of the higher digits;
- counting trigger 42;
- binary counter 43.

 The "Record" mode corresponds to the algorithm given in the prototype.

 In the algorithm of the "Operation" mode, taking into account the appearance of subunits 4 and 5 and the expansion of the functionality of the device, some additions are made in comparison with the prototype.

 Suppose you want to read an arbitrary column vector. By the presence of units in its digits, select the corresponding row vectors. Perform operations with elements of these row vectors defined by operation block 3. Next, calculate the sum of units of an arbitrarily selected column vector using subblock 5.

Then the device performs this operation as follows: to the input 7 ₁ "Initial installation" of the operation unit 3, a pulse signal of the initial installation. In addition to the initial installation of all the circuits of the device for parallel data processing, the unit is entered into the coincidence circuit 38 through the input 11 of block 4. After the end of the signal of the initial installation, the control unit reads the column vector at an arbitrary address and feeds it to the input of the two-input assembly of elements I19 of block 3. input 6 _{6 of} block 3 is fed by the BRC signal, and input 6 ₄ is the “Read Column” signal, which allows the read vector column through the assembly of elements I19 of block 3 to input 6 of subunit 4. The signal of the BRC, decrypted in command encoder 23 of block 3, is fed to input 4 of subunit 4 and then to input 1 of the assembly of OR 32 elements, allowing the column vector to pass to the shift register 35 of subunit 4 and in inverted form to input 2 of the assembly of OR 33 elements, prohibiting the passage of the vector -column to the output 5 of subunit 4. Next, the column vector is shifted to the higher bits of the shift register 35 of subunit 4. Thus, all the bits of the column vector pass through the highest bit of the shift register 35. At each shift, one bit is charged per unit page counter to 37 of subunit 4. When one appears in the high order of register-shifter 35, matching circuit 38 of subunit 4 is triggered, the information input of which is connected to the highest level of register-shifter 35. In this case, the coincidence signal from the output of coincidence circuit 38 arrives at the installation input line address counter 37, allows the entry of the value of counter 37 on the line address register 36 of subunit 4, line address decoder 34 of subunit 4 and through output 3 of subunit 4 to the bit coordinates of row vector vectors of block 2, choosing a row vector by definition green address. At the same time, the control unit sends a “Read line” signal to input 6 _of block 3 and one of the operation codes, for example, “Logical addition” to input 6 _of block 3. A row vector is fed to input 2 of block 3, which passes through the “Read” signal line "assembly of elements 20, 21 and enters the logical operation node 26 of block 3. Next, the logical operation" Logical addition "is performed in full accordance with the prototype. Upon completion of the operation "Logical addition", the column-vector shift in the shift register 35 is resumed until the next unit appears in its highest order, and the whole process is repeated. This cycle is repeated until the least significant bit of the column vector, shifting, is in the highest bit of the shift register 35 of subunit 4. After that, the pulse of the initial setting signal is again input 7 ₁ "Initial setting" of the operation unit 3. On this, the first part of the Operation mode ends.

 The number of units in an arbitrary column vector is calculated. It happens as follows.

After applying to the input 7 ₁ "Initial installation" of the initial installation signal, it passes through input 10 to trigger 42 and counter 43 of subunit 5 and resets them to their initial state. At the CI command and the Read Column command, a signal is received from the instruction decoder 23 through the input 7 of the subunit 5 to the reception register, which allows the column vector from the reception register 40 to be shifted to the shift register 41. The trigger 42 is connected to the highest bit of the shift register 41. As the column vector is shifted through the shift register 41, the trigger only responds to the presence of unity in this category. If there is a unit in the high order of the shift register 41, the trigger 42 fires and charges the counter 43 per unit. If there is a zero shifter register in the high order, the trigger remains in the previous state, the counter does not charge. Thus, the counter counts the number of units in the column vector and passes this to the control unit.

 The timing diagram of the mode setting signals is shown in the prototype of FIG. 5 and corresponds to this application for an invention, and the timing diagram of the operation mode setting signals is shown in FIG. 5.

 To explain the computing capabilities of the device, it is necessary to give the basic provisions of the mathematical software of the biassociative machine.

The main structural units in the existing systems of accumulation, search and sorting of non-numeric and mixed information are analogues of speech structures, i.e. letters, combinations of letters, words, identifiers, representations of numbers, etc. When entering and outputting information, these structural units are literally necessary, but the appropriateness of using them as the main intermediate elements in the process of machine implementation of parallel operations is doubtful. The effective use of bitwise processing of matrix structures and the use of natural parallelism of data, obviously, largely depends on the choice of the basic structural units in data processing and on the organization of calculations in which analogues of speech structures are not used as intermediate results, if possible. With this in mind, it is advisable to introduce as the main structural units the elements corresponding to the architecture of the BM. These include, but are not limited to:
- a sequence of M (string) and N (column) addresses;
- R - words, words and subwords;
- subsequences.

 The sequences M and N are sets of consecutive addresses of the corresponding "bit slices" of the matrix memory. By the composition of the elements (integers) they can intersect and even coincide.

 R-word - a row or column of zeros and ones whose dimension is equal to the dimension of the corresponding coordinate of the matrix memory. A word or subword is a continuous part of an R-word.

 The word can be encoded in (0,1) - the alphabet of numbers, letters, their sequences or parts thereof.

Subsequences P (R _i ) are defined by an arbitrary R-word R _i and represent a subset of addresses or associated identifiers corresponding to units of the R-word R _i . In other words, when determining a subsequence, it is believed that arbitrary R-words are characteristic vectors of any subsets of M or N, or associated identifiers.

The following notation is introduced: R-words will be denoted by R _i , RNi (if they are in the i-th register of the corresponding processor module) and SM _i , CN _i (if they are in the rows or columns of the matrix memory corresponding to the addresses M _i and N _i ). To designate the words, two more indices (j, k) are introduced, which denote the initial and final digits of the word in the given R-word, i.e. R _i (j, k), CM _i (j, k), CN _i (j, k) are words in the corresponding R-words.

If the data in the matrix memory is presented in the form of a table, and for each element of the table header, the initial and final digits are determined, i.e. a word in an arbitrary R-word is determined by the identifier of the header element, for example, R _i (B), CN _i (GP), etc. In the future, it is believed that SK _i is an R-word of arbitrary coordinate.

 Consider the basic elementary operations in BM.

1) R _i == CK _i - transfer of a row or column of matrix memory with address K _j to the register of the corresponding processor module.

2) CK _j = Ri - write the R-word contained in the register in the column (or row) of the matrix memory with the address K _j .

элементарные логические операции с R-словами, находящимися в регистрах определенного процессорного модуля: .NOT. - НЕ, OR. - ИЛИ, .AND. - И,. XOR. - ИСКЛ.ИЛИ.

elementary logical operations with R-words located in the registers of a particular processor module: .NOT. - NOT, OR. - OR, .AND. - And ,. XOR. - EXCLUSIVE OR.

4) R _i == R _j - transfer of the R-word from register to register.

5) R _i == 0 - "cleaning" of the register, i.e. write zero to all bits of the register.

6) R _i == 0: - zero check. This operation checks the condition; whether all bits in the register are zeros or is there at least one bit with a unit.

In addition to the above operations in BM, it is advisable to implement two types of cycles:
1) a word cycle in which the R-word is loaded into the processor module and operations of the same type are performed on them sequentially at a given subword of addresses M (j, k) or N (j, k), where j and k are the initial and final, respectively subwords addresses;
2) a subsequence cycle in which the loading of R-words and operations on them are carried out according to the subsequence P (R _i ).

For the quick implementation of loops in a subsequence, a sequential multiple-coincidence analyzer is introduced into the processor module, in which active bits of one of the registers of the processor module containing the R-word R _i are activated sequentially by increasing addresses.

 The control device (UE) is a regular mini- or microcomputer, in which the possibility of using a problem-oriented language is provided (in this paper we use a frequently encountered subset of the PASKAL language with some extension to denote the above operations with R-words).

In Art. Kulika B.A. "High-speed IPSs based on operations with logical vectors" a number of algorithms are given that allow you to organize a search in an arbitrary table. A list of these algorithms and an assessment of their computational complexity are given in the table. When evaluating the complexity of algorithms, the following notation is used:
0 - designation of the complexity function;
m is the number of bits of the bit representation of the array element;
k is the number of fields in the data table.

 For the algorithms shown in the table, the computational complexity does not depend on the number of array elements or the number of entries in the data tables, provided that this number does not exceed the corresponding dimension of the matrix memory.

 Consider some unpublished algorithms and methods for their implementation on the proposed device, allowing you to use it to solve problems of fast digital processing of vector and matrix data types. One of the main digital processing algorithms is the vector sum algorithm. We first consider this operation for a multitude of unsigned numbers presented in a fixed-point format.

Algorithm N (i, j) == N (p, q) + d
Data: the set of m-bit unsigned binary numbers located in the N (p, q) column and the m-bit binary number d, whose bit values are respectively
d _m-1 , d _m-2 , ..., d ₀ .

 Result: a set of m + 1-bit unsigned binary numbers located in the N (i, j) column and representing the sum of each element of the original vector with the number d.

{1} R ₁ == 0;
{2} R ₂ == 0;
{3} k: == 0;
{4} while k <m + 1 d ₀
{5} begin
{6} R ₃ == CN (qk);
{7} if d _k = 0 then R ₄ == R ₁ else R ₄ ==. NOT.R ₁ ;
{8} R ₅ == R ₂ .XOR.R ₃ .XOR.R ₄ ;
{9} R ₂ == (R _2. AND.R ₃ ). OR. (R ₂ .AND.R ₄ ). .OR. (R ₃ .AND.R ₄ );
{10} CN (jk) == R ₅ ;
{11} k: = k + 1
{12} end;
{13} CN (i) == R ₂ .

 In the presented algorithm, in line 8, the value of the current discharge of the sum is calculated, and in line 9, the transfer function is calculated.

In some cases, it becomes necessary to leave the subsequence of any elements of the set of numbers unchanged in the process of computing the vector sum, for example, add a given number only to negative numbers in a column. To solve this problem, in particular, you can use the algorithm
N (i, j) = N (p, q) + d.AND.P (r _i ), in which the magnitude of only those numbers that are marked by the vector P (n) located in one of the digits of the matrix memory changes. To solve this problem, you can use the previous algorithm by adding the following lines to it after lines 2 and 7:
{2a} R ₆ == P (n);
{7a} R ₄ == R4.AND.R ₆ .

 To account for the signs of numbers located in the columns of the matrix memory, it is advisable to introduce a sign digit located, as in traditional ALU, to the left of the most significant digit. In addition, numbers can be represented in additional and reverse codes. Let us show how the device performs the operation of converting a direct code with a sign in the high order to an additional code.

SS algorithm N (i, j)
Data: the set of fixed-point numbers represented in the direct code in the column N (i, j), and the m-bit positive number d, representing the smallest positive number in this format.

 Result: the original set of numbers represented in the additional code in the same column.

{1} R _i == CN (i);
{2} for k: = i + 1 t ₀ jd ₀
{3} begin
{4} R ₂ == CN (k);
{5} R ₂ == R ₂ .XOR.R ₁ ;
{6} CN (k) == R ₂ ;
{7} end;
{8} N (i, j) == N (i, j) + d.AND.R ₁ .

 In this algorithm, depending on the value of the sign digit, the values of the current bits of numbers remain unchanged or are inverted, after which the number d is added to the negative numbers.

 The algorithm for converting numbers from an additional code to a straight line is implemented similarly to the above, but in the reverse order: first, the smallest negative number, presented in the additional code, is added to the set of negative numbers, after which the significant digits of negative numbers are inverted.

 For vector addition of two sets of numbers, you can use the following algorithm.

Algorithm N (i, j) == N (p, q) + N (s, t)
Data: two numerical vectors represented in the additional code in m-bit columns N (p, q) and N (s, t).

 Result: a set of m + 1-bit numbers represented in an additional code, each of which is equal to the sum of two numbers located on the corresponding line in the columns N (p, q) and N (s, t).

{1} R ₁ == 0;
{2} k: = 0;
{3} while k <m + 1 d ₀
{4} begin
{5} R ₂ == CN (tk);
{6} R ₃ == CN (qk);
{7} R ₄ == R ₁ . XOR.R ₂ .XOR.R ₃ ;
{8} R ₁ == (R ₁ .AND.R ₂ ) .OR. (R ₁ .AND.R ₃ ). .OR. (R ₂ .AND.R ₃ );
{9} CN (j, k) == R ₄ ;
{10} k: = k + 1;
{11} end;
{12} R ₄ == R ₁ .XOR.R ₂ .XOR.R ₃ ;
{13} CN (i) == R ₄ .

 This algorithm provides for the addition of a discharge to the column of results in order to avoid possible cases of overflow when calculating the sum of two numbers.

 Knowing the algorithm for calculating the vector sum, it is easy to compose an algorithm for calculating the vector product. In this case, as well as when performing operations with numbers presented in floating point format, it is necessary to shift the marked numbers of the column. As an example, consider an algorithm that implements a right shift by one bit of marked column numbers.

Algorithm RS N (i, j) .ABD.P (n)
Data: m-bit words or numbers written in column N (i, j), and vector P (n) marking the lines to be shifted.

 Result: a shift by one digit in the marked words of column N (i, j).

{1} R ₁ == P (n);
{2} R ₂ == CN (i);
{3} R ₃ == .NOT. R ₁ . AND. R ₂ ;
{4} CN (i) == R ₃ ;
{5} R ₃ == CN (i + 1);
{6} for k: = 1 t ₀ m-1 d _o
{7} begin
{8} R ₂ == (R _1. AND.R ₂ ) .OR. (.NOT. R ₁ .AND. R ₃ );
{9} CN (i + k) == R ₂ ;
{10} R ₂ == R ₃ ;
{11} R ₃ == CN (i + k + 1)
{12} end.

 It is easy to verify that the computational complexity of the above algorithms does not depend on the dimension of the vector if it does not exceed the corresponding dimension of the matrix memory.

The calculation of the sum of an arbitrary vector in a traction computer is carried out with complexity O (N), where N is the number of elements in the vector. Introduction to the device of a vertical adder allows vectors of large dimension to significantly accelerate this operation. Denote by SUM (R _i ) the operation of summing the units in the register R _i . If m-bit elements of a numerical vector are represented in direct code in the column N (i, j), then the summation of all elements of this vector can be carried out using the following sequence of operations (S [1.. M-1], T [1..m -1] - intermediate arrays of positive integers):
{1} R ₁ == CN (i); {loading into the register of a sign discharge}
{2} R ₂ == .NOT .R ₁ ;
{3} for k: = i + 1 t ₀ jd ₀
{4} begin
{5} R ₃ == CN (k);
{6} R ₄ == R ₁ . AND. R ₃ ;
{7} S [k-1]: = SUM (R ₄ );
{8} R ₄ == R ₂ . AND .R ₃ ;
{9} T [k-1]: = SUM (R ₄ )
{10} end.

S[i]×2^m-i-1
{2} TS: =

T[i]×2^m-i-1
{3} RES:=TS-SS.To calculate the amount, it is enough in UU to make the following calculations:
{1} SS: =

S [i] × 2 ^mi-1
{2} TS: =

T [i] × 2 ^mi-1
{3} RES: = TS-SS.

 Obviously, when using a vertical adder, the computational complexity of the operation of summing a vector is O (sm), where s is the computational complexity of the operation of summing units in an arbitrary bit, and m is the number of bits of the vector elements.

 Thus, the proposed technical solution allows you to expand the class of parallel processing tasks carried out using parallel logical operations on logical vectors of arbitrary dimension.

Claims (1)

 A device for PARALLEL DATA PROCESSING, containing the first and second blocks for storing and comparing associative signs, a logical vector memory block and an operation block, the information inputs of the first and second blocks for storing and comparing associative signs are the first and second inputs of the device search argument, respectively, and their outputs connected respectively to the first and second address inputs of the logical vector memory block, the mode inputs of the first and second storage blocks and associative comparisons the nak and the write-read input of the logical vector memory block are respectively the first, second, and third inputs of the device mode, the first input of the initial installation of the device is connected to the inputs of the initial installation of the first and second blocks of storage and comparison of associative signs, the second input of the initial installation is to the input of the initial installation operating unit, the first and second outputs of the logical vector memory block are connected respectively to the first and second information inputs of the operating unit, the input of the operating code the device’s AI is connected to the input of the operation unit operation code, characterized in that, in order to expand the functionality by searching for logical row vectors by distinguishing attributes through cyclic enumeration of logical column vectors, as well as counting the number of units in an arbitrarily specified column vector, it contains a multiple coincidence analysis unit, a unit number counting unit, the second input of the initial installation of the device being connected to the initial settings of the unit numbering unit and the unit liz of multiple matches, the first and second outputs of which are connected respectively to the third address input of the logical vector memory block and the third information input of the operation unit, the first and second information outputs, the output of the operation attribute of the analysis of multiple matches and the output of the operation sign of determining the number of units of the operation unit are connected respectively to the information inputs of the multiple coincidence analysis unit and the unit number counting unit, to the synchronization inputs of the multiple coincidence analysis unit tnyh coincidence and counting the number of block units, whose output is connected to the data output device and the fourth data input operation unit.

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