JPS60537A - Normalizing circuit - Google Patents

Abstract

PURPOSE:To execute quick normalizing process by shifting plural bits in a bundle among plural bits at the first time, then changing the shift from plural bits to one bit at a time when the plural-bit shifting is recognized as excess shifting. CONSTITUTION:Output bits a0-an-1 of a register 10 in which decimals are set are connected with the input sides of a 4-bit shift circuit 24 and 1-bit shift circuit 12, and the output of the register 10 is shifted by four bits in a bundle at the circuit 24. Exclusive OR gate groups 32-38 take the exclusive OR of the sign bit a0 of the register 10 and high-order four bits and input the result into an encoder 40 as e0-e3. When all the signals e0-e3 are ''0'', the encoder 40 sets its output signal fa to ''1'' and opens a gate 26 and inputs the output of the circuit 24 into the register 10. When the excess of bits is shifted at the circuit 24 and any one of the signals e1-e3 goes to ''1'', the encoder 40 sets its output signal to ''1'' and switches the shifting operation to the circit 12. Then a gate 28 is opened by means of a signal fb and bits are shifted one by one and inputted into the register 10. When the signal e0 goes to ''1'', the normalization is terminated and an end signal F is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a decimal number normalization circuit, and is intended to enable quick normalization processing.

Conventional technology and problems In computers, n-bit binary decimal numbers Ao=aoa+ra a
For decimal numbers where up to l is 0, the decimal point is often moved so that the most significant bit al becomes 1, that is, normalization processing is often performed. This normalization process can be expressed as follows.

=A+X2' where 2°<A+<2-1- where S is a sign bit and if Ao≧0 then 0. A.

If <0, it is 1, A1 is the decimal after normalization, m is the number of shifts of the decimal point performed in the normalization process, and these are called the mantissa and exponent parts of the normalized decimal.

Figure 2 shows an example where the decimal number Ao=SOO1010 is normalized to 5101QOO (S=0(7)),
Normalization is completed with two left shifts. FIG. 1 shows an outline of a processing program that performs such normalization, and FIG. 3 shows the hardware. As shown in Figure 1, normalization involves the sign bit s and each decimal bit aI+a2...
If the result of this exclusive OR is 0, exclusive OR is performed between the next bit and the sign bit, and this is repeated until F=1. In FIG. 3, decimal numbers A and o are placed in register 10 during normalization. The output and input terminals of a 1-bit shift circuit 12 are connected to the input and output terminals of the register, and the shift circuit 12 is connected to the input and output terminals of the register 10.
Each of the bits a1 to an-1 at the output end of is shifted to the left by 1 bit·71~ and input to the register 10. This process is performed every time the shift clock CLK is input to the register 10. 14 is an exclusive OR gate which inputs ao, aaQ, a2 . Take the exclusive OR of... As a result, if F is O, inhibit game) 16
．． 18 is open and the clock CLK enters registers 10 and 20 through the gate. Each time the clock CLK is input to the register 20, the +1 circuit 22 fetches the contents of the register by +1, and counts the number of shifts m as a result.

When a1=1, F=1, gates 16 and 18 are closed, and shifting and counting are stopped.

The contents of the register 10 at this time are the normalized numerical part of the decimal number, that is, the mantissa, and m is its exponent. In the conventional method, as described above, the shift is performed one bit at a time until the most significant bit becomes 1. Therefore, for an n-bit decimal number where only the least significant bit is 1, the shift must be repeated (n-2) times, which increases the processing time. The disadvantage is that it becomes long.

OBJECTS OF THE INVENTION The present invention attempts to initially shift a plurality of bits at a time, and then switch to a 1-bit shift when the shift becomes too much, thus enabling rapid normalization processing.

Structure of the Invention The normalization circuit of the present invention includes a register to which a decimal number is set;
A 1-bit shift circuit that shifts all pins of the register one bit at a time, a multiple-bit shift circuit that shifts multiple bits/nodes at a time, and whether the high-order bits of the register can be shifted by multiple bits or only 1 bit can be shifted. , further comprising a circuit that determines whether normalization is completed, enables either the multi-bit shift circuit or the one-bit shift circuit, and outputs a normalization completion signal when normalization is completed, This will be explained with reference to examples.

Embodiment of the Invention FIG. 4 shows a first embodiment of the invention, in which the same parts as in FIG. 3 are given the same reference numerals. 24 is a 4-bit shift circuit which, like the 1-bit shift circuit 12, has an output terminal connected to the output and input terminal of the register 10, and shifts each via (a+ to a n -H) of the output terminal of the register 10 by 4 bits. Input to the register 10. Fig. 5 (al shows an example of the 4-bit shift circuit 24. In this example, n = 3, each has 8 output terminals, and the 1st sine focus remains the same, but the 6th The input of is connected to the 2nd output, the 7th input is connected to the 3rd output, etc., and the outputs of 5th to 8th are given "0" input, thus the output of register 10 is "a+" A7 is shifted by 4 bits at a time.■The focus shift circuit has the configuration shown in FIG. 5 (bl).The output terminals of these shift circuits receive signals fa,
It is connected to the input end of the register 10 through an AND gate 26, 28 and an OR gate 30 which are opened at fb.

Whether it is a 4-bit shift or a 1-bit shift is determined by looking at the upper 4 bits of register 10. Exclusive or gate 32.3'
4, 36. 38 and encoder 40 are the circuits that do this,
The exclusive gate group has the sign bit ao and the upper 4 bits a1
Take the exclusive OR of ~a4 and output the result as eo~e3. Encoder 40 receives these signals and produces output signals fa-fc shown in the truth table below.

Table 1 eo to e3 are O, which means a1 to a4 are the same as aQ,
That is, it is O, and in this case, it may be shifted by 4 bits. Also, eo is 0, but e1 to e? This means that al is 0, so normalization has not been completed, but a2
-a4 is 1, so a 4-bit shift is too much. Encoder 40 therefore produces signal fa in the former case, opens AND gate 26 to enable 4-bit shift circuit 24, and produces signal fb in the latter case.
is generated to open the AND gate 28 and enable the 1-bit shift circuit 12. These signals fa and fb are also applied to AND gates 42 and 44, which open them and output "'4".
or 1'' is inputted to the adder 22 through the OR gate 46, and the circuit consisting of the register 2o and the adder 22 becomes a +4 circuit or a +1 circuit.

Furthermore, when eo-1, this means that a1=l, that is, the normalization is completed, and at this time the encoder 40 outputs fc(-
F) closing the inhibitor gates 16 and 48;
Stop the shifting and counting operations of register 10.20. Signal F becomes a normalization completion indication signal.

FIG. 6 shows a second embodiment of the present invention that performs a +8 focus shift, and the same parts as in FIG. 4 are given the same reference numerals. 50 is an 8-bit shift circuit having a configuration as shown in FIG. 5(C), in which the 9th, 10th, . . . a. ,..., first, second, etc.
... data bits XI, X2. Do... 52 is an exclusive OR gate group, which includes the sign bit ao output from the register 10 and the first to eighth data bits a1.
Exclusive OR is performed with ~a8 and the result is 80j''e7. The encoder 40 receives this and produces the output fa+fb+fc shown in the truth table below.

Table 2 Item 1 is a case where 8-bit shift is possible, and items 2 to 8 are e
1 to e7 Therefore, any of a2 to ae is 1, 8 bit shift is not possible, 1 bit shift is the case, and eo = l
is a case where normalization is complete.

According to these cases, encoder 4o outputs signal fa.

It generates fb and fc, performs an 8-hit shift, a 1-bit shift, and displays the completion of normalization.

A multi-bit shift even larger than the 8-bit shift j-, and a combination of vinod, 4-bit, and 8-bit shifts, may be considered, but consideration should be given to the fact that the circuit is relatively simple and the multi-bit shift has great practical advantages. That is also important.

Moreover, although the above description has been made of a positive decimal number with zero sign bits, the present invention can be similarly applied to a sign bit of one, that is, a negative decimal number. Note that if the decimal number Ao to be normalized is all 0 or 1, it is removed before being processed by the circuit of the present invention.

As described in detail, according to the present invention, normalization processing can be performed quickly, and this invention greatly contributes to high-speed calculation.

[Brief explanation of the drawing]

1 to 3 are flowcharts, explanatory diagrams, and block diagrams explaining conventional normalization processing, FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a 1, 4.8 bit shift circuit. FIG. 6 is a block diagram showing another embodiment of the present invention. In the drawing, 10 is a register where a decimal number is set, and 12 is a register that is set to a decimal number.
A bit shift circuit, 24.25 is a plural bit shift circuit, and 32, 34, 36, 38, 40.52 is a circuit for selecting a shift circuit, etc. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 4 Figure 5

Claims (1)

[Claims] A register to which a decimal number is set, a 1-bit shift circuit that shifts all bits of the register one bit at a time, and a multiple-bit shift circuit that shifts multiple bits at a time, and whether the upper bits of the register are in a state where multiple pins can be shifted. and a circuit that determines whether only bit shifting is possible or whether normalization is complete, enables either the multi-bit shift circuit or the one-bit shift circuit, and outputs a normalization completion signal when normalization is complete. Characteristic normalization circuit.