CN103699351B - One is decaptitated the shift circuit that truncates - Google Patents
One is decaptitated the shift circuit that truncates Download PDFInfo
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- CN103699351B CN103699351B CN201310654278.6A CN201310654278A CN103699351B CN 103699351 B CN103699351 B CN 103699351B CN 201310654278 A CN201310654278 A CN 201310654278A CN 103699351 B CN103699351 B CN 103699351B
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Abstract
The invention discloses one to decaptitate the shift circuit that truncates, it is adaptable to count greatly square operations.This invention circuit structure includes: 2m lt depositor, m position Johnson move to left enumerator, m position and door network.Wherein, the 2m-1 position of 2m bit register and Johnson move to left the m position output of enumerator and are connected to m position and door network, and output result is sent in the depositor of 2m position, the final Q exporting 2m position.2m bit data progressively can be decaptitated and be truncated by the present invention, moves to left, and remaining bit mends 0, until finally output result is 0, thus reducing the operation time of square operation.
Description
Technical field
The invention belongs to IC design field, be specifically related to one and decaptitate the shift circuit that truncates.
Background technology
The scheme generally adopted currently for the research of big digital-to-analogue square is Montgomery algorithm, and this algorithm length in the time spent by the calculating process of mould square and input data is directly proportional.
In view of this, it is necessary to design a kind of novel squaring circuit, by the optimization of the partial product to calculating process, reducing the number of times of partial product, thus reducing by the operation time of whole square, solving the problems referred to above.
Summary of the invention
It is an object of the invention to provide one to decaptitate the shift circuit that truncates, 2m bit data progressively can be decaptitated and be truncated by it, moves to left simultaneously, by rest position 0, until output result is 0；It is applicable to big number square operation, it is possible to effectively reduce the time of square operation process.
In order to achieve the above object, the present invention is achieved by the following technical solutions: include 2m lt depositor, m position Johnson moves to left enumerator and m position and door network；Wherein, the 2m-1 position of 2m bit register and m position Johnson move to left the m position output of enumerator and are connected on m position and the door of m position and door network, the output result of m position and door is sent in the depositor of 2m position, and final output result is the Q of the depositor of 2m position；Wherein, Q be 2m position depositor in the result of d type flip flop true form outfan output, and 160≤m≤15360.
Described m position Johnson moves to left counter initial value and is all set to 1.
Described m position and door network are two inputs and door.
In described 2m lt depositor, each moves to left and comprises a d type flip flop and an alternative data selector in depositor, and the outfan of alternative data selector is connected with the D input of d type flip flop；The output of output and 2m-1 bit register that m position Johnson moves to left enumerator is separately input on two inputs with door of the m position, and m position and goalkeeper's result are input in the alternative data selector moved to left in depositor of 2m position.
Compared with prior art, the method have the advantages that
Input in m position of the present invention Yu door network moves to left enumerator respectively from 2m lt depositor and m position Johnson, output result is the Q of 2m position, this circuit often just can remove highest order and the lowest order of input data through a clock cycle, and is moved to left by the data obtained, and low level mends 0.Thus reaching to optimize the partial product of square operation, reduce the purpose of operation time.
Accompanying drawing explanation
Fig. 1 is that the present invention decaptitates the shift circuit structure chart that truncates；
Fig. 2 is the circuit diagram that the present invention is concrete.
Detailed description of the invention
Referring to Fig. 1, the present invention includes 2m lt depositor, m position Johnson moves to left enumerator and m position and door network；Wherein, m position Johnson moves to left counter initial value and is all set to 1.M position and door network are two inputs and door.The 2m-1 position of 2m bit register and m position Johnson move to left the m position output of enumerator and are connected to the m position with door network, the m position with on door, and the output result of m position and door is sent in the depositor of 2m position, and final output result is the Q of the depositor of 2m position；Wherein, Q be 2m position depositor in the result of d type flip flop true form outfan output, and 160≤m≤15360.In 2m lt depositor, each moves to left and comprises a d type flip flop and an alternative data selector in depositor, and the outfan of alternative data selector is connected with the D input of d type flip flop；The output of output and 2m-1 bit register that m position Johnson moves to left enumerator is separately input on two inputs with door of the m position, and m position and goalkeeper's result are input in the alternative data selector moved to left in depositor of 2m position.
The work process of the present invention is:
Referring to Fig. 2, during initialization, RS=0, the shift register of 2m position is all set to 0；SET=0, moves to left enumerator by m position Johnson and is all set to 1；During work, SE=0, when rising edge clock arrives, export Q=a2ma2m-1a2m-2…am+1am…a3a2a1, m position Johnson moves to left the lowest order of enumerator and becomes 0.After a clock, export Q=a2m-1a2m-2…am+1am…a3a200, and now m position Johnson moves to left the secondary low level of enumerator and also becomes 0.After two clocks, export Q=a2m-2…am+1am…a30000, m position Johnson move to left enumerator low three become 0.By that analogy, often after a clock, output Q decaptitates to truncate and moves to left one, and residue low level is filled with 0, until m+1 clock, output Q is full 0.
Illustrate for the situation of m=4 below:
Table 1
Referring to table 1, during the 0th CLK, Johnson enumerator output complete 1, circuit output Q is 0 entirely；Next often J and circuit output Q are exported according to above-mentioned rule change through CLK, a Johnson enumerator, until during the 5th CLK, exporting full 0.A8a7a6a5a4a3a2a1During for other situations, exporting change is similar.
Claims (4)
1. the shift circuit that truncates of decaptitating, it is characterised in that: include 2m lt depositor, m position Johnson moves to left enumerator and m position and door network；Wherein, the 2m-1 position of 2m lt depositor and m position Johnson move to left the m position output of enumerator and are connected on m position and the door of m position and door network, what the output result of m position and door was sent to 2m position moves to left in depositor, and finally exporting result is the Q moving to left depositor of 2m position；Wherein, Q is the result of d type flip flop true form outfan output in depositor that moves to left of 2m position, and 160≤m≤15360.
2. the shift circuit that truncates of decaptitating according to claim 1, it is characterised in that: described m position Johnson moves to left counter initial value and is all set to 1.
3. the shift circuit that truncates of decaptitating according to claim 1, it is characterised in that: described m position and door network are two inputs and door.
4. the shift circuit that truncates of decaptitating according to claim 1, it is characterized in that: in described 2m lt depositor, each moves to left and comprises a d type flip flop and an alternative data selector in depositor, and the outfan of alternative data selector is connected with the D input of d type flip flop；The output of output and 2m-1 lt depositor that m position Johnson moves to left enumerator is separately input on two inputs with door of the m position, and m position and goalkeeper's result are input in the alternative data selector moved to left in depositor of 2m position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310654278.6A CN103699351B (en) | 2013-12-05 | 2013-12-05 | One is decaptitated the shift circuit that truncates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310654278.6A CN103699351B (en) | 2013-12-05 | 2013-12-05 | One is decaptitated the shift circuit that truncates |
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| Publication Number | Publication Date |
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| CN103699351A CN103699351A (en) | 2014-04-02 |
| CN103699351B true CN103699351B (en) | 2016-06-29 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60537A (en) * | 1983-06-17 | 1985-01-05 | Fujitsu Ltd | Normalizing circuit |
| CN1375764A (en) * | 2001-03-19 | 2002-10-23 | 深圳市中兴集成电路设计有限责任公司 | Circuit and method for realizing RSA enciphering algorithm |
| US6751644B1 (en) * | 1999-09-15 | 2004-06-15 | Sun Microsystems, Inc. | Method and apparatus for elimination of inherent carries |
| CN101509954A (en) * | 2009-03-13 | 2009-08-19 | 西安交通大学 | Test graph builder of integrated circuit |
| CN101834723A (en) * | 2009-03-10 | 2010-09-15 | 上海爱信诺航芯电子科技有限公司 | RSA (Rivest-Shamirh-Adleman) algorithm and IP core |
-
2013
- 2013-12-05 CN CN201310654278.6A patent/CN103699351B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60537A (en) * | 1983-06-17 | 1985-01-05 | Fujitsu Ltd | Normalizing circuit |
| US6751644B1 (en) * | 1999-09-15 | 2004-06-15 | Sun Microsystems, Inc. | Method and apparatus for elimination of inherent carries |
| CN1375764A (en) * | 2001-03-19 | 2002-10-23 | 深圳市中兴集成电路设计有限责任公司 | Circuit and method for realizing RSA enciphering algorithm |
| CN101834723A (en) * | 2009-03-10 | 2010-09-15 | 上海爱信诺航芯电子科技有限公司 | RSA (Rivest-Shamirh-Adleman) algorithm and IP core |
| CN101509954A (en) * | 2009-03-13 | 2009-08-19 | 西安交通大学 | Test graph builder of integrated circuit |
Non-Patent Citations (2)
| Title |
|---|
| 利用中国剩余定理改进大数模平方计算研究;施月玲;《杭州电子科技大学学报》;20070228;第27卷(第1期);第42-45页 * |
| 数字专用集成电路中平方运算的硬件实现;韩雁等;《电子科学学刊》;19961231;第18卷(第6期);第649-651页 * |
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