CN103684368B - Universal reversible compares interchanger - Google Patents
Universal reversible compares interchanger Download PDFInfo
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- CN103684368B CN103684368B CN201310730155.6A CN201310730155A CN103684368B CN 103684368 B CN103684368 B CN 103684368B CN 201310730155 A CN201310730155 A CN 201310730155A CN 103684368 B CN103684368 B CN 103684368B
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Abstract
The invention discloses a kind of Universal reversible and compare interchanger.Present invention uses reversible logic gate and construct a reversible complete comparator, on this basis reversible for one, this position complete comparator and Fredkin door are carried out cascade, structure Universal reversible compares the cascade circuit of interchanger, this Universal reversible compares numeric ratio that interchanger realizes two n bits comparatively and export comparative result, determine whether exchange this two number according to comparative result, export this two n bits.The building method of this Universal reversible comparator has stronger versatility, is easy to expansion, has lower quantum cost and less constant input position and rubbish carry-out bit.
Description
Technical field
Present invention uses the Basic Reversible gate that these five kinds, NOT door, CNOT door, Toffoli door, 4-Toffoli door and Fredkin door is conventional, these reversible doors are carried out cascade, constructs the cascade circuit that a kind of Universal reversible based on reversible logic compares interchanger.
Background technology
Traditional computer uses irreversible technology, and there is information bit in calculating process and lose, according to Landauer principle, the loss of an information bit will cause kTln2 (to be about 3*10
-21j, wherein k is Boltzmann constant, and T is current thermodynamic temperature) loss of energy consumption.Along with the technological level of integrated circuit and integrated level improve constantly, the chip functions in integrated circuit will be subject to quantum effect interference, and the heat dissipation problem of chip cannot fundamentally solve simultaneously, also will suppress the development of traditional silicon chip technology.
Reversible calculating is a kind of new computation model, and he is by recovering and re-using the loss that the data of losing avoid the logic energy consumption in circuit.Say in a sense, the process of calculating is exactly that logarithm value carries out conversion calculus according to certain rule.Different from traditional irreversible calculating, reversible calculating is all reversible in the process of whole calculating, namely inverting can calculate back its back or initial conditions by any step intermediate object program in calculating, and in the ordinary course of things, irreversible calculating cannot accomplish this point.Bennett proposes and demonstrates reversible calculating is logically feasible.The design of reciprocal circuit is the important step realizing reversible calculating, and reversible door is the basic processing unit realizing reciprocal circuit, the people such as Toffoli and Fredkin propose several gate realizing reversible calculating, and this makes to become possibility to the design and implimentation of reversible logic parts.For the design of reciprocal circuit, scholars have dropped into great enthusiasm, the reciprocal circuit of multiple difference in functionality, as reversible adder, reversible multiplier, reversible divider etc. in succession propose and designed.The design of these reversible logic parts has huge theory significance to the development of reversible computer and realization and instructs and practice support.
Summary of the invention
The object of this invention is to provide a kind of Universal reversible and compare interchanger, solve the numeric ratio of two binary numbers comparatively with reversible logic circuits.Export comparative result and export this two binary numbers, when the first number is numerically wanted little than the second number, exchanging and export these two binary numbers.
The present invention is realized by following technical scheme:
A kind of Universal reversible compares interchanger, is formed by a n reversible complete comparator and n Fredkin door cascade construction, and this Universal reversible compares interchanger and inputs 0,1 constant input, 1,2 constant input, 0, two n bit A by n constant respectively
i (n-1), A
i (n-2)..., A
i0and B
i (n-1), B
i (n-2)..., B
i0formed, 3n+3 input altogether; Output corresponding is with it that n rubbish exports, O
a=B, O
a>B, O
a<B, and two n bit A
o (n-1), A
o (n-2)..., A
o0and B
o (n-1), B
o (n-2)..., B
o0.Forming first device that this Universal reversible compares the cascade circuit of interchanger is first piece of reversible complete comparator, the input I of first piece one reversible complete comparator
a=B, I
a>Band I
a<Bbe set to 1,0 and 0 respectively; Second device is second piece of reversible complete comparator, the input I of second piece one reversible complete comparator
a=B, I
a>Band I
a<Bbe respectively the output O of first piece one reversible complete comparator
a=B, O
a>Band O
a<B, the rest may be inferred, and (n-1)th device is (n-1)th piece of reversible complete comparator, the input I of (n-1)th piece one reversible complete comparator
a=B, I
a>Band I
a<Bbe respectively the output O of the n-th-2 pieces one reversible complete comparator
a=B, O
a>Band O
a<B; N-th device is n-th piece of reversible complete comparator, the input I of n-th piece one reversible complete comparator
a=B, I
a>Band I
a<Bbe respectively the output O of (n-1)th piece one reversible complete comparator
a=B, O
a>Band O
a<B.The control bit of n Fredkin door is afterwards all the output O of n-th piece one reversible complete comparator
a<B, target bit is the output A of first piece one reversible complete comparator respectively
o (n-1)with output B
o (n-1), the output A of second piece one reversible complete comparator
o (n-2)with output B
o (n-2), the like, the target bit of the n-th Fredkin door is the output A of n-th piece one reversible complete comparator
o0with output B
o0.
A reversible complete comparator has 6 to input and 6 outputs, and by 4 NOT doors, 1 CNOT door, 2 Toffoli doors and 2 4-Toffoli gate leve connection construct.6 inputs are respectively 1 constant input 0,5 and are respectively I
a=B, I
a>B, I
a<B, A
inand B
in; 6 corresponding with it outputs are respectively 1 rubbish output, O
a=B, O
a>B, O
a<B, A
outand B
out.First door is NOT door, and target bit is B
in; Second door is CNOT door, and control bit is I
a=B, target bit is constant input 0; 3rd door is 4-Toffoli door, and control bit is respectively I
a=B, A
inand B
in, target bit is I
a>B; 4th door is NOT door, and target bit is B
in; 5th door is NOT door, and target bit is A
in; 6th door is 4-Toffoli door, and control bit is respectively I
a=B, A
inand B
in, target bit is I
a<B; 7th door is NOT door, and target bit is A
in; 8th door is Toffoli door, and control bit is constant input 0 and I
a>B, target bit is I
a=B; 9th door is Toffoli door, and control bit is constant input 0 and I
a<B, target bit is I
a=B.
The present invention is that a kind of Universal reversible compares interchanger, completes while two n bit A and B size compare, and exports comparative result and remains the initial value of n bit A and B, as A<B, exchanging the value of A and B.This Universal reversible comparator has versatility, can compare two of an any digit binary number, according to comparative result, exchanges exporter two number.Because this circuit is reversible logic circuits, so avoid because of the energy loss that the loss of logical message position produces in system, can effectively reduce circuit energy consumption.
Accompanying drawing explanation
Fig. 1: one one reversible complete comparator realizing circuit figure;
Fig. 2: one reversible complete comparator module figure;
Fig. 3: Universal reversible compares interchanger realizing circuit figure.
Embodiment
In order to deepen the understanding of the present invention, below in conjunction with embodiment and accompanying drawing, the invention will be further described, and this embodiment only for explaining the present invention, does not form limiting the scope of the present invention.
The present invention is realized by following technical scheme:
Universal reversible compares interchanger and is formed by a n reversible complete comparator (OBCC) and n Fredkin door cascade construction.This Universal reversible compares interchanger and inputs 0,1 constant input, 1,2 constant input, 0, two n bit A by n constant respectively
i (n-1), A
i (n-2)..., A
i0and B
i (n-1), B
i (n-2)..., B
i0formed, 3n+3 input altogether; Output corresponding is with it that n rubbish exports (GarbageOutput), O
a=B, O
a>B, O
a<B, and two n bit A
o (n-1), A
o (n-2)..., A
o0and B
o (n-1), B
o (n-2)..., B
o0.Forming first device that this Universal reversible compares the cascade circuit of interchanger is OBCC (#1) (represent the 1st piece of OBCC, below analogize), the input I of OBCC (#1)
a=B, I
a>Band I
a<Bbe set to 1,0 and 0 respectively; Second device is the input I of OBCC (#2), OBCC (#2)
a=B, I
a>Band I
a<Bbe respectively the output O of OBCC (#1)
a=B, O
a>Band O
a<B, the rest may be inferred, and (n-1)th device is OBCC (#n-1), the input I of OBCC (#n-1)
a=B, I
a>Band I
a<Bbe respectively the output O of OBCC (#n-2)
a=B, O
a>Band O
a<B; N-th device is OBCC (#n), the input I of OBCC (#n)
a=B, I
a>Band I
a<Bbe respectively the output O of OBCC (#n-1)
a=B, O
a>Band O
a<B.The control bit of n Fredkin door is afterwards all the output O of OBCC (#n)
a<B, target bit is the output A of OBCC (#1) respectively
o (n-1)with output B
o (n-1), the output A of OBCC (#2)
o (n-2)with output B
o (n-2), the like, the target bit of the n-th Fredkin door is the output A of OBCC (#n)
o0with output B
o0.(1) as n bit A
i (n-1)a
i (n-2)a
i1a
i0be more than or equal to n bit B
i (n-1)b
i (n-2)b
i1b
i0time, the output of these two n bits equals their input, i.e. A
ok=A
ik, B
ok=B
ik(0≤k≤n-1, k is integer); (2) as n bit A
i (n-1)a
i (n-2)a
i1a
i0be less than n bit B
i (n-1)b
i (n-2)b
i1b
i0time, exchange the output of these two n bits, i.e. A
ok=B
ik, B
ok=A
ik(0≤k≤n-1, k is integer); (3) as n bit A
i (n-1)a
i (n-2)a
i1a
i0be greater than n bit B
i (n-1)b
i (n-2)b
i1b
i0time, O
a>B=1, O
a<B=0, O
a=B=0; (4) as n bit A
i (n-1)a
i (n-2)a
i1a
i0be less than n bit B
i (n-1)b
i (n-2)b
i1b
i0time, O
a<B=1, O
a>B=0, O
a=B=0; (5) as n bit A
i (n-1)a
i (n-2)a
i1a
i0equal n bit B
i (n-1)b
i (n-2)b
i1b
i0time, O
a=B=1, O
a>B=0, O
a<B=0.
A reversible complete comparator has 6 to input and 6 outputs, and by 4 NOT doors, 1 CNOT door, 2 Toffoli doors and 2 4-Toffoli gate leve connection construct.6 inputs are respectively 1 constant input, 0,51 input and are respectively I
a<B, I
a>B, I
a=B, A
inand B
in; 6 corresponding with it outputs are respectively 1 rubbish and export (GarbageOutput), O
a=B, O
a>B, O
a<B, A
outand B
out.First door is NOT door, and target bit is B
in; Second door is CNOT door, and control bit is I
a=B, target bit is constant input 0; 3rd door is 4-Toffoli door, and control bit is respectively I
a=B, A
inand B
in, target bit is I
a>B; 4th door is NOT door, and target bit is B
in; 5th door is NOT door, and target bit is A
in; 6th door is 4-Toffoli door, and control bit is respectively I
a=B, A
inand B
in, target bit is I
a<B; 7th door is NOT door, and target bit is A
in; 8th door is Toffoli door, and control bit is constant input 0 and I
a>B, target bit is I
a=B; 9th door is Toffoli door, and control bit is constant input 0 and I
a<B, target bit is I
a=B.
A reversible complete comparator:
For the comparison of multidigit binary numeral, according to binary number successively successive appraximation from a high position to low level.When each of two binary numbers is contrasted, need to consider that the magnitude relationship after a high comparison is to determine this comparative result, if a high position is than when going out the size of two numerical value, this is compared and becomes meaningless, only need to transmit high-order comparison result, namely transmit high-order O
a=B, O
a>Band O
a<Bnumerical value as this comparative result.Only have when the comparative result of high is equal, need to proceed this contrast, its magnitude relationship as shown in Table 1.
Table 1 comprises 1 bit magnitude relationship of high-order magnitude relationship
| A | B | |||||||||
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
Their logical relation is:
（1）
（2）
（3）
Because
a=Band O
a=Bbe in same input and output circuit, so need interpolation constant input position 0, copy
a=Binformation, according to equation (1), (2), (3), a reversible comparator is slightly made an amendment, a reversible complete comparator can be obtained, as shown in Figure 1:
Work as I
a>Bwhen=1, O
a>B=1, O
a<B=0, O
a=B=0;
Work as I
a<Bwhen=1, O
a<B=1, O
a>B=0, O
a=B=0;
Work as I
a=B=1, and A
in>B
intime, O
a>B=1, O
a<B=0, O
a=B=0;
Work as I
a=B=1, and A
in<B
intime, O
a<B=1, O
a>B=0, O
a=B=0;
Work as I
a=B=1, and A
in=B
intime, O
a=B=1, O
a>B=0, O
a<B=0.
Be the module map of a reversible complete comparator shown in Fig. 2, this reversible complete comparator has 6 inputs, comprises a constant input 0; 6 outputs, comprise a rubbish and export, and by 4 NOT doors, 1 CNOT door, 2 Toffoli doors and 2 4-Toffoli doors, totally 9 reversible gate leve connection form.
Universal reversible compares interchanger: as shown in Figure 2 one reversible complete comparator and fredkin door carry out cascade, generates Universal reversible and compares interchanger as shown in Figure 3.Because this Universal reversible compares interchanger, substantially to realize unit comparatively single, is conducive to fairly large cascade, generates the reversible numerical value comparison circuit in n position, only need to carry out expansion refinement according to the circuit structure rule in Fig. 3,32 can be realized, 64, even compare to 128 bit binary value.This Universal reversible compares interchanger and also has an outstanding feature, compares A and B two number, while obtaining comparative result, exports the initial value remaining binary number A and B, as A<B, exchanges the value of A and B.
Claims (2)
1. a Universal reversible compares interchanger, it is characterized in that: described Universal reversible compares interchanger and formed by a n reversible complete comparator and n Fredkin door cascade construction, this Universal reversible compares interchanger and inputs 0,1 constant input, 1,2 constant input, 0, two n bit A by n constant respectively
i (n-1), A
i (n-2)..., A
i0and B
i (n-1), B
i (n-2)..., B
i0formed, 3n+3 input altogether; Output corresponding is with it that n rubbish exports, O
a=B, O
a>B, O
a<B, and two n bit A
o (n-1), A
o (n-2)..., A
o0and B
o (n-1), B
o (n-2)..., B
o0, forming first device that this Universal reversible compares the cascade circuit of interchanger is first piece of reversible complete comparator, the input I of first piece one reversible complete comparator
a=B, I
a>Band I
a<Bbe set to 1,0 and 0 respectively; Second device is second piece of reversible complete comparator, the input I of second piece one reversible complete comparator
a=B, I
a>Band I
a<Bbe respectively the output O of first piece one reversible complete comparator
a=B, O
a>Band O
a<B, the rest may be inferred, and (n-1)th device is (n-1)th piece of reversible complete comparator, the input I of (n-1)th piece one reversible complete comparator
a=B, I
a>Band I
a<Bbe respectively the output O of the n-th-2 pieces one reversible complete comparator
a=B, O
a>Band O
a<B; N-th device is n-th piece of reversible complete comparator, the input I of n-th piece one reversible complete comparator
a=B, I
a>Band I
a<Bbe respectively the output O of (n-1)th piece one reversible complete comparator
a=B, O
a>Band O
a<B; The control bit of n Fredkin door is afterwards all the output O of n-th piece one reversible complete comparator
a<B, target bit is the output A of first piece one reversible complete comparator respectively
o (n-1)with output B
o (n-1), the output A of second piece one reversible complete comparator
o (n-2)with output B
o (n-2), the like, the target bit of the n-th Fredkin door is the output A of n-th piece one reversible complete comparator
o0with output B
o0.
2. Universal reversible according to claim 1 compares interchanger, it is characterized in that: a described reversible complete comparator has 6 to input and 6 outputs, a reversible complete comparator by 4 NOT doors, 1 CNOT door, 2 Toffoli doors and 2 4-Toffoli gate leves connection construct; 6 inputs are respectively 1 constant input, 0,51 input and are respectively I
a<B, I
a>B, I
a=B, A
inand B
in; 6 corresponding with it outputs are respectively 1 rubbish output, O
a=B, O
a>B, O
a<B, A
outand B
out; First door is NOT door, and target bit is B
in; Second door is CNOT door, and control bit is I
a=B, target bit is constant input 0; 3rd door is 4-Toffoli door, and control bit is respectively I
a=B, A
inand B
in, target bit is I
a>B; 4th door is NOT door, and target bit is B
in; 5th door is NOT door, and target bit is A
in; 6th door is 4-Toffoli door, and control bit is respectively I
a=B, A
inand B
in, target bit is I
a<B; 7th door is NOT door, and target bit is A
in; 8th door is Toffoli door, and control bit is constant input 0 and I
a>B, target bit is I
a=B; 9th door is Toffoli door, and control bit is constant input 0 and I
a<B, target bit is I
a=B.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521504A (en) * | 2009-04-13 | 2009-09-02 | 南通大学 | Implementation method for reversible logic unit used for low power consumption encryption system |
| CN101783672A (en) * | 2010-02-09 | 2010-07-21 | 南通大学 | Four-bit reversible digital comparator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521504A (en) * | 2009-04-13 | 2009-09-02 | 南通大学 | Implementation method for reversible logic unit used for low power consumption encryption system |
| CN101783672A (en) * | 2010-02-09 | 2010-07-21 | 南通大学 | Four-bit reversible digital comparator |
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