CN112751663B - A data encryption method and device - Google Patents

Abstract

The invention discloses a data encryption method and a data encryption device, and relates to a double-track domino logic gate structure, wherein the method comprises the following steps: receiving input data to be encrypted, and dividing the data to be encrypted into four paths of input data; when the preset PC signal is a high-level signal, executing exclusive OR operation by adopting the second path of input data, the third path of input data, the fourth path of input data and the variable round key to obtain an operation result; when the operation result is valid, converting the PC signal into a low-level signal through a double-track domino logic gate structure; generating a first path of encryption result according to the operation result and the first path of input data; executing four paths of input data updating operation; after the above operations are repeatedly executed 32 times, the four paths of input data are subjected to reverse order transformation to obtain four paths of output data, and the four paths of output data are merged to generate encrypted data. The method improves the speed of the encryption process, and simultaneously reduces the encryption power consumption and improves the encryption safety due to the addition of the domino logic gate structure.

Description

A data encryption method and device

technical field

The invention relates to the technical field of data encryption, in particular to a data encryption method and device.

Background technique

Today is the era of rapid development of information technology, the Internet is rapidly becoming the carrier of all walks of life, promoting the progress of the industry, and the Internet of Things, as the basic medium and pioneer of Internet applications, greatly improves the efficiency of industry production and people's lives. Its application is known as the third wave of the development of the world's information industry after computers and the Internet. Therefore, the security of the Internet of Things has also attracted people's attention.

With the rapid development of integrated circuit manufacturing technology, SoC came into being. SoC has greatly reduced the size of the system and improved the performance of the system; SoC has been more and more widely used for its advantages of high integration, small size, low power consumption, good reliability, and short product launch cycle. However, some products in the current market use software encryption, resulting in slow data encryption and long cycle times. At the same time, some products are encrypted entirely by hardware. Although the speed is fast, the chip area is large and the power consumption is high, which cannot meet the requirements Low power requirements for networking products. At the same time, almost most of the products on the market store the key in non-volatile memory, which is vulnerable to intrusive attacks, resulting in the key being copied and stolen. These problems seriously restrict the popularization and development of the Internet of Things, and bring great security risks to the products of the Internet of Things.

Contents of the invention

The present invention provides a data encryption method and device, which solves the problems of slow encryption speed caused by software defects, high power consumption caused by hardware encryption, and potential safety hazards caused by key storage methods in the existing data encryption method technical problem.

A data encryption method provided by the present invention relates to a double-track domino logic gate structure, the method comprising:

Receive the data to be encrypted input by the user, and divide the data to be encrypted into four input data on average; wherein, the four input data include the first input data, the second input data, the third input data and The fourth input data;

When the preset PC signal is a high-level signal, the XOR operation is performed using the second input data, the third input data, the fourth input data and the preset variable round key , get the operation result;

When the operation result is valid, the PC signal is converted into a low-level signal through the double-track domino logic gate structure;

generating a first encryption result according to the operation result and the first input data;

Perform four input data update operations;

Returning to the step of receiving the data to be encrypted input by the user, and dividing the data to be encrypted into four input data on average, until the update operation of the four input data is performed 32 times;

performing inverse transformation on the first path of input data, the second path of input data, the third path of input data, and the fourth path of input data to obtain four paths of output data;

Combine the output data of the four channels to generate encrypted data.

Optionally, after the step of performing the four-way input data update operation, the method further includes:

A round key different from the variable round key is selected from a preset round key group as a new variable round key.

Optionally, the step of generating the first encryption result according to the operation result and the first input data includes:

performing a synthetic permutation operation on the operation result by using a preset reversible transformation algorithm to generate an intermediate result;

Executing an XOR operation with the intermediate result and the first path of input data to generate a first path of encryption result.

Optionally, the step of performing the four-way input data update operation includes:

updating the first input data by using the second input data;

updating the second input data by using the third input data;

updating the third input data by using the fourth input data;

The fourth path of input data is updated by using the encryption result of the first path.

Optionally, after the step of converting the PC signal into a low-level signal through the double-track domino logic gate structure when the operation result is valid, the method further includes:

The low-level signal is returned to the double-track domino logic gate structure of the upper stage, so that the operation result corresponding to the double-track domino logic gate structure of the upper stage is valid.

The present invention also provides a data encryption device, which relates to a double-track domino logic gate structure, and the device includes:

The input data division module is used to receive the data to be encrypted input by the user, and divide the data to be encrypted into four input data on average; wherein, the four input data includes the first input data and the second input data , the third input data and the fourth input data;

An operation result generating module, configured to use the second input data, the third input data, the fourth input data and the preset variable input data when the preset PC signal is a high-level signal. The round key performs an XOR operation to obtain the operation result;

A low-level signal conversion module, configured to convert the PC signal into a low-level signal through the double-track domino logic gate structure when the operation result is valid;

A first encryption result generating module, configured to generate a first encryption result according to the operation result and the first input data;

A data update module, configured to perform four input data update operations;

Repeating the execution module for returning the received data to be encrypted input by the user, and dividing the to-be-encrypted data into four input data on average, until the update operation of the four input data is executed 32 times;

A four-way output data generation module, configured to perform inverse transformation on the first line of input data, the second line of input data, the third line of input data, and the fourth line of input data to obtain four lines of output data;

The encrypted data generating module is used to combine the output data of the four channels to generate encrypted data.

Optionally, the device also includes:

The round key reselection module is used to select a round key different from the variable round key from the preset round key group as a new variable round key.

Optionally, the first-way encryption result generation module includes:

The intermediate result generation sub-module is used to perform a synthetic permutation operation on the operation result by using a preset reversible transformation algorithm to generate an intermediate result;

The first encryption result generation sub-module is used to perform XOR operation with the intermediate result and the first input data to generate the first encryption result.

Optionally, the data update module includes:

The first input data updating submodule is used to update the first input data by using the second input data;

The second input data update submodule is configured to update the second input data by using the third input data;

A third input data updating submodule, configured to use the fourth input data to update the third input data;

The fourth input data update sub-module is configured to update the fourth input data by using the first encryption result.

Optionally, the device also includes:

The signal return module is used to return the low-level signal to the double-track domino logic gate structure of the upper stage, so that the operation result corresponding to the double-track domino logic gate structure of the upper stage is valid.

As can be seen from the above technical solutions, the present invention has the following advantages:

In the present invention, by receiving the data to be encrypted input by the user and dividing it into four-way data, the three-way data except the first-way data and the preset variable round key are subjected to XOR operation to obtain the operation result; when the operation result is valid At this time, the PC signal is converted into a low-level signal through the double-track domino logic gate structure, and then the first encryption result is generated according to the XOR operation between the operation result and the first input data, and the four input data update operations are performed, and repeated After 31 times, perform reverse transformation on the four channels of data to obtain four channels of output data; finally combine the four channels of output data to generate encrypted data. The method improves the speed of the encryption process, and at the same time reduces the encryption power consumption and improves the encryption security due to the addition of the domino logic gate structure.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings on the premise of not paying creative efforts.

Fig. 1 is a flow chart of the steps of a data encryption method provided by an embodiment of the present invention;

2 is a schematic diagram of an XOR structure of a dual-track domino logic gate in an embodiment of the present invention;

Fig. 3 is the AND gate structure schematic diagram of the dual-track domino logic gate in the embodiment of the present invention;

FIG. 4 is a flowchart of steps of a data encryption method provided by an optional embodiment of the present invention;

FIG. 5 is a data flow diagram of a data encryption device provided by an embodiment of the present invention;

Fig. 6 is a structural block diagram of a data encryption device provided by an embodiment of the present invention.

detailed description

With the popularization and application of wireless area network standards, my country has independently designed the SM4 symmetric block cipher algorithm. This algorithm has fast encryption and decryption speed, simple hardware implementation and certain security. It is mostly suitable for making cryptographic chips, and has been widely used in Protection of important data in the financial field and the Internet of Things. Therefore, it is far from enough to judge the security of cryptographic algorithms simply by studying the structure of cryptographic algorithms. We must also consider the speed of operation and power consumption design from the perspective of cryptographic algorithm implementation, which can greatly improve the quality of chips. Therefore, the embodiment of the present invention provides a data encryption method and device, which are used to solve the problem of slow encryption speed caused by software defects, high power consumption caused by hardware encryption, and problems caused by key storage methods in existing data encryption methods. A technical issue that presents a safety hazard.

In order to make the purpose, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the following The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to FIG. 1 . FIG. 1 is a flowchart of steps of a data encryption method provided by an embodiment of the present invention.

A data encryption method provided by the present invention relates to a double-track domino logic gate structure, the method comprising:

Step 101, receiving the data to be encrypted input by the user, and dividing the data to be encrypted into four input data on average;

Wherein, the four input data include the first input data, the second input data, the third input data and the fourth input data;

Step 102, when the preset PC signal is a high-level signal, use the second input data, the third input data, the fourth input data and the preset variable round key to execute XOR operation to obtain the operation result;

Step 103, when the operation result is valid, convert the PC signal into a low-level signal through the double-track domino logic gate structure;

In the embodiment of the present invention, the domino logic gate refers to a type of dynamic circuit in which a static inverter is inserted between the dynamic logic gates to avoid premature discharge when the dynamic logic gates are directly cascaded. It is called domino logic because the circuit state changes are propagated sequentially among the stages of the cascade, like dominoes. The dual-track domino logic gate refers to a design in the form of synchronous dual channels on the domino logic gate to reduce hardware resource consumption and power consumption.

Please refer to FIG. 2 . FIG. 2 shows a schematic diagram of an XOR structure of a dual-track domino logic gate in an embodiment of the present invention, which includes a plurality of field effect transistors, PC represents a precharge signal, and q_t and a_f represent output signals. When the PC signal is 0, both the output terminals q_t and q_f are 0 signals, indicating that the output signal is invalid; when the PC signal is 1, the output terminals q_t and q_f are both 1 signals, indicating that the output signal is valid.

Please refer to FIG. 3 . FIG. 3 shows a schematic diagram of an AND gate structure of a dual-track domino logic gate in an embodiment of the present invention, which includes a plurality of field effect transistors, PC represents a precharge signal, and q_t and a_f represent output signals. When the PC signal is 0, both the output terminals q_t and q_f are 0 signals, indicating that the output signal is invalid; when the PC signal is 1, the output terminals q_t and q_f are both 1 signals, indicating that the output signal is valid.

Step 104, generating a first encryption result according to the operation result and the first input data;

Step 105, performing four-way input data update operations;

Step 106, returning to the step of receiving the data to be encrypted input by the user, and dividing the data to be encrypted into four input data on average, until the update operation of the four input data is performed 32 times;

Step 107, performing inverse transformation on the first path of input data, the second path of input data, the third path of input data, and the fourth path of input data to obtain four paths of output data;

The reverse transformation refers to reconstructing the object through deserialization according to the state and description information of the object stored in the byte stream. For example, the ciphertext C=(Y0, Y1, Y2, Y3)=R(X32.X33, X34, X35)=(X35, X34, X33, X32).

Step 108, combining the output data of the four channels to generate encrypted data.

In the embodiment of the present invention, by receiving the data to be encrypted input by the user and dividing it into four channels of data, the three channels of data except the first channel of data are subjected to XOR operation with the preset variable round key to obtain the operation result ; When the operation result is valid, the PC signal is converted into a low-level signal through the double-track domino logic gate structure, and then the first encryption result is generated according to the XOR operation of the operation result and the first input data, and four input channels are executed. After the data update operation is repeated 31 times, the four channels of data are reversed to obtain four channels of output data; finally, the four channels of output data are combined to generate encrypted data. The method improves the speed of the encryption process, and at the same time reduces the encryption power consumption and improves the encryption security due to the addition of the domino logic gate structure.

Please refer to FIG. 4 . FIG. 4 is a flowchart of steps of a data encryption method provided by an embodiment of the present invention.

A data encryption method provided by the present invention relates to a double-track domino logic gate structure, the method comprising:

Step 401, receiving the data to be encrypted input by the user, and dividing the data to be encrypted into four input data on average; wherein, the four input data includes the first input data, the second input data, the third input data input data and the fourth input data;

In the embodiment of the present invention, the logic gates of each round of data encryption are controlled by the signal PC. When the circuit starts to work for the first time, all PC signals must be reset to zero for a period of time to pre-charge the circuit, and then the PC The signal transitions high, awaiting the computation of valid data.

Step 402, when the preset PC signal is a high-level signal, use the second input data, the third input data, the fourth input data and the preset variable round key to execute XOR operation to obtain the operation result;

In a specific implementation, taking the second input data X1, the third input data X2 and the fourth input data X3 as examples, the operation result X can be calculated by the following formula:

where rki refers to the variable round key of the i-th round.

Step 403, when the operation result is valid, convert the PC signal into a low-level signal through the double-track domino logic gate structure;

In the embodiment of the present invention, if the operation result is valid, the PC signal of the double-track domino logic gate structure is converted into a low-level signal to start the encryption process and encrypt the first input data.

Step 404 , returning the low-level signal to the double-track domino logic gate structure of the upper stage, so that the operation result corresponding to the double-track domino logic gate structure of the upper stage is valid.

In the specific implementation, when multiple data need to be encrypted in the pipeline, it is necessary to precharge the previous round of circuits. At this time, the low-level signal can be returned to the result of the upper-level double-track domino logic gate to ensure that the upper-level The operation results corresponding to the double-track domino logic gate structure are valid.

Step 405, generating a first encryption result according to the operation result and the first input data;

Further, the step 405 may include the following sub-steps:

performing a synthetic permutation operation on the operation result by using a preset reversible transformation algorithm to generate an intermediate result;

Executing an XOR operation with the intermediate result and the first path of input data to generate a first path of encryption result.

In an example of the present invention, a reversible transformation algorithm is used to perform a composite permutation operation on the operation result to obtain an intermediate result, and an XOR operation is performed on the intermediate result and the first input data to generate the first encryption result.

Among them, the reversible transformation algorithm refers to the invertible linear transformation (invertible linear transformation), also known as non-degenerate linear transformation, or full-rank linear transformation, which is a special kind of linear transformation. Let V be the linear space on the number field P, and σ be The linear transformation of V, if there is a transformation τ of V, so that στ=τσ=I, where I is the unit transformation, then σ is called a reversible linear transformation, τ is called the inverse transformation of σ, and the reversible linear transformation on V is the inverse of σ The transformation is still the linear transformation of V, and it is unique, denoted as σ ^-1 .

The synthetic permutation operation refers to a reversible transformation, which is composed of a nonlinear transformation r and a linear transformation L, that is, T(a)=L(r(a)), and a is the operation result.

Step 406, execute four input data update operations;

In the embodiment of the present invention, the step 406 may include the following sub-steps:

updating the first input data by using the second input data;

updating the second input data by using the third input data;

updating the third input data by using the fourth input data;

The fourth path of input data is updated by using the encryption result of the first path.

Optionally, after step 406, the method further includes:

A round key different from the variable round key is selected from a preset round key group as a new variable round key.

以得到

In the embodiment of the present invention, the length of the encryption key is 128 bits, expressed as MK=(MK0, MK1, MK2, MK3), wherein MKi is 32 bits, and the variable round key is expressed as (rk0, rk1,... , rk31), where rki is 32 bits. Can be extended via the key method: set

to get

Step 407, returning to the step of receiving the data to be encrypted input by the user, and dividing the data to be encrypted into four input data on average, until the update operation of the four input data is performed 32 times;

Step 408, performing inverse transformation on the first path of input data, the second path of input data, the third path of input data, and the fourth path of input data to obtain four paths of output data;

Step 409, combining the output data of the four channels to generate encrypted data.

In the embodiment of the present invention, by receiving the data to be encrypted input by the user and dividing it into four channels of data, the three channels of data except the first channel of data are subjected to XOR operation with the preset variable round key to obtain the operation result ; When the operation result is valid, the PC signal is converted into a low-level signal through the double-track domino logic gate structure, and then the first encryption result is generated according to the XOR operation of the operation result and the first input data, and four input channels are executed. After the data update operation is repeated 31 times, the four channels of data are reversed to obtain four channels of output data; finally, the four channels of output data are combined to generate encrypted data. The method improves the speed of the encryption process, and at the same time reduces the encryption power consumption and improves the encryption security due to the addition of the domino logic gate structure.

Please refer to FIG. 5 , which shows a data flow chart of a data encryption device according to an embodiment of the present invention.

By inputting 128bit plaintext X to be encrypted, it is divided into four input data X0, X1, X2 and X3. After entering Round ₁ , XOR operation is performed through X1, X2, X3 and rk1, and the operation result is obtained through detect The circuit (that is, the result of the dual-way domino logic gate) outputs the PC signal, and after performing the synthetic replacement operation T, it performs an XOR operation with X0 to generate the first encrypted data, and then updates each input data, using X0 as X4 and Shift, and so on, until the 32-round data encryption process is completed, the four channels of data are changed in reverse order, combined, and the 128-bit encrypted data Ciphertext Y is output.

Please refer to FIG. 6, which shows a structural block diagram of a data encryption device according to an embodiment of the present invention.

The present invention also provides a data encryption device, which relates to a double-track domino logic gate structure, and the device includes:

The input data division module 601 is configured to receive the data to be encrypted input by the user, and divide the data to be encrypted into four input data on average; wherein, the four input data include the first input data, the second input data data, the third input data and the fourth input data;

The calculation result generating module 602 is used to use the second input data, the third input data, the fourth input data and the preset possible input data when the preset PC signal is a high level signal. The wheel-changing key performs an XOR operation to obtain the operation result;

A low-level signal conversion module 603, configured to convert the PC signal into a low-level signal through the double-track domino logic gate structure when the operation result is valid;

A first-pass encryption result generating module 604, configured to generate a first-pass encryption result according to the operation result and the first-pass input data;

A data update module 605, configured to perform four input data update operations;

Repeat the execution module 606, for returning the step of receiving the data to be encrypted input by the user, and dividing the data to be encrypted into four input data on average, until the update operation of the four input data is executed 32 times;

The four-way output data generation module 607 is configured to perform inverse transformation on the first line of input data, the second line of input data, the third line of input data, and the fourth line of input data to obtain four lines Output Data;

The encrypted data generating module 608 is configured to combine the output data of the four channels to generate encrypted data.

Optionally, the device also includes:

The round key reselection module is used to select a round key different from the variable round key from the preset round key group as a new variable round key.

Optionally, the first-pass encryption result generating module 604 includes:

The intermediate result generation sub-module is used to perform a synthetic permutation operation on the operation result by using a preset reversible transformation algorithm to generate an intermediate result;

The first encryption result generation sub-module is used to perform XOR operation with the intermediate result and the first input data to generate the first encryption result.

Optionally, the data update module 605 includes:

The first input data updating submodule is used to update the first input data by using the second input data;

The second input data update submodule is configured to update the second input data by using the third input data;

A third input data updating submodule, configured to use the fourth input data to update the third input data;

The fourth input data update sub-module is configured to update the fourth input data by using the first encryption result.

Optionally, the device also includes:

The signal return module is used to return the low-level signal to the double-track domino logic gate structure of the upper stage, so that the operation result corresponding to the double-track domino logic gate structure of the upper stage is valid.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the device described above can refer to the corresponding process in the foregoing method embodiment, and details are not repeated here.

In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions recorded in each embodiment are modified, or some of the technical features are replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. A method of data encryption involving a dual-rail domino logic gate structure, the method comprising:

receiving data to be encrypted input by a user, and averagely dividing the data to be encrypted into four paths of input data; the four paths of input data comprise first path of input data, second path of input data, third path of input data and fourth path of input data;

when the preset PC signal is a high-level signal, performing exclusive-or operation by adopting the second path of input data, the third path of input data, the fourth path of input data and a preset variable round key to obtain an operation result;

when the operation result is valid, converting the PC signal into a low-level signal through the double-track domino logic gate structure;

generating a first path of encryption result according to the operation result and the first path of input data;

executing four paths of input data updating operation;

returning to the step of receiving the data to be encrypted input by the user and averagely dividing the data to be encrypted into four paths of input data until the four paths of input data are updated for 32 times;

performing reverse order transformation on the first path of input data, the second path of input data, the third path of input data and the fourth path of input data to obtain four paths of output data;

and combining the four paths of output data to generate encrypted data.

2. A data encryption method according to claim 1, wherein after said step of performing a four-way input data update operation, said method further comprises:

and selecting a round key different from the variable round key from a preset round key group as a new variable round key.

3. The data encryption method according to claim 1, wherein the step of generating the first encryption result according to the operation result and the first input data comprises:

adopting a preset reversible transformation algorithm to perform synthesis and replacement operation on the operation result to generate an intermediate result;

and executing exclusive-or operation by adopting the intermediate result and the first path of input data to generate a first path of encryption result.

4. The method of claim 1, wherein the step of performing a four-way input data update operation comprises:

updating the first path of input data by adopting the second path of input data;

updating the second path of input data by adopting the third path of input data;

updating the third path of input data by adopting the fourth path of input data;

and updating the fourth path of input data by adopting the first path of encryption result.

5. The method of claim 1, wherein after said step of converting said PC signal to a low signal via said dual-rail domino logic gate structure when said operation result is valid, said method further comprises:

and returning the low-level signal to the upper-stage double-rail domino logic gate structure, so that the operation result corresponding to the upper-stage double-rail domino logic gate structure is valid.

6. A data encryption apparatus, relating to a dual-rail domino logic gate structure, the apparatus comprising:

the device comprises an input data dividing module, a data processing module and a data processing module, wherein the input data dividing module is used for receiving data to be encrypted input by a user and averagely dividing the data to be encrypted into four paths of input data; the four paths of input data comprise a first path of input data, a second path of input data, a third path of input data and a fourth path of input data;

the operation result generating module is used for executing exclusive or operation by adopting the second path of input data, the third path of input data, the fourth path of input data and a preset variable round key when a preset PC signal is a high-level signal to obtain an operation result;

the low-level signal conversion module is used for converting the PC signal into a low-level signal through the double-track domino logic gate structure when the operation result is valid;

the first path encryption result generation module is used for generating a first path encryption result according to the operation result and the first path input data;

the data updating module is used for executing four paths of input data updating operation;

the repeated execution module is used for returning the data to be encrypted input by the receiving user and averagely dividing the data to be encrypted into four paths of input data until the four paths of input data updating operation are executed for 32 times;

a four-path output data generating module, configured to perform reverse order transformation on the first path of input data, the second path of input data, the third path of input data, and the fourth path of input data, so as to obtain four paths of output data;

and the encrypted data generation module is used for combining the four paths of output data to generate encrypted data.

7. A data encryption apparatus according to claim 6, said apparatus further comprising:

and the round key reselection module is used for selecting a round key different from the variable round key from a preset round key group as a new variable round key.

8. The data encryption device according to claim 6, wherein the first encryption result generating module comprises:

the intermediate result generation submodule is used for executing synthesis and replacement operation on the operation result by adopting a preset reversible transformation algorithm to generate an intermediate result;

and the first path encryption result generation submodule is used for executing exclusive or operation by adopting the intermediate result and the first path input data to generate a first path encryption result.

9. The apparatus of claim 6, wherein the data update module comprises:

the first path of input data updating submodule is used for updating the first path of input data by adopting the second path of input data;

the second path input data updating submodule is used for updating the second path input data by adopting the third path input data;

a third path input data updating submodule, configured to update the third path input data with the fourth path input data;

and the fourth path input data updating submodule is used for updating the fourth path input data by adopting the first path encryption result.

10. A data encryption apparatus according to claim 6, characterized in that said apparatus further comprises:

and the signal returning module is used for returning the low-level signal to the upper-stage double-track domino logic gate structure so that an operation result corresponding to the upper-stage double-track domino logic gate structure is effective.

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