CN112751663A - Data encryption method and device - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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- Y02D30/00—Reducing energy consumption in communication networks
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Abstract
本发明公开了一种数据加密方法和装置，涉及双轨道多米诺逻辑门结构，方法包括：接收输入的待加密数据，并将待加密数据划分为四路输入数据；当预置的PC信号为高电平信号时，采用第二路输入数据、第三路输入数据、第四路输入数据与可变轮密钥执行异或运算，得到运算结果；当运算结果有效时，通过双轨道多米诺逻辑门结构将PC信号转换为低电平信号；根据运算结果与第一路输入数据，生成第一路加密结果；执行四路输入数据更新操作；重复执行32次上述操作后，对四路输入数据执行反序变换，得到四路输出数据并合并生成加密数据。该方法提高了加密过程的速度，同时由于多米诺逻辑门结构的加入，降低加密功耗，提高加密安全性。
The invention discloses a data encryption method and device, and relates to a dual-track domino logic gate structure. The method includes: receiving input data to be encrypted, and dividing the data to be encrypted into four channels of input data; when a preset PC signal is high When the level signal is used, the second input data, the third input data, the fourth input data and the variable round key are used to perform the XOR operation to obtain the operation result; when the operation result is valid, the dual-track domino logic gate is used. The structure converts the PC signal into a low-level signal; generates the first encryption result according to the operation result and the first input data; performs four input data update operations; after repeating the above operations for 32 times, executes the four input data. Reverse sequence transformation to obtain four output data and combine to generate encrypted data. The method improves the speed of the encryption process, and at the same time, because of the addition of the domino logic gate structure, the encryption power consumption is reduced and the encryption security is improved.
Description
Technical Field
The present invention relates to the field of data encryption technologies, and in particular, to a data encryption method and apparatus.
Background
At present, in the era of high-speed development of information technology, the internet is rapidly becoming a carrier of all industries and promoting the progress of the industries, and the internet of things is used as a basic medium and a pioneer for improving the application of the internet, so that the efficiency of industrial production and life of people is greatly improved. The application of the method is called as the third wave of development of the world information industry after computers and the Internet, so that the safety problem of the Internet of things is concerned by people.
With the rapid development of integrated circuit manufacturing processes, SoC of system on chip is in operation. The SoC greatly reduces the system volume and improves the system performance; SoC is more and more widely used due to its advantages of high integration level, small volume, low power consumption, good reliability, short product appearance period, etc. However, some products in the current market adopt a software encryption mode, so that the data encryption speed is low, the period is long, meanwhile, some products are completely encrypted by hardware, although the speed is high, the chip area is large, the power consumption is high, and the low-power-consumption requirement of the product of the internet of things cannot be met. Meanwhile, most products in the market store the key in a nonvolatile memory, so that the key is easily attacked in an intrusive way, and the key is copied and stolen. The problems seriously restrict the popularization and development of the Internet of things and bring great potential safety hazard to products of the Internet of things.
Disclosure of Invention
The invention provides a data encryption method and a data encryption device, which solve the technical problems of low encryption speed caused by software defects, high power consumption caused by hardware encryption and potential safety hazard caused by a secret key storage mode in the conventional data encryption method.
The invention provides a data encryption method, which relates to a double-track domino logic gate structure, and comprises the following steps:
receiving data to be encrypted input by a user, and averagely dividing the data to be encrypted into four paths of input data; the four paths of input data comprise a first path of input data, a second path of input data, a third path of input data and a fourth path of input data;
when the preset PC signal is a high-level signal, performing exclusive-or operation by adopting the second path of input data, the third path of input data, the fourth path of input data and a preset variable round key to obtain an operation result;
when the operation result is valid, converting the PC signal into a low-level signal through the double-track domino logic gate structure;
generating a first path of encryption result according to the operation result and the first path of input data;
executing four paths of input data updating operation;
returning to the step of receiving the data to be encrypted input by the user and averagely dividing the data to be encrypted into four paths of input data until the four paths of input data are updated for 32 times;
performing reverse order transformation on the first path of input data, the second path of input data, the third path of input data and the fourth path of input data to obtain four paths of output data;
and combining the four paths of output data to generate encrypted data.
Optionally, after the step of performing four-way input data update operation, the method further comprises:
and selecting a round key different from the variable round key from a preset round key group as a new variable round key.
Optionally, the step of generating a first path encryption result according to the operation result and the first path input data includes:
adopting a preset reversible transformation algorithm to perform synthesis and replacement operation on the operation result to generate an intermediate result;
and executing XOR operation by adopting the intermediate result and the first path of input data to generate a first path of encryption result.
Optionally, the step of performing four-way input data update operation includes:
updating the first path of input data by adopting the second path of input data;
updating the second path of input data by adopting the third path of input data;
updating the third path of input data by adopting the fourth path of input data;
and updating the fourth path of input data by adopting the first path of encryption result.
Optionally, after the step of converting the PC signal to a low signal through the dual-rail domino logic gate structure when the operation result is valid, the method further comprises:
and returning the low-level signal to the upper-stage double-rail domino logic gate structure, so that the operation result corresponding to the upper-stage double-rail domino logic gate structure is valid.
The invention also provides a data encryption device, which relates to a double-track domino logic gate structure, and the device comprises:
the device comprises an input data dividing module, a data processing module and a data processing module, wherein the input data dividing module is used for receiving data to be encrypted input by a user and averagely dividing the data to be encrypted into four paths of input data; the four paths of input data comprise a first path of input data, a second path of input data, a third path of input data and a fourth path of input data;
the operation result generating module is used for executing exclusive or operation by adopting the second path of input data, the third path of input data, the fourth path of input data and a preset variable round key when a preset PC signal is a high-level signal to obtain an operation result;
the low level signal conversion module is used for converting the PC signal into a low level signal through the double-track domino logic gate structure when the operation result is valid;
the first path encryption result generation module is used for generating a first path encryption result according to the operation result and the first path input data;
the data updating module is used for executing four paths of input data updating operation;
the repeated execution module is used for returning the data to be encrypted input by the receiving user and averagely dividing the data to be encrypted into four paths of input data until the four paths of input data are updated for 32 times;
a four-path output data generating module, configured to perform reverse order transformation on the first path of input data, the second path of input data, the third path of input data, and the fourth path of input data to obtain four paths of output data;
and the encrypted data generation module is used for combining the four paths of output data to generate encrypted data.
Optionally, the apparatus further comprises:
and the round key reselection module is used for selecting a round key different from the variable round key from a preset round key group as a new variable round key.
Optionally, the first path encryption result generating module includes:
the intermediate result generation submodule is used for executing synthesis and replacement operation on the operation result by adopting a preset reversible transformation algorithm to generate an intermediate result;
and the first path encryption result generation submodule is used for executing exclusive or operation by adopting the intermediate result and the first path input data to generate a first path encryption result.
Optionally, the data updating module includes:
the first path input data updating submodule is used for updating the first path input data by adopting the second path input data;
the second path of input data updating submodule is used for updating the second path of input data by adopting the third path of input data;
a third path input data updating submodule, configured to update the third path input data with the fourth path input data;
and the fourth path input data updating submodule is used for updating the fourth path input data by adopting the first path encryption result.
Optionally, the apparatus further comprises:
and the signal returning module is used for returning the low-level signal to the upper-stage double-rail domino logic gate structure so that an operation result corresponding to the upper-stage double-rail domino logic gate structure is effective.
According to the technical scheme, the invention has the following advantages:
receiving data to be encrypted input by a user and dividing the data into four paths of data, and executing XOR operation on the three paths of data except the first path of data and a preset variable round key to obtain an operation result; when the operation result is valid, converting the PC signal into a low level signal through a double-track domino logic gate structure, generating a first path of encryption result according to the XOR operation of the operation result and first path of input data, executing four paths of input data updating operation, repeating for 31 times, and then executing reverse order transformation on the four paths of data to obtain four paths of output data; and finally combining the four paths of output data to generate encrypted data. The method improves the speed of the encryption process, and simultaneously reduces the encryption power consumption and improves the encryption safety due to the addition of the domino logic gate structure.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a flowchart illustrating steps of a data encryption method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an XOR structure of a dual-rail domino logic gate according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an AND gate structure of a dual-rail domino logic gate according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating steps of a method for encrypting data according to an alternative embodiment of the present invention;
fig. 5 is a data flow chart of a data encryption apparatus according to an embodiment of the present invention;
fig. 6 is a block diagram of a data encryption apparatus according to an embodiment of the present invention.
Detailed Description
With the popularization and application of the wireless local area network standard, China autonomously designs an SM4 symmetric block cipher algorithm, the algorithm is high in encryption and decryption speed, simple in hardware implementation and certain in safety, is mostly suitable for manufacturing cipher chips, and is widely applied to protection of important data in the financial field, the Internet of things and the like. Therefore, the safety of the cryptographic algorithm is far from being judged only by researching the structure of the cryptographic algorithm, and the operation speed and power consumption design must be considered from the implementation angle of the cryptographic algorithm, so that the quality of a chip can be greatly improved. Therefore, the embodiment of the invention provides a data encryption method and a data encryption device, which are used for solving the technical problems of low encryption speed caused by software defects, high power consumption caused by hardware encryption and potential safety hazards caused by a key storage mode in the conventional data encryption method.
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating steps of a data encryption method according to an embodiment of the present invention.
The invention provides a data encryption method, which relates to a double-track domino logic gate structure, and comprises the following steps:
step 101, receiving data to be encrypted input by a user, and averagely dividing the data to be encrypted into four paths of input data;
the four paths of input data comprise a first path of input data, a second path of input data, a third path of input data and a fourth path of input data;
102, when the preset PC signal is a high-level signal, performing an exclusive-or operation by using the second path of input data, the third path of input data, the fourth path of input data and a preset variable round key to obtain an operation result;
103, when the operation result is valid, converting the PC signal into a low-level signal through the double-rail domino logic gate structure;
in the embodiment of the invention, the domino logic gate refers to a dynamic circuit which is inserted with a static reverser between dynamic logic gates to avoid generating premature discharge when the dynamic logic gates are directly cascaded. Circuit state changes are referred to as domino logic because they propagate sequentially between cascaded stages, like domino. The double-track domino logic gate is designed in a synchronous double-path mode on the domino logic gate so as to reduce hardware resource loss and power consumption.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating an xor structure of a dual-rail domino logic gate according to an embodiment of the present invention, wherein the xor structure includes a plurality of fets, PC represents a precharge signal, and q _ t and a _ f represent output signals. When the PC signal is 0, the output ends q _ t and q _ f are both 0 signals, which indicates that the output signals are invalid; when the PC signal is 1, the output terminals q _ t and q _ f are both 1 signals, indicating that the output signal is valid.
Referring to fig. 3, fig. 3 is a schematic diagram of an and gate structure of a dual-rail domino logic gate according to an embodiment of the present invention, wherein the and gate structure includes a plurality of fets, PC represents a precharge signal, and q _ t and a _ f represent output signals. When the PC signal is 0, the output ends q _ t and q _ f are both 0 signals, which indicates that the output signals are invalid; when the PC signal is 1, the output terminals q _ t and q _ f are both 1 signals, indicating that the output signal is valid.
104, generating a first path of encryption result according to the operation result and the first path of input data;
the reverse order transformation refers to reconstructing the object through reverse serialization according to the object state and the description information stored in the byte stream. For example, ciphertext C ═ Y0, Y1, Y2, Y3 ═ R (X32.X33, X34, X35) ═ X35, X34, X33, X32.
And step 108, combining the four paths of output data to generate encrypted data.
In the embodiment of the invention, the data to be encrypted input by a user is received and divided into four paths of data, and the three paths of data except the first path of data and a preset variable round key are subjected to XOR operation to obtain an operation result; when the operation result is valid, converting the PC signal into a low level signal through a double-track domino logic gate structure, generating a first path of encryption result according to the XOR operation of the operation result and first path of input data, executing four paths of input data updating operation, repeating for 31 times, and then executing reverse order transformation on the four paths of data to obtain four paths of output data; and finally combining the four paths of output data to generate encrypted data. The method improves the speed of the encryption process, and simultaneously reduces the encryption power consumption and improves the encryption safety due to the addition of the domino logic gate structure.
Referring to fig. 4, fig. 4 is a flowchart illustrating steps of a data encryption method according to an embodiment of the present invention.
The invention provides a data encryption method, which relates to a double-track domino logic gate structure, and comprises the following steps:
step 401, receiving data to be encrypted input by a user, and averagely dividing the data to be encrypted into four paths of input data; the four paths of input data comprise a first path of input data, a second path of input data, a third path of input data and a fourth path of input data;
in the embodiment of the invention, the logic gate of each round of data encryption is controlled by the signal PC, when the circuit starts to work for the first time, all PC signals must be reset to zero for a period of time to pre-charge the circuit, and then the PC signals are converted into high level to wait for the calculation of valid data.
in a specific implementation, taking the second path of input data X1, the third path of input data X2, and the fourth path of input data X3 as an example, the operation result X may be calculated by the following formula:
wherein rki refers to the variable round key of the ith round.
in the embodiment of the invention, if the operation result is valid, the signal of the dual-track domino logic gate structural member PC is converted into a low-level signal so as to start an encryption process and encrypt the first path of input data.
In a specific implementation, when a plurality of data need to be encrypted in a pipeline, a previous round of circuit needs to be precharged, and at this time, a low level signal can be returned to a previous-stage double-rail domino logic gate result, so that an operation result corresponding to the previous-stage double-rail domino logic gate structure is guaranteed to be effective.
further, the step 405 may comprise the following sub-steps:
adopting a preset reversible transformation algorithm to perform synthesis and replacement operation on the operation result to generate an intermediate result;
and executing XOR operation by adopting the intermediate result and the first path of input data to generate a first path of encryption result.
In an example of the present invention, a reversible transformation algorithm is used to perform a synthesis and permutation operation on the operation result to obtain an intermediate result, and an xor operation is performed on the intermediate result and the first path of input data to generate a first path of encryption result.
The reversible transformation algorithm is a special linear transformation, and is a special linear transformation, where V is a linear space in a number domain P, σ is a linear transformation of V, and if there is a transformation τ of V, σ τ is τ σ τ I, where I is a unit transformation, σ is a reversible linear transformation, τ is an inverse transformation of σ, and the inverse transformation of the reversible linear transformation σ in V is still a linear transformation of V, and is uniquely denoted as σ, and is also called non-degenerate linear transformation (non-degenerate linear transformation)-1。
The synthesis substitution operation is an invertible transform, and is a composite of one nonlinear transform r and one linear transform L, i.e., t (a) ═ L (r (a)), where a is the result of the operation.
in an embodiment of the present invention, the step 406 may include the following sub-steps:
updating the first path of input data by adopting the second path of input data;
updating the second path of input data by adopting the third path of input data;
updating the third path of input data by adopting the fourth path of input data;
and updating the fourth path of input data by adopting the first path of encryption result.
Optionally, after the step 406, the method further comprises:
and selecting a round key different from the variable round key from a preset round key group as a new variable round key.
In the embodiment of the present invention, the length of the encryption key is 128 bits, and is expressed as MK ═ (MK0, MK1, MK2, MK3), where MKi is 32 bits, and the variable round keys are expressed as (rk0, rk1, … …, rk31), where rki is 32 bits. The method can be realized by a key expansion method: is provided with
To obtain
and 409, combining the four paths of output data to generate encrypted data.
In the embodiment of the invention, the data to be encrypted input by a user is received and divided into four paths of data, and the three paths of data except the first path of data and a preset variable round key are subjected to XOR operation to obtain an operation result; when the operation result is valid, converting the PC signal into a low level signal through a double-track domino logic gate structure, generating a first path of encryption result according to the XOR operation of the operation result and first path of input data, executing four paths of input data updating operation, repeating for 31 times, and then executing reverse order transformation on the four paths of data to obtain four paths of output data; and finally combining the four paths of output data to generate encrypted data. The method improves the speed of the encryption process, and simultaneously reduces the encryption power consumption and improves the encryption safety due to the addition of the domino logic gate structure.
Referring to fig. 5, fig. 5 is a data flow chart of a data encryption apparatus according to an embodiment of the present invention.
The data to be encrypted, Plaintext X, which is 128bit input, is divided into four paths of input data X0, X1, X2 and X3, and then enters Round1And then, carrying out XOR operation on the X1, the X2, the X3 and the rk1 to obtain an operation result, outputting a PC signal through a detect circuit (namely a two-way domino logic gate result), carrying out synthesis and replacement operation T, carrying out XOR operation on the operation result and the X0 to generate a first path of encrypted data, updating each path of input data, taking X0 as X4, shifting, and so on until the 32-round data encryption process is completed, carrying out reverse order change on the four paths of data, merging the four paths of data, and outputting 128-bit encrypted data Ciphertext Y.
Referring to fig. 6, fig. 6 is a block diagram illustrating a data encryption apparatus according to an embodiment of the present invention.
The invention also provides a data encryption device, which relates to a double-track domino logic gate structure, and the device comprises:
the input data dividing module 601 is configured to receive data to be encrypted input by a user, and averagely divide the data to be encrypted into four paths of input data; the four paths of input data comprise a first path of input data, a second path of input data, a third path of input data and a fourth path of input data;
an operation result generating module 602, configured to perform an exclusive or operation with the second path of input data, the third path of input data, the fourth path of input data, and a preset variable round key when the preset PC signal is a high level signal, so as to obtain an operation result;
a low level signal conversion module 603, configured to convert the PC signal into a low level signal through the dual-rail domino logic gate structure when the operation result is valid;
a first path encryption result generating module 604, configured to generate a first path encryption result according to the operation result and the first path input data;
a data update module 605, configured to perform four-way input data update operations;
a repeated execution module 606, configured to return the data to be encrypted input by the receiving user, and averagely divide the data to be encrypted into four paths of input data until the four paths of input data update operations are executed for 32 times;
a four-path output data generating module 607, configured to perform reverse order transformation on the first path of input data, the second path of input data, the third path of input data, and the fourth path of input data to obtain four paths of output data;
and an encrypted data generating module 608, configured to combine the four paths of output data to generate encrypted data.
Optionally, the apparatus further comprises:
and the round key reselection module is used for selecting a round key different from the variable round key from a preset round key group as a new variable round key.
Optionally, the first path encryption result generating module 604 includes:
the intermediate result generation submodule is used for executing synthesis and replacement operation on the operation result by adopting a preset reversible transformation algorithm to generate an intermediate result;
and the first path encryption result generation submodule is used for executing exclusive or operation by adopting the intermediate result and the first path input data to generate a first path encryption result.
Optionally, the data update module 605 includes:
the first path input data updating submodule is used for updating the first path input data by adopting the second path input data;
the second path of input data updating submodule is used for updating the second path of input data by adopting the third path of input data;
a third path input data updating submodule, configured to update the third path input data with the fourth path input data;
and the fourth path input data updating submodule is used for updating the fourth path input data by adopting the first path encryption result.
Optionally, the apparatus further comprises:
and the signal returning module is used for returning the low-level signal to the upper-stage double-rail domino logic gate structure so that an operation result corresponding to the upper-stage double-rail domino logic gate structure is effective.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working process of the apparatus described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method of data encryption involving a dual-rail domino logic gate structure, the method comprising:
receiving data to be encrypted input by a user, and averagely dividing the data to be encrypted into four paths of input data; the four paths of input data comprise a first path of input data, a second path of input data, a third path of input data and a fourth path of input data;
when the preset PC signal is a high-level signal, performing exclusive-or operation by adopting the second path of input data, the third path of input data, the fourth path of input data and a preset variable round key to obtain an operation result;
when the operation result is valid, converting the PC signal into a low-level signal through the double-track domino logic gate structure;
generating a first path of encryption result according to the operation result and the first path of input data;
executing four paths of input data updating operation;
returning to the step of receiving the data to be encrypted input by the user and averagely dividing the data to be encrypted into four paths of input data until the four paths of input data are updated for 32 times;
performing reverse order transformation on the first path of input data, the second path of input data, the third path of input data and the fourth path of input data to obtain four paths of output data;
and combining the four paths of output data to generate encrypted data.
2. A data encryption method according to claim 1, wherein after said step of performing a four-way input data update operation, said method further comprises:
and selecting a round key different from the variable round key from a preset round key group as a new variable round key.
3. The data encryption method according to claim 1, wherein the step of generating the first path encryption result according to the operation result and the first path input data comprises:
adopting a preset reversible transformation algorithm to perform synthesis and replacement operation on the operation result to generate an intermediate result;
and executing XOR operation by adopting the intermediate result and the first path of input data to generate a first path of encryption result.
4. The method of claim 1, wherein the step of performing a four-way input data update operation comprises:
updating the first path of input data by adopting the second path of input data;
updating the second path of input data by adopting the third path of input data;
updating the third path of input data by adopting the fourth path of input data;
and updating the fourth path of input data by adopting the first path of encryption result.
5. The method of claim 1, wherein after said step of converting said PC signal to a low signal via said dual-rail domino logic gate structure when said operation result is valid, said method further comprises:
and returning the low-level signal to the upper-stage double-rail domino logic gate structure, so that the operation result corresponding to the upper-stage double-rail domino logic gate structure is valid.
6. An apparatus for encrypting data, the apparatus being related to a dual-rail domino logic gate structure, the apparatus comprising:
the device comprises an input data dividing module, a data processing module and a data processing module, wherein the input data dividing module is used for receiving data to be encrypted input by a user and averagely dividing the data to be encrypted into four paths of input data; the four paths of input data comprise a first path of input data, a second path of input data, a third path of input data and a fourth path of input data;
the operation result generating module is used for executing exclusive or operation by adopting the second path of input data, the third path of input data, the fourth path of input data and a preset variable round key when a preset PC signal is a high-level signal to obtain an operation result;
the low level signal conversion module is used for converting the PC signal into a low level signal through the double-track domino logic gate structure when the operation result is valid;
the first path encryption result generation module is used for generating a first path encryption result according to the operation result and the first path input data;
the data updating module is used for executing four paths of input data updating operation;
the repeated execution module is used for returning the data to be encrypted input by the receiving user and averagely dividing the data to be encrypted into four paths of input data until the four paths of input data are updated for 32 times;
a four-path output data generating module, configured to perform reverse order transformation on the first path of input data, the second path of input data, the third path of input data, and the fourth path of input data to obtain four paths of output data;
and the encrypted data generation module is used for combining the four paths of output data to generate encrypted data.
7. A data encryption apparatus according to claim 6, said apparatus further comprising:
and the round key reselection module is used for selecting a round key different from the variable round key from a preset round key group as a new variable round key.
8. The data encryption device according to claim 6, wherein the first path encryption result generation module comprises:
the intermediate result generation submodule is used for executing synthesis and replacement operation on the operation result by adopting a preset reversible transformation algorithm to generate an intermediate result;
and the first path encryption result generation submodule is used for executing exclusive or operation by adopting the intermediate result and the first path input data to generate a first path encryption result.
9. The apparatus of claim 6, wherein the data update module comprises:
the first path input data updating submodule is used for updating the first path input data by adopting the second path input data;
the second path of input data updating submodule is used for updating the second path of input data by adopting the third path of input data;
a third path input data updating submodule, configured to update the third path input data with the fourth path input data;
and the fourth path input data updating submodule is used for updating the fourth path input data by adopting the first path encryption result.
10. A data encryption apparatus according to claim 6, said apparatus further comprising:
and the signal returning module is used for returning the low-level signal to the upper-stage double-rail domino logic gate structure so that an operation result corresponding to the upper-stage double-rail domino logic gate structure is effective.
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