CN112394905B - Design method of quantum divider - Google Patents

Abstract

The invention relates to a design method of a quantum divider, belonging to the field of quantum operation. The method comprises the following steps: s1: designing an n-bit quantum comparator by using a quantum gate to realize comparison operation of two n-bit binary numbers; s2: designing an equipotential and unequal quantum subtracter by using a quantum gate; s3: comprehensively designing the comparator and the subtracter in the steps S1 and S2 to obtain a quantum divider; s4: an experiment platform is built by adopting a classical computer and an open source quantum cloud simulator provided by an IBM laboratory, and simulation is carried out to realize quantum division operation. The invention realizes the quantum division operation by adding the auxiliary quantum bit and multiplexing, improves the performance of the quantum division operation and lays a foundation for processing more complex quantum calculation.

Description

Design method of quantum divider

Technical Field

The invention belongs to the field of quantum operation, and relates to a design method of a quantum divider.

Background

Based on the quantum mechanics principle, quantum computing effectively solves the mathematical problem that the classical computer can not overcome by using quantum. With the further research of quantum computing theory and quantum computers, quantum algorithms applied to various fields are also being researched and designed continuously. The quantum algorithm is the core of quantum computation, and the potential of the quantum algorithm is far superior to that of a classical algorithm. The quantum computer has own advantages and states compared with a classical computer, the storage unit of the quantum computer is a quantum bit, and the quantum bit theoretically contains countless information because the state of the quantum bit can be 0 or 1 and can also be a superposition state of 0 and 1, while the bit of the classical computer can only be 0 or 1, which is different from the quantum bit and the classical bit. At present, the research on quantum algorithms is many, and from the initial quantum algorithms to the present, the quantum algorithms are also continuously perfected and innovated, and more complex functions can be realized.

Division operation is one of the four fundamental operations, is often applied to various research fields, is widely applied to the fields of digital signal processing and digital communication, and how to realize quick and efficient division operation is related to the operation speed of the whole system. The design and research of the algorithm of the quantum divider are vacant, so that the search of the design and implementation method of the quantum divider is of great significance.

Disclosure of Invention

In view of the above, the present invention provides a method for designing a quantum divider.

In order to achieve the purpose, the invention provides the following technical scheme:

a method for designing a quantum divider comprises the following steps:

s1: designing an n-bit quantum comparator by using a quantum gate to realize comparison operation of two n-bit binary numbers;

s2: designing an equipotential and unequal quantum subtracter by using a quantum gate;

s3: comprehensively designing the comparator and the subtracter in the steps S1 and S2 to obtain a quantum divider;

s4: an experiment platform is built by adopting a classical computer and an open source quantum cloud simulator provided by an IBM laboratory, and simulation is carried out to realize quantum division operation.

Optionally, step S1 specifically includes:

given a composite system | a of two n-bit quantum states>|b>And realizing the QBstring | a by using a QBSC (Quantum bit string comparator)>＝|a _n-1 a _n-2 ...a ₀ I and | b>＝|b _n-1 b _n-2 ...b ₀ OfComparison operation, QBSC is a unitary evolution U as shown below _CMP ：

U _CMP |a〉|b〉|0〉|0〉＝|a〉|b〉|0>|c>

Wherein, l is the total quantum bit number contained in the composite system | a > | b >, and the implementation of the comparator needs 2 additional auxiliary quantum bits initialized to 0; i0 > does not carry any useful information, the last qubit state | c > carries the resulting information of the comparison, | a > and | b > are the two qubit strings being compared, respectively.

Optionally, the step S2 specifically includes:

the n quantum subtractors with one bit are superposed together to form allelic subtraction of n quantum bits, the subtraction is started from the lowest bit, the borrow is used as the borrow of the last subtraction of the next subtraction, thus, the borrow positions are alternately multiplexed, circulation is realized until the subtraction of the highest bit is completed, and finally, the subtraction result is obtained.

Optionally, step S3 specifically includes:

s31, comparing the divisor N and the dividend M by using the comparator, aligning the qubit representing the divisor N and the qubit representing the dividend M sequentially from high to low before the comparison, and taking the comparison result as a control bit a, where the value of the control bit a is: when the qubits represented by the divisor N are smaller than the qubits aligned with the divisor N among the qubits represented by the dividend M, the control bit is 0; otherwise, the value is 1; a is used as a control bit to control the highest bit of the quotient S, and when the control bit result is 1, the quotient S is assigned with 1; when the control bit result is 0, the quotient S is assigned 0;

s32, taking a in the S221 as a control bit, and controlling subtraction under the action of a subtracter; the result of the subtraction is b, the divisor is aligned with the second highest bit of b, and the highest bit c of b is used as the value of the control bit to the second highest bit of the quotient, and c is also the control bit of the subtraction;

s33, the result of the subtraction of S222 is d, d is taken as the beginning of a new cycle, and the qubits represented by the divisor N are aligned with the next highest order bits of d;

and S34, repeating S31, S32 and S33 until all the quantum bits representing the dividend M participate in the operation, wherein the result is reserved to an integer bit, if the result is further reserved to a decimal number, adding a new quantum bit with the state of |0> after representing the quantum bit of the dividend M as the lower bit of the dividend, repeating S31, S32 and S33 again, wherein the result is reserved to the decimal number, the accuracy degree of the decimal number is related to the number of the added |0> bits, and the more the |0> bits are added, the more the result is accurate.

Optionally, step S4 specifically includes:

and (3) simulating and realizing quantum division operation simulation by using Python language by utilizing packet management and environment management functions provided by an open source quantum computing toolkit QISKIT and Anaconda.

The invention has the beneficial effects that:

1. the invention successfully fills the blank of the quantum divider in the algorithm design and designs the efficient quantum divider.

2. The invention realizes division operation on the quantum simulator for the first time and can reserve to decimal place, and uses the zero setting gate and the auxiliary bit of constant quantum bit, thus greatly reducing the running time and complexity.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

For a better understanding of the objects, aspects and advantages of the present invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a technical roadmap for the process of the invention;

FIG. 2 is a typical quantum gate; (a) controlled-non-Toffoli Gate, (b) controlled non-CNOT Gate;

FIG. 3 is a circuit diagram of a specific structure of a two-bit quantum comparator;

FIG. 4 is a circuit diagram of a specific structure of a one-bit quantum subtracter;

FIG. 5 is a circuit diagram of a specific construction of an equipotential subtractor for two qubits;

FIG. 6 is a circuit diagram of a specific structure of an unequal bit subtractor for subtracting two bits from three bits;

FIG. 7 (a) is a diagram of the operation steps of a six-bit by two-bit quantum division method, and FIG. 7 (b) is a circuit diagram of a specific structure of a six-bit by two-bit quantum divider;

FIG. 8 is a histogram of the measured probability of "101011" divided by "11";

fig. 9 (a) is a diagram of the result of dividing the quantum divider operation "101011" by "11" with no remainder, and fig. 9 (b) is a diagram of the result of dividing the quantum divider operation "101011" by "11" with remainder.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.

Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.

Fig. 1 to 9 show a design method of a quantum divider.

Specifically, in this embodiment, taking binary number "101011" divided by binary number "11" as an example, S1 specifically is:

in this embodiment, an n-bit quantum comparator is designed by using a controlled-non-Toffoli gate as shown in fig. 2 (a), a controlled non-CNOT gate as shown in fig. 2 (b), and a zero-setting gate, so as to implement comparison operation of two n-bit binary numbers.

The quantum comparator is realized according to the following principle:

given a composite system | a of two n-bit quantum states>|b>And a qubit string comparator (QBSC) is adopted to realize the qubit string | a>＝|a _n-1 a _n-2 ...a ₀ I and | b>＝|b _n-1 b _n-2 ...b ₀ The comparison operation of |, QBSC is a unitary evolution U as shown below _CMP ：

U _CMP |a>|b>|0>|0>＝|a>|b>|0>|c>

Wherein l is a composite system | a>|b>The total number of qubits involved, and 2 additional auxiliary qubits initialized to 0 are required for the implementation of the comparator; |0>Does not carry any useful information, the final qubit state | c>Carrying the result information of comparison, | a>And | b>Two qubit strings for comparison, respectively. In the embodiment, a is a in a 2-bit quantum comparator ₀ 、b ₀ And c ₀ The operation relationship is as follows:

a ₀ 、b ₀ 、c ₀ and c ₁ The operation relationship is as follows:

fig. 3 shows a specific configuration circuit diagram of the two-bit quantum comparator.

And S2, designing an equipotential and unequal quantum subtracter by utilizing a control-non-Toffoli gate, a controllable non-CNOT gate and a zero setting gate, and realizing subtraction operation of two binary numbers.

The design of the subtracter firstly starts from the number with only one qubit, because the subtracter relates to borrowing, including previous borrowing and the current borrowing, and therefore two auxiliary bits are needed to store the carry information. Fig. 4 shows a specific construction circuit diagram of a one-bit quantum subtracter.

And designing an equipotential subtracter. Based on the design of a one-bit quantum subtracter, an equipotential subtracter is designed. The allelic subtraction of the numbers containing n-bit quantum bits is formed by overlapping n-bit quantum subtracters, the subtraction is started from the lowest bit, the borrow of the lowest bit is used as the borrow of the last time of the next subtraction, and thus, the borrow positions are alternately multiplexed, circulation is realized until the subtraction of the highest bit is completed, and finally, the subtraction result is obtained. Specifically, in this embodiment, we design a subtractor with an allelic subtraction of two qubits, and fig. 5 shows a specific configuration circuit diagram of the allelic subtractor with two qubits, which implements the allelic subtraction process of md [0-1] -rc [0-1], md [0-1] is the subtree, and rc [0-1] is the subtree. The subtraction is started from the lower order, md [0-1] is the subtracted number, rc [0-1] is the subtracted number, and the final result is stored at md [0-1]. Since the allelic subtraction only needs two auxiliary qubits ass [0-1] and the final borrow information, it is determined that the result is exactly negative, the information is stored in one qubit of ass [0-1] and is related to the number of bits of the two binary numbers used for the subtraction, if the number of bits of the two binary numbers is odd, the final borrow information is stored in ass [1], if the number of bits is even, ass [0] is stored.

And designing an unequal bit subtracter. The method can be modified on the basis of the allelic subtraction, firstly, the allelic parts are aligned from the lower bits, allelic subtraction is carried out, the result of the allelic subtraction and the borrow of the current time are obtained, then the highest bit of the subtracted number and borrow information are subtracted, the result of the non-allelic subtraction can be obtained, and the unequal phase subtraction operation is completed. Specifically, in this embodiment, we design an unequal subtractor of three bits minus two bits, and fig. 6 shows a specific configuration circuit diagram of the unequal subtractor of three bits minus two bits, which is implemented by the unequal subtraction process of md [0-2] -rc [0-1], and the first step is: allelic subtraction is performed on md [1-2] and rc [0-1], and the first two red boxes in the figure perform this function. The second step is that: subtracting borrow information ass [0] obtained by subtracting the highest bit of md [0] from the allele in the first step.

And S3, comprehensively designing the comparator and the subtracter in the steps S1 and S2 to obtain the quantum divider.

The quantum divider is implemented according to the following principle:

specifically, in the embodiment, taking the example of a binary number "101011" divided by a binary number "11", we align the divisor with the highest order bit of the dividend, e.g., the divisor "11" is aligned with the highest order bit "10" of the dividend "101011" in the example. In the second step, the comparator designed above is used to compare 10 with 11, and the comparison result is the control bit a, the value of the control bit a is: when 10-straw 11, the control bit is 0; otherwise, the number is 1. Step three, a is used as a control bit to control the highest bit of the quotient S, and when the control bit result is 1, the quotient is assigned with 1; when the control bit result is 0, a quotient of 0 is assigned. And step four, taking a as a control bit, and controlling subtraction operation under the action of the subtracter. And fifthly, the result of the subtraction is b, the divisor and the next highest bit of b are added, the highest bit c of b is used as the control bit, and the value of the next highest bit of the quotient is assigned, and c is also used as the control bit of the subtraction. Sixthly, taking the result of the fifth subtraction as d, taking d as the beginning of a new cycle, aligning the divisor 11 with the next higher order of d, repeating the above steps until all the qubits represented by "101011" participate in the operation, then keeping the result to an integer number, if further keeping to a decimal, adding a new qubit in state |0> after the qubit represented by "101011" as the lower order of the dividend, and repeating the above six steps again, thus keeping the result to a decimal number, wherein the accuracy of the decimal number is related to the number of the added |0> bits, and the more the added |0> bits are, the more the result is accurate. Fig. 7 (a) is a circuit diagram illustrating the operation steps of the six-bit-by-two-bit quantum division, and fig. 7 (b) is a circuit diagram illustrating a specific structure of the six-bit-by-two-bit quantum divider.

And S4, adopting an open source quantum cloud simulator provided by a classical computer and an IBM laboratory to build an experimental platform and carrying out simulation to realize quantum division operation.

The simulation implementation adopts a classical computer and a programmable quantum computer provided by an IBM platform, a quantum line is compiled by using a python language according to the environmental management provided by an open source quantum computer toolkit Qiskit and Anaconda provided by an IBM laboratory, the operation is implemented according to the compiled line, the quantum measurement is carried out, and finally, a corresponding simulation result is output. When the Qiskit quantum simulation system runs the quantum lines, the output quantum sequences are in one-to-one correspondence with the quantum lines from left to right from bottom to top according to the information expressed by the quantum bits in the quantum lines from bottom to top. Fig. 8 shows the probability histogram of "101011" divided by "11" after measurement. Specifically, in the embodiment, the binary number "101011" is divided by the binary number "11", i.e., 43 divided by 3 in decimal. FIG. 9 (a) is the result of the quantum divider operating "101011" divided by "11" remainder, the result of the first row being the time of operation; the result of the second row is the final output value of all qubits at the end of the run; the third row result is the calculation result displayed by the division operation, the result is turned over, the quantum divider operation result is obtained to be 111001, the quantum bit result of 1110 being the integer number is decimal 10, the quantum bit result of 01 being the floating point number is 0.25. This is because the 2-bit qubit of the floating-point number is added here, so that the result output has a small number of bits, the more qubits are added to represent the floating-point number, the more accurate the result. Fig. 9 (b) shows the result of dividing "101011" by "11" with remainder, remainder is quotient remainder, and there is no qubit corresponding to the floating point number added, so that the operation time is greatly reduced, because the operation time increases exponentially for each qubit increase. From the above experimental process, it can be known that the feasibility and the universality of the quantum division method are realized in the design method, and the quantum division operation is realized.

Finally, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (1)

1. A design method of a quantum divider is characterized by comprising the following steps: the method comprises the following steps:

s1: designing an n-bit quantum comparator by using a quantum gate to realize comparison operation of two n-bit binary numbers;

s2: designing an equipotential and unequal quantum subtracter by using a quantum gate;

s3: comprehensively designing the comparator and the subtracter in the steps S1 and S2 to obtain a quantum divider;

s4: adopting a classical computer and an open source quantum cloud simulator provided by an IBM laboratory to build an experimental platform and carrying out simulation to realize quantum division operation;

the step S1 specifically includes:

given a composite system | a of two n-bit quantum states>|b>And realizing the QBSA by using QBSC>＝|a _n-1 a _n-2 ...a ₀ I and I b>＝|b _n-1 b _n-2 ...b ₀ The comparison operation of |, QBSC is a unitary evolution U as shown below _CMP ：

U _CMP |a>|b>|0>|0>＝|a>|b>|0>|c>

Wherein, the realization of the comparator needs another 2 auxiliary quantum bits initialized to 0; the |0> does not carry any useful information, the last qubit state | c > carries the result information of the comparison, | a > and | b > are two qubit strings for comparison, respectively;

the step S2 specifically includes:

n quantum subtracters with one bit are overlapped to form allelic subtraction of n quantum bits, subtraction is started from the lowest bit, and borrow of the n quantum bits is used as borrow of the last subtraction of the next subtraction, so that borrow positions are alternately multiplexed, circulation is realized until subtraction of the highest bit is completed, and finally, a subtraction result is obtained;

the step S3 specifically comprises the following steps:

s31, comparing the divisor N and the dividend M by using a comparator, aligning the qubit representing the divisor N and the qubit representing the dividend M from high to low in sequence before comparison, and taking a comparison result as a control bit a, wherein the value of the control bit a is as follows: when the qubits represented by the divisor N are smaller than the qubits aligned with the divisor N among the qubits represented by the dividend M, the control bit is 0; otherwise, the value is 1; a is used as a control bit to control the highest bit of the quotient S, and when the control bit result is 1, the quotient S is assigned with 1; when the control bit result is 0, the quotient S is assigned 0;

s32, taking a in the S31 as a control bit, and controlling subtraction under the action of a subtracter; the result of the subtraction is b, the divisor is aligned with the second highest bit of b, and the highest bit c of b is used as the value of the control bit to the second highest bit of the quotient, and c is also the control bit of the subtraction;

s33, the result of the subtraction of S32 is d, d is taken as the beginning of a new cycle, and the quantum bit represented by the divisor N is aligned with the next highest bit of d;

s34, repeating S31, S32 and S33 until all the quantum bits representing the dividend M participate in the operation, wherein the result is reserved to an integer bit, if the result is further reserved to a decimal number, adding a new quantum bit with the state of |0> after representing the quantum bit of the dividend M as the lower bit of the dividend, repeating S31, S32 and S33 again, wherein the result is reserved to the decimal number, the accuracy degree of the decimal number is related to the number of the added |0> bits, and the more the |0> bits are added, the more the result is accurate;

the step S4 specifically comprises the following steps:

and (3) simulating and realizing quantum division operation simulation by using Python language by utilizing packet management and environment management functions provided by an open source quantum computing toolkit QISKIT and Anaconda.

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