JPS6236800A - Ic memory device - Google Patents

Abstract

PURPOSE:To incorporate an IC memory to an IC card to prevent the misuse of this card and to improve the versatility and the flexibility of the IC card, by providing selectively a write/erasion unable area into an EEPROM. CONSTITUTION:When the data on a memory cell 5 are erased, and OV potential connected to the source of a MOS-FET 21 is applied to a gate G of the cell 5 via a fuse 22. While a high potential VPP connected to the drain of a MOS- FET 20 is applied to the gate G of the cell 5 via the fuse 22 when the data are written to the cell 5. Therefore the write/eration operation is impossible if the fuse 22 is cut off since the signals are always transmitted via the fuse 22 in a write/erasion operation mode. In a reading mode the output of a Y decoder 3 is applied directly to the gate G of the cell 5. Thus the reading operation is carried out regardless of the presence or absence of the fuse 22. In such a way, the fuse 22 is cut off only with a specific address and only a specific area is set under a write/erasion unable state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an IC memory device, and in particular to an electrically programmable/erasable read-only memory device (E 1 electric
Erasable Programmable
e ReadOnly Memory, hereinafter referred to as EE
(referred to as PROM).

[Background of the invention]

Conventionally, a card-type read-only memory using an IC has a structure that makes it impossible to write to all memory cells at the same time, as in the technology described in Japanese Patent Laid-Open No. 58-133699, for example. In other words, with magnetically recorded cards, the recorded data could be erased or rewritten, so in the above-mentioned prior art, the data embedded in the card was used to prevent the data written on the card from being rewritten. After writing data into the IC memory, the fuse of the write gate line is cut to prevent the written data from being rewritten.

However, with this method of making it impossible to write to the entire card at the same time, advances in semiconductor technology have made it difficult to use large-capacity ICs inside the card.
If it becomes possible to embed memory, a method would be to greatly expand the range of applications of IC memory by arbitrarily making only specific addresses a non-writable area and making other areas writable. Therefore, flexibility is suppressed.

[Purpose of the invention]

An object of the present invention is to improve such conventional problems, to provide an IC that can selectively write/erase data, and is versatile, flexible, and capable of expanding the field of application of cards.
An object of the present invention is to provide a memory device.

[Summary of the invention]

In order to achieve the above object, the IC memory device of the present invention includes:
In a read-only memory device having a memory cell matrix that can be electrically written and erased, each block of the memory cell matrix is provided with a permanently destructive element such as a fuse and a means for destroying the destructive element, and a specific address is provided. The feature is that only when input is input, the destruction means is operated to make writing and erasing impossible.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an EEFROM according to an embodiment of the present invention.
FIG. 3 is a block diagram of a blotting gate type MO8.
FET (Metal Oxided Sem1
c.

nducjer-Field Effect Tr
This shows the case where a memory cell (Ansistor) is used as a memory cell. In FIG. 1, 1 is a memory cell unit arranged in a matrix. If the columns of the matrix are X and the rows are Y, then 2 is the X-side decoder and 3 is the Y-side decoder. 4 is a bidirectional data buffer for exchanging data with the outside. The C8 signal is a control input signal that activates decoders 2, 3 and data buffer 4. The OE multiplication signal is a control input signal for causing the data buffer 4 to perform an output operation. Reference numeral 5 designates a memory cell of a bloating gate type MO3-FET, which has its source connected to the X decoder output line, its gate connected to the Y decoder output line, and its drain connected to the voltage line via a resistor 6. 6 is a pull-up resistor, 7 is a sense amplifier connected to msa, 8, 12, 14, 15° 16 is AN
D gate, 9 to 11 are inverters, 13 is OR gate,
117 to 21 and 23 are MOS-FETs, and 22 is a fuse element made of a material such as polysilicon. In the floating gate MO3-FET memory cell 5, the data nl is when the floating gate stores charge.
n, fl When there is no load, it operates as data "On."
The circuit 28 in the R gland is a write/erase control circuit, and there are as many bits as there are in the data buffer 4, but in this case, there are only 1 circuits.
Only the bits are shown in detail, and the rest are omitted. The circuit 29 inside the chain line is a control circuit for performing a read operation, and only one circuit is provided in the EEFROM, and its output is common to the Y decoder output and the floating gate type MO3-FET of the memory cell unit. The gate of the MOS-FET 19 is connected to the gate input of the MOS-FET 19. Further, circuits 30 enclosed in chain lines are write/erase and fuse cutting control circuits, and there are as many circuits as there are output lines of the Y decoder. In this circuit 30, MOS-
FET20, 23, fuse 22, AND gate 14,
16, OR gate 13 is a circuit that operates to cut the fuse.

In this way, in the EEPROM, a block of memory cells is selected by the input address signal, and writing/erasing is performed by the writing/erasing control circuit 28.

In addition, a write/erase and fuse cutting control circuit 30 is provided for each block of memory cells, and by cutting a permanently destructive element such as a fuse, writing/erasing of the corresponding memory block becomes impossible and the circuit is read-only. Make it.

First, when erasing data, a high voltage Vpp, which is used only during writing/erasing, is applied to the drain D of the memory cell 5 via the MOS-FET 18 of the writing/erasing control circuit 28, and at the same time, the gate of the memory cell 5 is applied to the drain D of the memory cell 5. For G,
MO in write/erase and fuse cut control circuit 30
Data is erased by applying a ground potential (Ov) through the S-FET 2 and the fuse 22 to discharge the charges on the bloating gate.

That is, an ERASE signal for performing an erase operation is applied to the drain D of the memory cell 5, so that the MOS-FETI 8 in the control circuit 28 becomes conductive, and by subsequently applying the high voltage VPP, the above-mentioned MO8-FE
The 0th order where a high voltage is applied to the drain D through T18,
The gate of memory cell 5 is connected to ERA by AND gate 15.
The SE signal and the output of the selected Y decoder 3 are ANDed, and the gate 15 is opened to open the MOS-FET 2.
1 is conductive, the Ov potential is applied via the fuse 22. As a result, the negatively charged floating gate is discharged to the Ov of the gate G and the high voltage VPP of the drain D, and the charge disappears, so that the data of the memory cell 5 selected by the X decoder 2 and the Y decoder 3 is will be deleted.

Next, when writing data, an Ov potential is applied to the drain D of the memory cell 5, and a high voltage VPP is applied to the gate G. Drain D has buffer 4
Only when the input data to the MOS-FE is II 1 s, the WRITE signal and the data output from the sense amplifier 7 are input to the AND gate 8, the output becomes 1'', and the MOS-FE
An Ov potential is applied with two ζ making T 17 conductive. On the other hand, the output of the Y decoder 3 selected as one by opening the AND gate 14 by the WRITE signal inputted through the OR gate 13 is input to the gate G.
-FET 20 is made conductive, and the input high voltage Vpp is applied via the MOS-FET 20 and fuse 22. By applying an ov potential to the drain D and a high voltage VPP to the gate G, high-energy electrons and holes are generated near the interface, and the barrier is smaller for electrons than for holes, so Electrons jump over the oxide barrier and are injected into the floating gate. As a result, the floating gate becomes negatively charged and the data II 11. has been written. When the write data input to the buffer 4 is it O, , the AND gate 8 does not open and the MOS-FET 17 does not become conductive, so 0VtI1 is not applied to the drain D of the memory cell 5. Therefore, the blowout occurs. Since no electrons are injected into the timing gate and no charge is accumulated, data "'0" is written.

Next, the operation when reading data will be explained. At the time of reading, the read control circuit 29 outputs the WRITE signal, E
Since both the RASE signal and the PROG signal are '0', '1' is input to the AND gate 12 via the inverters 9 and 10°11, so the AND gate 12
opens, and depending on the signal! Make JMO3-FETI 9 conductive. As a result, the output of the Y decoder 3 is applied to the gate G of the memory cell 5. If a charge is accumulated in the bloating gate of the memory cell 5, the potential input to the gate G and the negative potential of this charge cancel each other out.
Since memory cell 5 is not conductive, drain D is biased to potential Vcc by pull-up resistor 6, and that potential is output via sense amplifier 7 and buffer 4. In this case, the read data is 91''.

Next, when there is no charge accumulation in the floating gate, when the output from the Y decoder 3 is applied to the gate of the memory cell 5, the source S connected to the low potential and the high potential Vcc are connected. The low potential of the X decoder 2, which is electrically connected to the drain D and connected to the source S, is output from the sense amplifier 7 through the buffer 4 via the drain D. The read data in this case is '0#.

In this way, when erasing data in the memory cell 5, the Ov potential connected to the source of the MOS-FET 21 is applied to the gate G of the cell 5 via the fuse 22, and when writing data into the memory cell 5, , MOS-FE
A high potential VPP connected to the drain of T20 is applied to the gate G of the cell 5 via the fuse 22. Therefore, during a write/erase operation, a signal is always transmitted via the fuse 22, so if this fuse is cut, the write/erase operation becomes impossible. On the other hand, in a read operation, since the output of the Y decoder 3 is directly applied to the gate G of the cell 5, the read operation is performed regardless of the presence or absence of the fuse 22.

In this embodiment, the fuse 22 is cut only for a specific address, thereby making writing/erasing impossible only in the specific area.

When cutting the fuse 22, AND gates 14 and 16 perform a logical product of the output of the Y decoder 3 and the input of the control signal PROG for cutting the fuse.
Conducting FETs 20 and 23 to force fuse 22
Apply current to and disconnect. That is, MOS-FET2
0 is made conductive and a high potential VPP is applied to one end of the fuse 22, and at the same time, by making the MOS-FET 23 conductive and applying an Ov potential to the other end of the fuse 22, Vpp→
A current is forced to flow through the path of FET 20 → fuse 22 → FET 23 → Ov, and fuse 22 is cut off.

In this embodiment, since the fuse 22 is installed on the output side of the Y decoder 3, the memory cell 5 connected to the output of the Y decoder 3 is the unit of the block that makes write/erase operations impossible. becomes. In other words, a group of memory cells connected to the same Y decoder output line are divided into areas as a write/erase block unit.

In addition, although the fuse 22 is used in this embodiment, it can also be realized by using an avalanche destruction type MOS-FET, and if it is an element that can be destroyed permanently, the same function can be achieved. can be easily realized.

Furthermore, it is also possible to mount the IC memory having the configuration shown in FIG. 1 on the same chip together with other elements such as a microcomputer so that the IC memory functions as a multi-function element such as a one-chip microcomputer.

FIG. 2 is a block diagram of an IC card to which the IC memory of the present invention is applied.

The present invention is effective when applied to an IC card as shown in FIG.

24 is a resin that is the base material of the IC card, 25 is an input/output terminal, 26 is a microcomputer, and 27 is an E according to the present invention.
It is an EPROM. The input/output terminal 25 includes an I10 terminal,
Reset terminal (R8T), clock terminal (CLK), !
These external input signals have a source terminal (Vcc), a ground terminal (GND), and a high voltage terminal (Vpp).
These are divided into those that are once input to the microcomputer 26 and those related to power that are also supplied to the EEFROM 27 in parallel. Microcomputer 26 to EEPRO
For M27, an address to be accessed, data for IF loading/reading, a control input signal C8 for activating decoders 2 and 3 and data buffer 4, and a control input signal for outputting data buffer 4. There are a write signal WRITE for writing, an erase signal ERASE for erasing, and a program signal PROG for disabling write/erase operations. EEPR○M27
In the memory matrix, a specific address corresponding to the Y decoder output can be set by cutting a fuse in any one of the write/erase control and fuse cutting circuits 30 provided corresponding to the Y decoder output. Writing/erasing is not possible only when input.
It is read-only, and when another address is input, not only reading but also writing and erasing are possible.

There are many uses for IC cards, but for example, in applications such as cash cards, among the contents stored in the EEPROM, such as a personal identification number and a control program for a microcomputer.

Content can be broadly divided into content that must never be rewritten, and content that can be modified later or cannot be misused even if it is rewritten. Conventional E
EPROM has the possibility of all data being rewritten due to its structure.

In order to place non-rewritable data in the memory matrix, a different element is used only at that location.

For example, PROM (Programmable Rea
dOnlyMe+*ory) must be used in parallel. on the other hand.

IC cards are very weak in terms of strength, and the reliability is improved if the number of built-in IC chips is as small as possible, so it was difficult to incorporate multiple chips in addition to the microcomputer. In the example, as shown in FIG.
It is sufficient to incorporate a chip EEPROM 27, and the write/erasable area can be arbitrarily set, so it is highly flexible and can expand the range of applications of the IC card.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to selectively provide a non-writable/non-erasable area in the EEPROM, so if it is built into an IC card, it is extremely effective in preventing misuse.

[Brief explanation of the drawing]

FIG. 1 is an internal block diagram of an IC memory device showing one embodiment of the present invention, and FIG. 2 is an internal block diagram of an IC memory device incorporating the IC memory of the present invention.
It is a structural diagram of a C card. 1: Memory cell unit, 2: X decoder, 3: Y decoder, 4: Data buffer, 5: Floating gate type MO3-FET, 7: Sense amplifier, 17 to 21,
23: MOS-FET, 22: Fuse, 28: Write/erase control circuit, 29: Read control circuit, 30: Write/erase and fuse cutting circuit. Patent applicant: Hitachi, Ltd., -

Claims (1)

[Claims] (1) Memory cells that can be electrically programmed and erased
In a read-only memory device having a matrix, each block of the memory cell matrix is provided with a permanently destructive element such as a fuse and means for destroying the destructive element, and the destructive means is operated only when a specific address is input. An IC memory device characterized in that writing and erasing are impossible.