JPS6236157Y2 - - Google Patents

Description

[Detailed description of the invention] This invention is a circuit that obtains a time signal by counting the commercial power supply frequency of 50/60Hz, and automatically generates a constant time signal without the need for a switch or the like for either 50/60Hz input. It was designed to be obtained.

Conventionally, a 50/60Hz mode changeover switch or the like is often used to switch between a quinary and hexadecimal counter. However, changing the switch for each power frequency is troublesome and operation errors are likely to occur. Also, in order to do this electrically, 50/60Hz
A method has been considered in which the mode is detected by using the difference in pulse width and by the difference in the integral level, but there are the following problems. At 50/60Hz, the pulse width is even if the duty cycle is 50%.
They are 10msec (50Hz) and 8.3msec (60Hz), and the difference in integral level is minute and difficult to detect. Furthermore, if the duty cycle of the pulse signal fluctuates, the operation becomes unstable.

The present invention improves this point, and the pulse _{width t} is
Trigger the monostable multivibrator (T ₅₀ > t > T ₆₀ ), detect 50/60Hz at the integral level of its output, and if the input pulse signal is 50Hz, use the "5" output of the hexadecimal counter to detect this. This resets the hexadecimal counter and switches it to a quinary counter.

FIG. 1 is a pulse diagram showing the configuration of the present invention. A is a 50Hz pulse signal, B is a 60Hz pulse signal. C is the output of a monostable multivibrator triggered by a 50Hz pulse signal A, and D is the output of a monostable multivibrator triggered by a 60Hz pulse signal B. Now, if the output pulse width t of the monostable multivibrator is (T ₅₀ + T ₆₀ )/2, then
In D, the pulse interval is t=18.3msec.
For this, T ₅₀ −(T ₅₀ +T ₆₀ )/2=1.7 msec, 2T ₆₀ −(T ₅₀ +T ₆₀ )/2=15 msec. It is easy to integrate this to obtain logic "1" and "0" levels. E and F are examples of the integrated output waveforms of C and D, respectively, and by setting the threshold value to Vt, a 50/60Hz switching signal can be stably obtained. G and H are hexadecimal counter outputs when a 50/60Hz pulse signal is input, and both are
It becomes a time signal with a period of 0.1 seconds.

FIG. 2 is a wiring diagram of a circuit according to an embodiment of the present invention.
50/60Hz AC signal input added to 1 is waveform shaping circuit 2
The pulse signal is shaped into a 50/60 Hz pulse signal of a desired level, and is applied to the counter 4 and inputted to the monostable multivibrator 5 as a trigger signal. Output 6 of monostable multivibrator 5 is a resistor
The pulse signal of output 3 of circuit 2 is added to the integrating circuit composed of R ₁ , R ₂ , R ₃ and capacitor C ₁ .
When the frequency is 50Hz, the transistor _Q1 is turned on, and when the frequency is 60Hz, it is turned off. Transistor Q ₁
The collector output 14 of is set to logic “0” and “1” respectively.
Set to level. “2 ⁰ ” output of counter 4 (A
Add output) 7 and "2 ² " output (C output) 9 to NAND gate 10, and when the counter output is "5"
A logic "0" level output is obtained at the output 11 of the NAND gate 10. Furthermore, this output and transistor
The collector output 14 of Q ₁ is applied to an OR gate 15 such that its output 16 is at a logic "0" level only when the output 11 of the circuit 10 and the output 14 of the transistor Q ₁ are both at a logic "0" level. . At this time, the output 18 of the NAND gate 17 becomes a logic "1" level, which is applied to the "0" reset input terminal of the counter 4, thereby resetting the counter 4 to "0". This causes the counter 4 to operate as a quinary counter. Also, pulse signal 3 is 60Hz
In this case, the collector output 14 of the transistor Q ₁ becomes logic “1” level, and the output 1 of the OR gate 15
6 is also at the logic "1" level. Therefore, the output 18 of the NAND gate 17 is the output 1 of the NAND gate 12.
3 becomes a logic "1" level only when it is a logic "0" level, and the counter 4 is reset. NAND
The “2 ¹ ” output of the counter 4 (B
Output) 8 and "2 ² " output 9 are added, and when the counter output is "6", the output 13 of the NAND gate 12 is set to logic "0" level, and the counter 4 is reset to "0", making it a hexadecimal counter. make it work. At the "2 ² " output 9 of the counter 4, a time signal output with a period of 0.1 second is obtained for either 50/60 Hz input.

[Brief explanation of the drawing]

FIG. 1 is a pulse diagram for explaining the operation of the present invention, and FIG. 2 is a wiring diagram of an embodiment of the present invention. 4... Counter, 5... Monostable multivibrator, R ₁ , R ₂ , R ₃ and C ₁ ... Resistance and capacitor forming an integrating circuit, 10, 12, 15 and 17... Gate circuit.

Claims (1)

[Scope of utility model registration request] A hexadecimal counter that counts 50Hz and 60Hz pulse signal inputs, a monostable multivibrator that is triggered by the pulse signal inputs, an integrator circuit that integrates the output of this monostable multivibrator, and that responds to the output level of this integrator circuit. and a gate circuit that generates a reset input for operating the hexadecimal counter as a quinary counter, and the pulse width t of the monostable multivibrator is set to 50Hz and 60Hz
For the periods T ₅₀ and T ₆₀ of the pulse signal, T ₅₀ >t>
A time signal generation circuit characterized in that the circuit is set to a relationship of _T60 .