JPH04101143U - Watchdog timer circuit - Google Patents

Abstract

(57) [Summary] [Configuration] An operational amplifier, a bias resistor circuit that applies bias to the input end of the operational amplifier and also serves as a part of the integrator circuit, and an integrator connected between the output end of the operational amplifier and a part of the input. Resistors, diodes and capacitors that make up the circuit,
and a diode that clamps the output of the operational amplifier.
A watchdog signal, which is a no-voltage contact signal, is input to both ends of the capacitor, and a watchdog alarm signal is output from the output end of the operational amplifier when the watchdog signal is interrupted. [Effect] Since it is an analog timer that operates stably as a long-term timer and operates at a low frequency, it generates little EMI noise.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention is a fail-safe system for supervisory control systems applied to computers, etc. Analog watchdog timers that are particularly effective in preventing EMI noise. Watchdog timer using a timer Watchdog timer with alarm detection function Regarding the current circuit.

0002

[Conventional technology]

Conventionally, this type of wow dog timer circuit uses a crystal generator that generates a high frequency signal. It consists of a digital timer that combines an oscillator, a frequency dividing circuit, and a preset counter. It was common to In addition, the preset counter value can be made programmable. It was also relatively easy to do.

0003

[Problem that the idea aims to solve]

The watchdog timer circuit using the conventional digital timer described above has a high frequency Since it uses a crystal oscillator that generates wave signals, it has high performance in terms of time measurement. Ru. However, watchdog timers generally range from a few seconds to hundreds of seconds. Since the clock is used with a relatively long monitoring time, it is less accurate than the absolute time. However, it is important that it operates stably as a long-term timer. Also, digital Because IMA uses a high-frequency oscillation circuit to process digital signals, it is difficult to generate EMI noise signals. It had the disadvantage that it could easily become a source of controversy.

0004

[Means to solve the problem]

The watchdog timer circuit of this invention has positive and negative signal input terminals and signal output terminals. A bias is applied to the positive and negative input terminals, and one of the integrating circuits a bias resistor circuit that also serves as a circuit, and one end connected to the output end of the operational amplifier. a resistor; a first diode having an anode connected to the other end of the resistor; A capacitor connected between the cathode of the diode and the negative input terminal of the operational amplifier. a second electrode whose anode is connected to the other end of the resistor and whose cathode is grounded; A watchdog with a no-voltage contact signal across the capacitor, including a diode and Input the signal and output the watchdog alarm signal to the output terminal of the operational amplifier. Ru.

[0005] Further, the integration circuit includes the operational amplifier, the bias resistance circuit, and the resistance circuit. The time constant of the integrating circuit includes the first diode and the capacitor, and the time constant of the integrating circuit is equal to the time constant of the integrating circuit. When the watchdog signal is interrupted even once, the watchdog alarm signal is output. There are things that are meant to be strengthened.

[0006]

【Example】

Next, the present invention will be explained with reference to the drawings.

[0007] FIG. 1 is a circuit diagram of an embodiment of the present invention. Analog timer circuit 1 is a switch No-voltage contact momentary signal IN1 terminal which is a watchdog timer signal from CH2 input the watchdog alarm signal from the OUT1 terminal to the relay drive circuit 3. Output to IN2 terminal of. The relay drive circuit 3 receives the watchdog alarm signal. When input, the relay 4 connected to the OUT2 terminal is driven.

[0008] Analog timer circuit 1 has one end connected to operational amplifier A1 and negative power supply E1. A resistor R1, a resistor R2 connected between the other end of the resistor R1 and ground, and one end connected to a negative power supply E. 1 has a resistor R3 whose other end is connected to the negative input terminal of the operational amplifier A1, and one end which is connected to a resistor R1. The other end is connected to a resistor R4 whose other end is connected to the positive input terminal of the operational amplifier A1, and one end is connected to the operational amplifier A1. Resistor R5 is connected to the output end of amplifier A1, and the anode is connected to the other end of resistor R5. diode D1, the cathode of diode D1 and the negative input of operational amplifier A1 The capacitor C1 is connected between the two ends, and the anode is connected to the other end of the resistor R5. Diode D2 whose cathode is grounded and whose anode is the output of operational amplifier A1 It has a diode D3 at its end whose cathode is connected to the OUT1 terminal. Further, both ends of the capacitor C1 are set as IN1 terminals.

[0009] The relay drive circuit 3 is connected to an NPN transistor Tr1 whose emitter is grounded. A resistor R6 has one end connected to the IN2 terminal and the other end connected to the base of the NPN transistor Tr1. and a resistor R7 whose one end is connected to the positive power supply E2, and whose cathode is connected to the other end of the resistor R7. and a diode D4 whose node is connected to the collector of the NPN transistor Tr1. have. Both ends of diode D4 are used as OUT2 terminals that drive relay 4. ing.

0010 Next, refer to the waveform of the operation signal and the signal timing chart of this embodiment shown in Figure 2. and explain its operation.

[0011] First, a voltageless contact momentary signal (watchdog signal) from the switch 2 shorts both ends of the capacitor C1 during a time Ts which is a signal period. Then, capacitor C1 is discharged, and the output terminal of operational amplifier A1 is connected to the negative input terminal of operational amplifier A1 through resistor R5, diode D1, and capacitor C1, so operational amplifier A1 becomes a voltage follower type, and its output voltage V _A becomes positive. The voltage at the input terminal falls to (-V _L ), that is, -V _L =V1·r1/(r1+r2). (However, -V1 is the voltage of the negative power supply E1, and r1 and r2 are the resistance values of the resistors R1 and R2, respectively. The same applies hereinafter.) When the switch 2 is turned off after the time Ts and both ends of the capacitor C1 are opened. , the capacitor C1 is charged by the current I flowing through the resistor R3, and the operational amplifier A1, the resistor R3, and the capacitor C1 start operating as an integrator. Here, the potential difference V3 across the resistor R3 is V3=-V1·r1/(r1+r2), and the integrated current I of the capacitor C1 at this time is I=V3/r3. The capacitor C1 is linearly charged by this integrated current I, and the output voltage V _A of the operational amplifier A1 rises accordingly. If diodes D1, D2, and D3 are chosen to have the same forward voltage Vd, when the output voltage V _A of operational amplifier A1 reaches that value Vd, it was turned off because the output voltage V _A was lower than the forward voltage Vd. Diode D2 turns on, suppressing the value of output voltage V _A to forward voltage Vd. When the integrated current I further flows into the capacitor C1, it pushes down the positive input terminal voltage of the operational amplifier A1, the virtual short circuit of the operational amplifier A1 is broken, and the output voltage V _A of the operational amplifier A1 rises to the positive saturation voltage (+V _L ). .

Note that when the operational amplifier A1 is operating as an integrator (V _A <Vd), the diode D3 separates the analog timer circuit 1 from the relay drive circuit 3, and when the output voltage V _A is equal to or higher than its forward voltage Vd. This is for supplying an output to the relay drive circuit 4, which is the load, only when the load is reached.

This analog timer circuit 1 has circuit constants such that the resistance values r1 to r5 of the resistors R1 to R5 are r1=82KΩ, r2=330KΩ, r3=r4=20KΩ, r5=22KΩ, and the voltage of the negative power supply E1 - When V1 is -15V, the integration time rate C _T of the integrator is approximately 0.01 μF/sec. The integration time Td is C1/CT, and if the capacitance of the capacitor C1 is 1 μF, the integration time Td has a relatively long time constant of 100 seconds. The analog timer circuit 1 is characterized in that the capacitor C1 is not charged according to an exponential charging/discharging curve, but is linearly charged and integrated over a wide voltage range of the positive input terminal potential difference -V _L of the operational amplifier A1. do. As a result, the timing at which the charging curve crosses the set value (time) is constant, allowing relatively stable and accurate timer operation.

When the OUT1 terminal of the analog timer circuit 1 and the IN2 terminal of the relay drive circuit 3 are connected, the NPN transistor Tr1 is in an off state while the output voltage V _A of the operational amplifier A1 is equal to or lower than the forward voltage Vd of the diode D3. , after the integration time Td has passed, when the output voltage V _A reaches the positive saturation voltage +V _L (≧Vd), the NPN transistor Tr1 is turned on. Then, the emitter-collector voltage V _CE decreases, driving the relay 4 on.

[0015] In this way, the analog timer circuit 1 operates after the switch 2 is turned on. The sum of the dog signal period Ts and the integration time Td of the integrator (Ts〈〈Td) Functions as an interval timer.

[0016] FIG. 3 is a diagram illustrating signal timing in this embodiment.

When momentary signal sequences P1, P2, P3, P4 with pulse width Ts are input to the IN1 terminal at intervals of time T1, T2, T3, the integration time Td of the analog timer circuit 1 is equal to the interval time T1, T2. , T3, the integration operation of the analog timer circuit 1 is reset at the timing of each of the momentary signals P1 to P4. At this time, the output voltage V _A of the operational amplifier A1 is below OV.

On the other hand, when the momentary signal P4 is not input, the output voltage _{V A} of the operational amplifier A1 reaches positive saturation when the signal period Ts and the integration time Td elapse after being reset at the position of the momentary signal P4. The voltage becomes +V _L and the NP-N transistor Tr1 of the relay drive circuit 3 is turned on. Then, the collector-emitter voltage _VCE of the NPN transistor Tr1 drops to nearly OV, turning on the relay 4.

[0019] In this way, with the watchdog monitoring timer value as the integration time Td, the capacitor C1 Determine the capacitance of the pulse train of the momentary signal and use it as the watchdog signal of the control system. If the watchdog signal is interrupted due to a failure in the control system, the It is passed to the external circuit as a watchdog timer alarm signal through the relay drive circuit 3. I can know.

[0020]

[Effect of the idea]

As explained above, the watchdog timer circuit of the present invention is a control system health check. check signal (watchdog signal) with no-voltage contact signal (momentary pulse) and integrate it for a predetermined period of time from the point of the input signal, and during the integration When the next watchdog signal is input to Repeat the integral operation. Then, a failure occurs in the control system and the watchdog signal is interrupted. When the watchdog signal is lost, the watchdog signal is output after the aforementioned integration time has elapsed since the previous watchdog signal was input. Outputs the touchdog alarm signal to the external circuit.

[0021] In this way, the watchdog timer circuit of the present invention can also be used for analogs operating at low frequencies. Since it is a log timer, it does not generate EMI noise, etc., and has no negative impact on the outside. can be excluded. Also, as an analog timer, it is suitable for long-term monitoring and is stable. It has the effect of operating as follows.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a timing chart diagram of operation waveforms and signals of the embodiment.

FIG. 3 is a diagram illustrating signal timing in the embodiment.

[Explanation of symbols]

1 Analog timer circuit 2 switch 3 Relay drive circuit 4 relay A1 operational amplifier C1 capacitor D1~D4 Diode E1 negative power supply E2 Positive power supply R1~R7 resistance Tr1 NPN transistor

Claims (2)

[Scope of utility model registration request] 1. An operational amplifier having positive and negative signal input terminals and a signal output terminal; a bias resistor circuit that applies bias to the positive and negative input terminals and also serves as a part of an integrating circuit; a resistor connected to the output end of the operational amplifier; a first diode having an anode connected to the other end of the resistor; and a first diode connected between the cathode of the first diode and the negative input end of the operational amplifier. a second diode, the anode of which is connected to the other end of the resistor and the cathode of which is grounded; a watchdog signal, which is a no-voltage contact signal, is input to both ends of the capacitor; A watchdog timer circuit characterized by outputting a watchdog alarm signal. 2. The integrating circuit includes the operational amplifier, the bias resistor circuit, the resistor, the first diode, and the capacitor, and the time constant of the integrating circuit is such that when the watchdog signal is interrupted even once, 2. The watchdog timer circuit according to claim 1, wherein said watchdog alarm signal is determined to be output.