JPS6235567A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6235567A
JPS6235567A JP17603385A JP17603385A JPS6235567A JP S6235567 A JPS6235567 A JP S6235567A JP 17603385 A JP17603385 A JP 17603385A JP 17603385 A JP17603385 A JP 17603385A JP S6235567 A JPS6235567 A JP S6235567A
Authority
JP
Japan
Prior art keywords
collector layer
transistor
silicon
collector
thick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17603385A
Other languages
Japanese (ja)
Inventor
Kiichi Nishikawa
毅一 西川
Tadashi Hirao
正 平尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17603385A priority Critical patent/JPS6235567A/en
Publication of JPS6235567A publication Critical patent/JPS6235567A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To form a transistor having a thick collector layer and a transistor having a thin collector layer on the same substrate, and to form a collector wall by shallow diffusion without surrounding a base layer by forming in advance a step on a portion formed with the thick collector layer and then forming a thin collector layer. CONSTITUTION:An oxide film 2 is patterned on a portion to form a thick collector layer on a substrate 1, and silicon-etched. Then, an N-type high density diffused layer 4 is formed on the surface, an oxide film is patterned on a portion to form a thin collector layer, a separating silicon portion is removed and oxidized thereafter similarly to the conventional manufacturing method, a polysilicon 6 is laminated in a V-shaped groove 3 removed with the silicon, the back surface is polished to form a silicon island of a transistor. Here, the collector wall of a transistor having a thin collector wall is formed only on one side.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は同一基板上に厚さの異なるシリコン島領域を
有する半導体装置およびその製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having silicon island regions having different thicknesses on the same substrate and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

周知のように、高耐圧用トランジスタはコレクタ層を厚
くする必要がある。第2図は厚いコレクタ層を有するI
〜ランジスクを含む従来の半導体装置およびその製造方
法の主要工程における各状態をそれぞれ示す断面図であ
る。このような半導体装置を製造するには、まず、第2
図+a+に示すように、n型(100)基板(1)の上
に酸化膜(2)をバターニングした後、この酸化膜(2
)をマスクとしてアルカリ系エンチング液で異方性エン
チングを行い、(111)面を側面にもったV字溝(3
)を形成する。続いて、第2図(blに示すように、基
板(1)の表面にn型高沼度拡散層(4)を形成し、さ
らに酸化膜(5)を形成する。
As is well known, high voltage transistors require a thick collector layer. Figure 2 shows I with a thick collector layer.
- FIGS. 3A and 3B are cross-sectional views showing each state in the main steps of a conventional semiconductor device including a run disk and a method for manufacturing the same. To manufacture such a semiconductor device, first, the second
As shown in Figure +a+, after patterning an oxide film (2) on an n-type (100) substrate (1), this oxide film (2)
) was used as a mask to perform anisotropic etching with an alkaline etching solution to form a V-shaped groove (3) with (111) planes on the sides.
) to form. Subsequently, as shown in FIG. 2 (bl), an n-type high-intensity diffusion layer (4) is formed on the surface of the substrate (1), and an oxide film (5) is further formed.

次に、第2図(C1に示すように、7字溝(3)の上部
にポリシリコン(6)を数百μm程度積層し、店板(1
1の裏面を研磨して酸化膜(5)を露出させる。ここで
、基板(1)の研磨面を新たな基板表面とする。続いて
、第2図(dlに示すように、この新たな基板表面にベ
ース(7)、エミッタ(8)を形成し、さらに、基板(
1)の表面を酸化して各コンタクト芯を形成後、配線を
施して所望の工程を完了する。
Next, as shown in Figure 2 (C1), polysilicon (6) is laminated to a thickness of several hundred μm on the top of the 7-shaped groove (3), and the shop board (1
The back surface of 1 is polished to expose the oxide film (5). Here, the polished surface of the substrate (1) is defined as a new substrate surface. Subsequently, as shown in FIG. 2 (dl), a base (7) and an emitter (8) are formed on the surface of this new substrate, and the substrate (
After forming each contact core by oxidizing the surface of step 1), wiring is applied to complete the desired process.

第2図[al〜fdlに示した半導体装置の製造方法に
おいては、第2図Fdlから明らかなように、コレクタ
ウオール(9)がベース(7)を取り囲んで形成されて
しまう。そこで、コレクタウオール(9)をベース(7
)を取り囲まないように形成する方法として第3図ta
)〜td)に示す製造方法が従来から知られている。
In the method for manufacturing a semiconductor device shown in FIGS. 2[al to fdl, as is clear from FIG. 2Fdl, the collector wall (9) is formed surrounding the base (7). Therefore, we used the collector all (9) as the base (7
) is shown in Figure 3.
) to td) are conventionally known.

この製造方法では、まず第3図talに示すように、n
型(100)基板(I)の表面にn型高濃度拡散層(4
)を形成し、酸化膜(2)をパターニングする。次に、
第3図(blに示すように、酸化膜(2)をマスクとし
て異方性エツチングを行い7字溝(3)を形成し、さら
に酸化膜(5)を形成する。続いて、第3図(C)に示
すように、ポリシリコン(6)を積層し、基板(11の
裏面を研磨し酸化膜(5)を露出させる。次に、第3図
(dlに示すように、研磨面を新たな基板表面にして、
コレクタウオール(9)をシリコン島領域の一側面にだ
け形成し、さらにベース(7)とエミッタ(8)とを形
成し、各コンタクト窓形成後配線を施して所望の工程を
完了する。
In this manufacturing method, first, as shown in FIG.
An n-type high concentration diffusion layer (4) is formed on the surface of the type (100) substrate (I).
) and pattern the oxide film (2). next,
As shown in FIG. 3 (bl), anisotropic etching is performed using the oxide film (2) as a mask to form a 7-shaped groove (3), and then an oxide film (5) is formed.Subsequently, as shown in FIG. As shown in (C), polysilicon (6) is laminated, and the back surface of the substrate (11) is polished to expose the oxide film (5).Next, as shown in Figure 3 (dl), the polished surface is As a new board surface,
A collector wall (9) is formed only on one side of the silicon island region, a base (7) and an emitter (8) are further formed, and after each contact window is formed, wiring is provided to complete the desired process.

以上のようにして、厚いコレクタ層を有する高耐圧用ト
ランジスタを含む半導体装置が得られる。
In the manner described above, a semiconductor device including a high voltage transistor having a thick collector layer is obtained.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の半導体装置は以上のように構成されているので、
厚いコレクタ層を有するトランジスタと薄いコレクタ層
を有するトランジスタを一緒に含むことができず、耐圧
をそれほど必要としないトランジスタでも高耐圧用トラ
ンジスタと同一基板上に形成する場合には、コレクタ層
が1¥くならざるを得ないという問題点があった。
Conventional semiconductor devices are configured as described above, so
If a transistor with a thick collector layer and a transistor with a thin collector layer cannot be included together, and even a transistor that does not require a high withstand voltage is formed on the same substrate as a high withstand voltage transistor, the collector layer must be 1 yen. There was a problem in that it had no choice but to become

また、従来の半導体装置の製造方法は、高耐圧用トラン
ジスタと耐圧をそれほど必要としないトランジスタとを
同一基板上に形成する場合、耐圧をそれぼど必要としな
いトランジスタでもコレクタ層の厚さを高耐圧用トラン
ジスタのコレクタ層の厚さに合わせて厚くしなければな
らず、集積度ならびに周波数特性などが向上しないとい
う問題点があった。
In addition, in conventional semiconductor device manufacturing methods, when a high-voltage transistor and a transistor that does not require a high breakdown voltage are formed on the same substrate, the thickness of the collector layer is increased even for the transistor that does not require a high breakdown voltage. The thickness must be increased to match the thickness of the collector layer of the breakdown voltage transistor, which poses a problem in that the degree of integration and frequency characteristics are not improved.

また、コレクタウオールを高耐圧用トランジスタに形成
する場合、第2図+dlに示すように、コレクタウオー
ル(9)がI・ランジスタの両側面にできたり、第3図
+dlに示すように、コレクタウオール(9)が横方向
にも拡散してしまうなど、コレクタウオール(9)の形
成に伴ってトランジスタサイズが大きくなってしまうな
どの問題点があった。
In addition, when forming a collector all in a high-voltage transistor, collector all (9) may be formed on both sides of the I transistor as shown in Fig. 2 +dl, or collector all (9) may be formed on both sides of the I transistor as shown in Fig. 3 +dl. There were problems such as the transistor size increasing due to the formation of the collector all (9), such as that (9) was also diffused in the lateral direction.

この発明は上記のような問題点を解消するためになされ
たもので、厚いシリコン島9■域と薄いシリコン島領域
とを備える半導体装置を提供することを目的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device having a thick silicon island region 9 and a thin silicon island region.

また、この発明の別の発明は、異なった厚さのコレクタ
層を有するトランジスタを集積度を高めて同一基板上に
形成すると同時に、浅い拡散でコレクタウオールをベー
ス層を囲まずに形成する半導体装置の製造方法を提供す
ることを目的とする。
Another invention of the present invention is a semiconductor device in which transistors having collector layers of different thicknesses are formed on the same substrate with an increased degree of integration, and at the same time, a collector layer is formed by shallow diffusion without surrounding the base layer. The purpose is to provide a manufacturing method for.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

この発明に係る半導体装置は、絶縁基板上に2段になっ
た厚いシリコン島令頁域と、°この厚いシリコン島領域
の1段目と同程度の厚さを有する薄いシリコン島領域と
を設けるようにしたものである。
A semiconductor device according to the present invention includes a two-tier thick silicon island area on an insulating substrate, and a thin silicon island area having a thickness comparable to that of the first layer of the thick silicon island area. This is how it was done.

また、この発明の別の発明に係る半導体装置の製造方法
は、厚いコレクタ層を形成する部分に段差をあらかじめ
形成しておき、次に薄いコレクタ層を従来の方法で形成
させることで、厚いコレクタ層を有するトランジスタと
薄いコレクタ層を有するトランジスタとを同一基板上に
形成するものである。
Further, in a method for manufacturing a semiconductor device according to another aspect of the present invention, a step is formed in advance in a portion where a thick collector layer is to be formed, and then a thin collector layer is formed by a conventional method, thereby forming a thick collector layer. A transistor having a thin collector layer and a transistor having a thin collector layer are formed on the same substrate.

〔作用〕[Effect]

この発明における半導体装置は、厚いシリコン島領域と
薄いシリコン島領域とを併せ持つことができることによ
り、高耐圧用トランジスタを含む集積回路の集積度を高
めたり、周波数特性を向上させたりすることができる。
Since the semiconductor device according to the present invention can have both a thick silicon island region and a thin silicon island region, it is possible to increase the degree of integration of an integrated circuit including a high voltage transistor and to improve frequency characteristics.

また、この発明の別の発明における半導体装置の製造方
法は、従来のV字溝の形成に先立って厚いコレクタ層を
形成する部分以外をシリコンエツチングにより除去し、
次いで酸化膜をマスクに2回目のソリコンエツチングを
行って浅い溝を形成し、厚いコレクタ層を有するトラン
ジスタと薄いコレクタ層を有するトランジスタとを同時
に形成する。
Further, in a method for manufacturing a semiconductor device according to another aspect of the present invention, prior to forming a conventional V-shaped groove, a portion other than a portion where a thick collector layer is to be formed is removed by silicon etching,
Next, a second silicon etching process is performed using the oxide film as a mask to form shallow grooves, thereby simultaneously forming a transistor with a thick collector layer and a transistor with a thin collector layer.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図(δ)〜+flは、この発明の一実施例による半導体
装置およびその製造方法の主要工程における各状態をそ
れぞれ示す断面図である。この実施例の製造方法におい
て、第2図(al〜(diに示した従来の製造方法と異
なる点は、第1図(a)に示すように、V字溝(3)の
形成に先立って厚いコレクタ層の部分にあたる部分を残
してシリコン基板+1)を選択的にエツチングした点に
ある。
An embodiment of the present invention will be described below with reference to the drawings. 1st
Figures (δ) to +fl are cross-sectional views showing each state in the main steps of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention. The manufacturing method of this embodiment differs from the conventional manufacturing method shown in FIGS. 2(a-1) to (di) as shown in FIG. The point is that the silicon substrate +1) is selectively etched leaving a portion corresponding to the thick collector layer.

まず、第1図ta+に示すように、基板+1j上の厚い
コレクタ層を形成すべき部分に酸化膜(2)をバターニ
ングしシリコンエツチングを施す。次いで、第1図[b
lに示すように、表面にn型高濃度拡散層(4)を形成
し、薄いコレクタ層を形成すべき部分に酸化膜をバター
ニングし、以降は従来の製造方法と同様にして、分離す
るシリコン部分を除去しく第11(c+参照)、酸化を
行い(第1図idl参照)、次いで、シリコンを除去し
たV字溝(3)にポリシリコン(6)を積層し、裏面を
研磨して(第1図(e))、トランジスタのシリコン島
を形成する。ここで、薄いコレクタウオールを有するト
ランジスタのコレクタウオールは、第3図ff)に示す
ように、一方の側面にだけ形成する。
First, as shown in FIG. 1 (ta+), an oxide film (2) is buttered and silicon etched on a portion of the substrate +1j where a thick collector layer is to be formed. Next, FIG. 1 [b
As shown in Fig. 1, an n-type high concentration diffusion layer (4) is formed on the surface, and an oxide film is buttered in the area where a thin collector layer is to be formed. Step 11 (see c+) to remove the silicon part, oxidize (see Figure 1 IDl), then stack polysilicon (6) in the V-shaped groove (3) from which the silicon was removed, and polish the back surface. (FIG. 1(e)), a silicon island of a transistor is formed. Here, the collector all of a transistor having a thin collector all is formed only on one side, as shown in FIG. 3ff).

上記製造方法より厚いコレクタ層を有するトランジスタ
と薄いコレクタ層を有するトランジスタとの2種類のト
ランジスタを同一4−54H上に形成できる。また、薄
いコレクタ層のコレクタウオールとともに厚いコレクタ
層のコレクタウオールもン曳い拡散により形成され、コ
レクタ層の一側面にだけコレクタウオールを形成するこ
ともできる。このように、コレクタウオールが浅い拡散
によりコレクタ層の一側面にだけ形成できるので、横方
向拡散が少なく、素子分離の余裕度が小さくてすみ、高
耐圧用トランジスタを含む半導体装置の微細化に役立つ
By the above manufacturing method, two types of transistors, one having a thick collector layer and the other having a thin collector layer, can be formed on the same 4-54H. Further, the collector all of the thick collector layer is also formed by drag diffusion together with the collector all of the thin collector layer, and the collector all can be formed only on one side of the collector layer. In this way, since the collector all can be formed only on one side of the collector layer by shallow diffusion, there is less lateral diffusion and less margin for element isolation, which is useful for miniaturization of semiconductor devices including high voltage transistors. .

なお、上記実施例ではシリコンエツチングの深さを制御
しやすくするために選択エツチングをしてV字溝を形成
したが、通常のシリコンエツチングで溝を形成してもよ
く、このときは(1,00)に限らず他の方位をもった
シリコン基板を用いてもよい。また、逆に最初のシリコ
ンエツチングを選択的に行ってもよいことはもちろんで
ある。
In the above embodiment, the V-shaped groove was formed by selective etching in order to easily control the depth of silicon etching, but the groove may also be formed by normal silicon etching. 00), and silicon substrates having other orientations may also be used. Moreover, it goes without saying that the first silicon etching may be performed selectively.

また、基板支持膜としてポリシリコンを使用したが、こ
の基板支持膜はアモルファスシリコン膜でもよく、さら
に後工程への影響(例えば、汚染や熱歪みによる反りや
割れなど)がなければ、絶縁膜、金属膜、さらには有機
物質膜であってもよい。
In addition, although polysilicon was used as the substrate support film, the substrate support film may also be an amorphous silicon film, and as long as it does not affect subsequent processes (for example, warping or cracking due to contamination or thermal distortion), an insulating film, It may be a metal film or even an organic material film.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば半導体装置を厚いシリ
コン島領域と薄いシリコン島領域とを備えるように構成
したので、高耐圧用トランジスタを含みながら集積度を
高めたり、周波数特性を向上させたりしたものが得られ
る効果がある。
As described above, according to the present invention, a semiconductor device is configured to include a thick silicon island region and a thin silicon island region, so that it is possible to increase the degree of integration and improve frequency characteristics while including a high voltage transistor. There is an effect that you get what you do.

また、この発明の別の発明によれば、半導体装置の製造
方法を初めに半導体基板上のシリコンの一部を残して除
去する工程を含むように構成したので、厚いコレクタ層
を有するトランジスタを薄いコレクタ層を有するトラン
ジスタとともに形成でき、さらにコレクタウオールを浅
い拡散により形成できるために高耐圧用トランジスタを
含む高集積度半導体装置を製造することができる効果が
ある。
According to another aspect of the present invention, the method for manufacturing a semiconductor device is configured to include the step of first removing silicon on the semiconductor substrate, leaving only a portion of the silicon on the semiconductor substrate. Since it can be formed together with a transistor having a collector layer, and furthermore, the collector layer can be formed by shallow diffusion, it is possible to manufacture a highly integrated semiconductor device including a high breakdown voltage transistor.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(8)〜(flは本発明の一実施例による半導体
装置とその製造方法の主要工程における各状態をそれぞ
れ示す断面図、第2図tal〜fd+は従来の半導体装
置の一例とその製造方法の主要工程における各状態をそ
れぞれ示す断面図、第3図+al〜(dlは従来の半導
体装置の他の例とその製造方法の主要工程における各状
態をそれぞれ示す断面図である。 (11はn型(100) M板、(2)は?スフ酸化膜
、(3)はV字溝、(4)はn型高濃度拡散層、(5)
は酸化膜、(6)はポリシリコン、(7)はベース、(
8)はエミ、夕、(9)はコレクタウオール、(1o)
は薄いコレクタ層を有するトランジスタ、(11)は厚
いコレクタ層を有する1−ランジスタ。 なお、図中、同一符号は同一または相当部分を示す。
FIGS. 1(8) to (fl) are cross-sectional views showing each state in the main steps of a semiconductor device and its manufacturing method according to an embodiment of the present invention, and FIGS. 2(a) to (fd+) show an example of a conventional semiconductor device and its Cross-sectional views showing each state in the main steps of the manufacturing method, FIGS. is an n-type (100) M plate, (2) is a double oxide film, (3) is a V-shaped groove, (4) is an n-type high concentration diffusion layer, (5)
is an oxide film, (6) is polysilicon, (7) is a base, (
8) is Emi, Yu, (9) is Collector All, (1o)
(11) is a transistor with a thin collector layer, and (11) is a 1-transistor with a thick collector layer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁基板上に2段になった厚いシリコン島領域と
、この厚いシリコン島領域の1段目と同程度の厚さを有
する薄いシリコン島領域とを備えることを特徴とする半
導体装置。
(1) A semiconductor device comprising a thick silicon island region formed in two stages on an insulating substrate, and a thin silicon island region having a thickness comparable to that of the first stage of the thick silicon island region.
(2)一方導電型の半導体基板上の所望の領域以外のシ
リコンを除去する工程と、上記半導体基板の表面に濃度
の高い一方導電型の拡散領域を形成する工程と、上記半
導体基板上の所望の領域のシリコンを除去する工程と、
上記半導体基板の表面に絶縁膜を形成する工程と、上記
半導体基板上に基板支持膜を積層する工程と、上記半導
体基板の裏面より研磨し上記絶縁膜を露出させる工程と
、上記絶縁膜を露出させた面を新たな上記半導体基板の
表面としてこの表面からシリコン島の所望の領域に濃度
の高い一方導電型の拡散層を形成する工程とを含むこと
を特徴とする半導体装置の製造方法。
(2) a step of removing silicon from a region other than a desired region on a semiconductor substrate of one conductivity type; a step of forming a diffusion region of a high concentration of one conductivity type on the surface of the semiconductor substrate; a step of removing silicon in the area;
a step of forming an insulating film on the surface of the semiconductor substrate; a step of laminating a substrate support film on the semiconductor substrate; a step of polishing the back surface of the semiconductor substrate to expose the insulating film; and a step of exposing the insulating film. A method for manufacturing a semiconductor device, comprising the step of forming a high concentration diffusion layer of one conductivity type from this surface in a desired region of a silicon island, using the surface thus obtained as a new surface of the semiconductor substrate.
JP17603385A 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof Pending JPS6235567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17603385A JPS6235567A (en) 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17603385A JPS6235567A (en) 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6235567A true JPS6235567A (en) 1987-02-16

Family

ID=16006547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17603385A Pending JPS6235567A (en) 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6235567A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4960687A (en) * 1972-10-13 1974-06-12
JPS5516443A (en) * 1978-07-24 1980-02-05 Hitachi Ltd Semiconductor device and its production method
JPS55105340A (en) * 1979-01-23 1980-08-12 Nec Corp Semiconductor device and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4960687A (en) * 1972-10-13 1974-06-12
JPS5516443A (en) * 1978-07-24 1980-02-05 Hitachi Ltd Semiconductor device and its production method
JPS55105340A (en) * 1979-01-23 1980-08-12 Nec Corp Semiconductor device and its manufacturing method

Similar Documents

Publication Publication Date Title
US5136354A (en) Semiconductor device wafer with interlayer insulating film covering the scribe lines
US5286673A (en) Method for forming position alignment marks in a manufacturing SOI device
US6677193B2 (en) Method of producing semiconductor device and its structure
JPS6235567A (en) Semiconductor device and manufacture thereof
JPS6039848A (en) Manufacture of semiconductor device
JPH03270254A (en) Manufacture of semiconductor device
JP2786199B2 (en) Method for manufacturing thin film semiconductor device
JPS6258541B2 (en)
JPH08298314A (en) Nonvolatile semiconductor memory and its manufacture
JPS61119056A (en) Manufacture of semiconductor device
JP3216488B2 (en) Method for manufacturing semiconductor device
JPH10326896A (en) Semiconductor device and manufacture thereof
JP3189320B2 (en) Method for manufacturing semiconductor device
JP2961860B2 (en) Method for manufacturing semiconductor device
JP3688860B2 (en) Manufacturing method of semiconductor integrated circuit
JP2001274388A (en) Semiconductor device and manufacturing method thereof
JPH10321549A (en) Manufacture of semiconductor substrate
KR0166039B1 (en) Capacitor fabrication method of semiconductor device
JPH0243766A (en) Manufacture of semiconductor memory device
JPH04317357A (en) Manufacture of semiconductor device
JPS6278851A (en) Formation of fine contact hole
JP2940484B2 (en) Semiconductor memory device and method of manufacturing the same
JPH01162358A (en) Formation of laminar-structure mis semiconductor device
JPH1050824A (en) Manufacture of soi board
JPH01140667A (en) Semiconductor device