JPS6235267B2 - - Google Patents
Info
- Publication number
- JPS6235267B2 JPS6235267B2 JP8682480A JP8682480A JPS6235267B2 JP S6235267 B2 JPS6235267 B2 JP S6235267B2 JP 8682480 A JP8682480 A JP 8682480A JP 8682480 A JP8682480 A JP 8682480A JP S6235267 B2 JPS6235267 B2 JP S6235267B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- film
- etching
- semiconductor device
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 239000005360 phosphosilicate glass Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000004880 explosion Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001015 X-ray lithography Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Description
【発明の詳細な説明】
本発明は、溝状素子間分離領域を有する半導体
装置を製造するのに好適な方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method suitable for manufacturing a semiconductor device having a trench-like element isolation region.
従来、半導体装置に於ける素子間分離領域を溝
状に形成する所謂グルーブド・アイソーレーシヨ
ン(grooved isolation)技術が知られている。 2. Description of the Related Art Conventionally, a so-called grooved isolation technique is known in which an isolation region between elements in a semiconductor device is formed in a groove shape.
これは、例えば、第1図に見られるように、シ
リコン半導体基板1に深さ例えば3〔μm〕、幅
例えば1〔μm〕の溝2は形成し、全面に厚さ例
えば〔Å〕の熱酸化膜3を形成し、更に全面に化
学気相成長(CVD)法に依り二酸化シリコン膜
4を形成するものである。 For example, as shown in FIG. 1, a trench 2 with a depth of, for example, 3 [μm] and a width of, for example, 1 [μm] is formed in a silicon semiconductor substrate 1, and the entire surface is heated to a thickness of, for example, [Å]. An oxide film 3 is formed, and a silicon dioxide film 4 is further formed on the entire surface by chemical vapor deposition (CVD).
この技術に依つて形成した素子間分離領域は平
面で見た占有面積が小さいので半導体装置を高集
積化するのに有効である。 Since the element isolation region formed by this technique occupies a small area when viewed in plan, it is effective for highly integrating semiconductor devices.
しかしながら、前記素子間分離領域には甚だ大
きな欠点が在る。それは、図に見られるように、
CVD法で二酸化シリコン膜4を形成した際、内
部に鬆4′が生成され易いことである。このよう
な鬆4′が存在すると、後の工程で例えば表面の
二酸化シリコン膜4をエツチングする必要ある場
合、そのエツチングに依つて鬆4′の一部が現わ
れてしまうと、鬆4′は更に拡大されて空洞化
し、溝2内を二酸化シリコン膜4で埋めようとす
る目的は達成できない。 However, the device isolation region has serious drawbacks. As can be seen in the figure,
When the silicon dioxide film 4 is formed by the CVD method, voids 4' are likely to be generated inside. If such a hole 4' exists, when it is necessary to etch the silicon dioxide film 4 on the surface in a later step, if a part of the hole 4' is exposed due to the etching, the hole 4' will be further removed. The purpose of filling the groove 2 with the silicon dioxide film 4 by enlarging it into a cavity cannot be achieved.
また、鬆4′が存在する状態でその後の半導体
装置製造工程を経続して熱処理などを行なうと、
鬆4′に封じ込められた気体が熱膨脹して爆発を
起し、装置が破壊されるような事故も発生する。 Additionally, if heat treatment is performed in the subsequent semiconductor device manufacturing process with the 4′ present,
Accidents may also occur in which the gas trapped in the cap 4' expands thermally and causes an explosion, destroying the device.
前記欠点を解消する為、第2図に見られる構成
の素子間分離領域が提案されている。即ち、この
従来例では、溝2の側壁にテーパを持たせるよう
にしたものである。このようにすると、二酸化シ
リコン膜4に鬆が形成される可能性は少なくな
る。しかしながら、側壁にテーパを有する溝2を
再現性、制御性ともに良好に形成することは容易
でない。即ち、この種の溝は、通常、リアクチ
ブ・イオン・エツチング(RIE)法を適用して形
成するが、前記のようにテーパを付する為には、
エツチング・ガスの成分比、エツチング・ガスの
圧力、高周波パワなどを特別に制御しなければな
らず、また、再現性は良くない。 In order to eliminate the above-mentioned drawbacks, an element isolation region having the configuration shown in FIG. 2 has been proposed. That is, in this conventional example, the side walls of the groove 2 are tapered. In this way, the possibility that cavities will be formed in the silicon dioxide film 4 is reduced. However, it is not easy to form grooves 2 having tapered side walls with good reproducibility and controllability. That is, this type of groove is usually formed by applying the reactive ion etching (RIE) method, but in order to create the taper as described above,
The component ratio of the etching gas, the pressure of the etching gas, the high frequency power, etc. must be specially controlled, and the reproducibility is not good.
本発明は、溝内に埋めた絶縁物に鬆を持たない
素子間分離領域を容易に形成できるようにするも
のであり、以下これを詳細に説明する。 The present invention makes it possible to easily form an isolation region between elements without a cavity in an insulator buried in a trench, and this will be described in detail below.
第3図乃至第7図は本発明一実施例を説明する
為の工程要所に於ける半導体装置の要部側断面説
明図であり、次に、これ等の図を参照しつつ記述
する。 3 to 7 are sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.
第3図参照
(1) シリコン半導体基板11に例えば熱酸化法を
適用し、厚さ例えば4000〔Å〕程度の二酸化シ
リコン膜を形形成し、それを例えばX線リソグ
ラフイ技術、電子ビーム・リソグラフイ技術等
の適当な技術にてパターニングし、幅1〔μ
m〕程度の開口を形成する。Refer to Fig. 3 (1) For example, a thermal oxidation method is applied to the silicon semiconductor substrate 11 to form a silicon dioxide film having a thickness of, for example, about 4000 [Å], and then it is processed using, for example, X-ray lithography technology or electron beam lithography. Patterning is performed using an appropriate technique such as A technique, and the width is 1 [μ
m].
(2) 前記二酸化シリコン膜をマスクとしてシリコ
ン半導体基板11をFIE法にてエツチングし、
幅1〔μm〕程度、深さ例えば1〔μm〕程度
の溝12を形成する。(2) Etching the silicon semiconductor substrate 11 by FIE method using the silicon dioxide film as a mask,
A groove 12 having a width of about 1 [μm] and a depth of, for example, about 1 [μm] is formed.
(3) 二酸化シリコン膜を除去してから等方性プラ
ズマ・エツチング法、等方性化学ウエツト・エ
ツチング法などを適用してエツチングを行なう
と図示のように溝12の表面角部に円み12′
が付される。その際、溝12の深部には反応原
子が殆んど供給されないので殆んどエツチング
はされない。(3) After removing the silicon dioxide film, if etching is performed by applying an isotropic plasma etching method, isotropic chemical wet etching method, etc., the surface corner of the groove 12 will have a circular shape 12 as shown in the figure. ′
is attached. At this time, since almost no reactive atoms are supplied to the deep part of the groove 12, almost no etching is performed.
第4図参照
(4) 例えば熱酸化法を適用して厚さ例えば1000
〔Å〕程度の酸化膜13を成長させる。See Figure 4 (4) For example, by applying the thermal oxidation method, the thickness of
An oxide film 13 of about [Å] is grown.
第5図参照
(5) 化学気相成長(CVD)法を適用し、厚さ例
えば3500〔Å〕程度の燐珪酸ガラス(PSG)膜
14を形成する。Refer to FIG. 5 (5) A phosphosilicate glass (PSG) film 14 having a thickness of, for example, about 3500 [Å] is formed by applying a chemical vapor deposition (CVD) method.
第6図参照
(6) 例えば温度1100〔℃〕、時間30〔分〕程度の
熱処理を行ないPSG膜14を溶融する。これに
依り、表面のPSGは溶けて溝12内に流れ込
み、空所を或る程度埋める。Refer to FIG. 6 (6) For example, heat treatment is performed at a temperature of 1100 [° C.] for about 30 [minutes] to melt the PSG film 14. As a result, the PSG on the surface melts and flows into the groove 12, filling the void to some extent.
第7図参照
(7) 再びCVD法に依りPSG膜の成長を行なつて
から熱処理に依つて溶融すると図示のように溝
12内はPSG膜14にて密実に埋められ、ま
た、表面は平担になる。Refer to Figure 7 (7) When the PSG film is grown again using the CVD method and then melted by heat treatment, the inside of the groove 12 is densely filled with the PSG film 14 as shown in the figure, and the surface is flat. I will be in charge.
以上の説明で判るように、本発明に依れば、半
導体基板をリアクチブ・スパツタ・エツチングし
て略垂直に切立つた側壁を有する溝を形成してか
ら等方性エツチングを行なつて該溝の表面角部に
円みを持たせ、薄い絶縁膜を形成してからガラス
膜の形成及びその溶融を複数回繰返して溝内を該
ガラスで密実に埋めるとともに表面を平担にして
いるので、溝内のガラスに鬆や空洞は発生しな
い。従つてその後の熱処理工程を経ても爆発など
は起らず、そして、長期に亘り信頼性を維持でき
る半導体装置を容易に製造することができるもの
である。 As can be seen from the above description, according to the present invention, a semiconductor substrate is reactive sputter etched to form a groove having substantially vertical sidewalls, and then isotropic etching is performed to form the groove. The corners of the surface are rounded, a thin insulating film is formed, and the glass film is repeatedly formed and melted several times to fill the grooves densely with the glass and flatten the surface. No cavities or cavities occur in the glass within the groove. Therefore, no explosion occurs even after the subsequent heat treatment process, and it is possible to easily manufacture a semiconductor device that can maintain reliability over a long period of time.
第1図及び第2図は従来技術を説明する為の工
程要所に於ける半導体装置の要部側断面説明図、
第3図乃至第7図は本発明一実施例を説明する為
の工程要所に於ける半導体装置の要部側断面説明
図である。
図に於いて、11は基板、12は溝、12′は
円み、13は酸化膜、14はPSG膜である。
1 and 2 are side cross-sectional explanatory views of main parts of a semiconductor device at key points in the process for explaining the conventional technology;
3 to 7 are side cross-sectional views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention. In the figure, 11 is a substrate, 12 is a groove, 12' is a circle, 13 is an oxide film, and 14 is a PSG film.
Claims (1)
溝を形成してから該溝表面角部に円みを付与し、
次に、絶縁膜を形成し、次に、ガラス膜を形成し
てからそれを溶融することを複数回繰返しガラス
を前記溝に密実に充填する工程が含まれてなるこ
とを特徴とする半導体装置の製造方法。1. Forming a groove having substantially perpendicular side walls in a semiconductor substrate, and then rounding the groove surface corners,
A semiconductor device comprising the steps of: next forming an insulating film; then forming a glass film and melting it; repeating this process multiple times to densely fill the groove with glass; manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8682480A JPS5712533A (en) | 1980-06-26 | 1980-06-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8682480A JPS5712533A (en) | 1980-06-26 | 1980-06-26 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5712533A JPS5712533A (en) | 1982-01-22 |
JPS6235267B2 true JPS6235267B2 (en) | 1987-07-31 |
Family
ID=13897550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8682480A Granted JPS5712533A (en) | 1980-06-26 | 1980-06-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5712533A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102021213701A1 (en) | 2021-12-02 | 2023-06-07 | Robert Bosch Gesellschaft mit beschränkter Haftung | Control system and method for controlling the position of a mobile device using a control system |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5743438A (en) * | 1980-08-29 | 1982-03-11 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPS589333A (en) * | 1981-07-08 | 1983-01-19 | Hitachi Ltd | Semiconductor device |
US4506435A (en) * | 1981-07-27 | 1985-03-26 | International Business Machines Corporation | Method for forming recessed isolated regions |
US4544576A (en) * | 1981-07-27 | 1985-10-01 | International Business Machines Corporation | Deep dielectric isolation by fused glass |
JPS5955033A (en) * | 1982-09-22 | 1984-03-29 | Fujitsu Ltd | Formation of interelement isolating film |
JPS59106133A (en) * | 1982-12-09 | 1984-06-19 | Nec Corp | Integrated circuit device |
JPS59119848A (en) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS6043843A (en) * | 1983-08-19 | 1985-03-08 | Nec Corp | Semiconductor device having dielectric isolating region |
JPS60111436A (en) * | 1983-11-22 | 1985-06-17 | Toshiba Corp | Manufacture of semiconductor device |
JPS60170951A (en) * | 1984-02-16 | 1985-09-04 | Nec Corp | Element isolating method |
US4729815A (en) * | 1986-07-21 | 1988-03-08 | Motorola, Inc. | Multiple step trench etching process |
JP2554635B2 (en) * | 1986-09-30 | 1996-11-13 | 株式会社東芝 | Method for manufacturing semiconductor device |
JPS6392045A (en) * | 1986-10-06 | 1988-04-22 | Toshiba Corp | Manufacture of semiconductor device |
JP2635607B2 (en) * | 1987-08-28 | 1997-07-30 | 株式会社東芝 | Method for manufacturing semiconductor device |
US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
JP2667552B2 (en) * | 1990-05-28 | 1997-10-27 | 株式会社東芝 | Method for manufacturing semiconductor device |
KR960006714B1 (en) * | 1990-05-28 | 1996-05-22 | 가부시끼가이샤 도시바 | Semiconductor device fabrication process |
US6077786A (en) * | 1997-05-08 | 2000-06-20 | International Business Machines Corporation | Methods and apparatus for filling high aspect ratio structures with silicate glass |
KR100392894B1 (en) * | 2000-12-27 | 2003-07-28 | 동부전자 주식회사 | Method for forming trench of semiconductor element |
-
1980
- 1980-06-26 JP JP8682480A patent/JPS5712533A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102021213701A1 (en) | 2021-12-02 | 2023-06-07 | Robert Bosch Gesellschaft mit beschränkter Haftung | Control system and method for controlling the position of a mobile device using a control system |
WO2023099369A1 (en) | 2021-12-02 | 2023-06-08 | Robert Bosch Gmbh | Control system and method for controlling the position of a mobile terminal by means of a control system |
Also Published As
Publication number | Publication date |
---|---|
JPS5712533A (en) | 1982-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6235267B2 (en) | ||
JPS63502313A (en) | How to form isolation regions on a semiconductor substrate | |
JPH0210575B2 (en) | ||
JPH02156552A (en) | Semiconductor device and manufacture thereof | |
JPH10335444A (en) | Manufacture of semiconductor device | |
US5371036A (en) | Locos technology with narrow silicon trench | |
JPS6020530A (en) | Forming method of element isolation region | |
JPH11260903A (en) | Method for forming non-cavity trench isolation | |
JPH07135247A (en) | Manufacture of semiconductor device | |
JPS5963739A (en) | Method for insulation and isolation of semiconductor device | |
JPH098118A (en) | Manufacture of semiconductor device | |
JPH05315442A (en) | Manufacture of semiconductor device | |
JP2786259B2 (en) | Method for manufacturing semiconductor device | |
JPS6058636A (en) | Forming of dielectric isolation region | |
JPS60161632A (en) | Semiconductor device and manufacture thereof | |
JPH01129439A (en) | Manufacture of semiconductor device | |
JP2671359B2 (en) | Method for manufacturing semiconductor device | |
JPH0310231B2 (en) | ||
JPS5815247A (en) | Manufacture of semiconductor device | |
JPH0521592A (en) | Manufacture of semiconductor device and semiconductor device | |
JPH0478013B2 (en) | ||
JPH04273462A (en) | Manufacture of semiconductor device | |
JPS59232443A (en) | Manufacture of semiconductor device | |
JPS5929439A (en) | Insulating isolation method for semiconductor device | |
JP2679626B2 (en) | Film formation method |