JP2635607B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a method for manufacturing a semiconductor device, for example, providing an insulator on a substrate surface such as a single crystal or polycrystalline silicon having a groove. A method of forming a capacitor or the like of a MOS type memory cell, digging a groove in a single crystal silicon substrate, forming an element isolation region in this groove, or forming a multi-layered wiring. The present invention relates to a method for manufacturing a semiconductor device including an etching step for rounding a corner generated in a step portion or the like of a semiconductor device.

(Related Art) In recent years, in a semiconductor device represented by a MOS dynamic memory (dRAM) or the like, miniaturization and high integration of elements have been promoted in accordance with the proportional reduction side. MOS, a component of dRAM
The capacitor is no exception, and the gate oxide film thickness t _OX and the area S have been reduced. Assuming that the scaling factor is α, the gate oxide film thickness is t _OX / α and the area is S / α ² .
The capacitance C of a MOS capacitor is expressed as follows:
_Since it is expressed as _OX , the capacity C ′ after proportional reduction is C ′ = C /
When it becomes α and becomes smaller to 1 / α, the soft error due to the flying alpha ray becomes smaller. In this way, the capacitance of the MOS capacitor is likely to occur, a soft error due to a bit line jump is likely to occur, and the ratio to the capacitance of the bit line is reduced to reduce the sensing margin, thereby causing a malfunction. . Therefore, the area of general MOS capacitor instead S / alpha ^2, have been made possible stop General Domel to the reduction of S / alpha. However, the size has been reduced for each generation, and it has been approaching the limit to obtain highly reliable semiconductor devices such as dRAM.

The use of an insulating film having a large dielectric constant, such as a Ta ₂ O ₅ film, has been studied as a means for increasing the capacity of a MOS capacitor, but it has not yet been put to practical use. Also, 10nm
The application of the following extremely thin and highly reliable silicon oxide film is being studied, but this also requires practical use because it requires extremely high-purity pure and chemicals, and also requires a clean room with high cleanliness. Not reached.

Therefore, recently, as a method of increasing the capacitance of a MOS capacitor, a so-called trench capacitor technique has been studied in which a trench is dug in the surface of a semiconductor substrate to substantially increase the capacitor area without increasing the occupied area. However, such grooves are formed by reactive ion etching (RI
The following problem arises when vertical side pieces are formed by anisotropic etching such as E). That is, the corner (corner) at the top or bottom of such a groove (recess) has a very small radius of curvature, and when the gate film is formed by thermal oxidation, the oxide film thickness is smaller at this corner than at the flat portion. Become. This phenomenon is explained as follows. When silicon is oxidized, the volume of the formed oxide film is about 2.3 times that of the original silicon. For this reason, it is considered that as oxidation proceeds, a compressive stress acts on the oxide film side at the interface between silicon and the silicon oxide film, and as a result of the concentration of stress described above, oxidation is suppressed.

If the oxide film thickness at the bottom or upper corner of the groove is thinner than that at the flat portion, the dielectric breakdown voltage in this portion decreases, and a large leak current flows in a low electric field. If the gate oxide film thickness is increased to keep the leakage current at the working voltage sufficiently small, it will be too thick in the flat part,
The effect of increasing the capacity by digging the groove to increase the area is offset.

Another method to increase the capacity of a MOS capacitor is to stack electrodes such as polycrystalline silicon on other elements or element isolation regions, oxidize the surface, and form another electrode. Stacked capacitor technology as a capacitor is being studied. However, the electrodes made of polycrystalline silicon or the like also have sharp corners at the upper portions of the electrodes due to processing such as RIE. If the surface of the polycrystalline silicon is oxidized while the corners are left as it is, the oxide film becomes thinner at the corners as in the trenches of single crystal silicon.
There is a problem that the withstand voltage of this portion is reduced.

In addition, it is difficult to perform subsequent steps such as losing flatness of a film covering the groove or the step due to a corner of the groove or the step formed in the process of manufacturing the semiconductor device, or May affect their own characteristics.

(Problems to be Solved by the Invention) As described above, conventionally, the leakage current concentrates on the bottom or upper corner of the groove or the step formed when the step of the trench capacitor or the like is formed. There has been a problem that the dielectric breakdown voltage at the corners is low. In other words, when a groove or a step is formed in a semiconductor substrate or the like by anisotropic etching such as RIE, the radius of curvature of the corner at the bottom or upper part of the groove or the step becomes extremely small,
These steep corners are difficult points in manufacturing various devices.

The present invention has been made in view of the above circumstances, and its purpose is to form a trench or a groove which causes problems such as generation of a leak current and a decrease in dielectric strength when forming a semiconductor element such as a trench capacitor or a stud capacitor. It is an object of the present invention to round the corners of the step to solve the above problem and improve the reliability of the device.

[Configuration of the invention]

(Means for Solving the Problems) The present invention In order to solve the above problems, the present invention provides:
Etching gas such that the ratio of oxygen to fluorine is excessive in the corners of grooves and steps formed by etching a silicon substrate or thin film of single crystal or polycrystal, or a thin film of metal or metal silicide. By acting, the corners are rounded to suppress a problem such as a decrease in withstand voltage that occurs when forming a semiconductor element such as a trench capacitor or a DRAM formed through the above steps, and to improve the reliability of the element. It is.

(Function) The gist of the present invention is to discharge a substrate such as single crystal silicon or a thin film such as polycrystalline silicon to round a sharp corner generated in a groove or a step formed by anisotropic etching such as RIE. By exposing it to an atmosphere containing fluorine and other radicals activated by the method and an excess of oxygen gas, and forming silicon oxyfluoride on the surface of the substrate or the like on which the grooves and steps are formed, while thinning the surface. It is to remove by etching.

That is, under conditions where the number of oxygen atoms is larger than the number of fluorine atoms in the etching gas, formation of the oxyfluoride film and etching compete on the silicon surface. Therefore, the etching speed is
The rate is controlled by the supply of fluorine radicals arriving by diffusing in the silicon oxyfluoride, the solid angle is large, the protruding part with a large supply is etched faster, and conversely, the etching rate of the concave part is slowed down, The part is rounded.

When a capacitor is manufactured by forming an insulating film such as a thin gate oxide film on the surface of a groove of a Si substrate or a polycrystalline silicon film having rounded corners as described above, the thickness of the insulating film is generally reduced. It becomes uniform, the electric field concentration which has conventionally occurred at the corners of the groove is alleviated, and the withstand voltage of the insulating film is improved.

At the same time, since the surface of the Si substrate or the polycrystalline silicon film is smoothed, the density of surface states is reduced, a pn junction having a small reverse leakage current can be formed on the side wall, and element isolation becomes easy.

Further, since the wiring of polysi, molybdenum silicide, tungsten, or the like can be processed into a tapered shape, the manufacture of an element having a multilayer wiring structure is facilitated.

(Embodiment) Before describing an embodiment of a method of manufacturing a semiconductor device according to the present invention, a downflow type etching apparatus (hereinafter referred to as chemical dry etching) used in a dry etching step which is one of the main steps of the present invention. : CDE.). FIG. 1 is a schematic diagram of the CDE device. The main part of this device is a vacuum vessel (11), a sample table (12) for placing a sample (19) in this vessel, and gas inlets (15) and (16) for introducing two types of gases. , A quartz discharge tube for discharging the gas introduced (14)
And an exhaust port (13) for exhausting the introduced gas.
It is composed of By introducing a gas containing the elemental fluorine of CF ₄ from the gas inlet port (15) and oxygen (O ₂ ) gas from the gas inlet port (16) while controlling a predetermined flow rate, and performing vacuum evacuation from the exhaust port (13), Maintain a predetermined pressure. or,
The discharge tube (14) has a frequency of 2.45GH via a waveguide (17).
When a microwave of z is applied, an electrodeless discharge is generated inside. This discharge dissociates the CF ₄ gas to generate fluorine (F) radicals. The F radicals are transported together with the oxygen gas into the vacuum vessel (11), cause a chemical reaction with a predetermined material of the sample (19), and perform etching.

Next, it is an important key of the method of the present invention. The reaction between silicon and fluorine radicals and oxygen will be described. Figure 2 shows CF
₄ shows the relationship between the silicon etching rate when the oxygen flow rate is changed while the flow rate is set to 50 atm cm ² / min.
The solid line shows the result for single-crystal silicon, and the broken line shows the result for polycrystalline silicon doped with phosphorus. In both cases, adding oxygen will result in O ₂
The silicon etching rate increases up to a flow rate of about 100 cm ³ atm / min, and decreases when the O ₂ flow rate is further increased. The silicon etching reaction proceeds by the following chemical reaction.

Si + 4F → SiF ₄酸 素 Further, oxygen dissociates CF ₄ and reacts with generated radicals such as CF ₃ and CF ₂ to remove these radicals. Therefore, recombination of CF ₃ or CF ₂ with F atoms is prevented, and the etching rate is increased. Conversely, adding 100 cm ³ atm / ming excess oxygen to the flow rate of the CF ₄ will decrease the rate. The silicon surface was measured by Auger electron spectroscopy to clarify the cause.
It was discovered that a silicon oxide film containing 80% of fluorine was formed. FIG. 2 shows the formed film thickness of the silicon oxyfluoride film in addition to the etching rate. That is, in the presence of fluorine atoms, the following reaction occurs, and Si also reacts with oxygen to deposit a nonvolatile oxyfluoride film.

Under these conditions, in order to promote the etching of Si, it is necessary that fluorine atoms diffuse in the film and react with Si, and that SiF _{4 as a} product must be de-diffused and desorbed from the film. is there. Therefore, the etching is accelerated quickly because the solid angle receiving the supply of fluorine atoms is large in the corner of the groove or the step formed in the silicon substrate, the polycrystalline silicon film, or the like,
The corners are rounded. Conversely, since the concave portion has a low etching rate, the uneven surface is smoothed as a whole.

FIG. 3 is a cross-sectional view showing a process of rounding a corner of a groove formed by RIE using the apparatus shown in FIG. That is, as shown in FIG. 3A, first, a groove is formed in the substrate (32) by reactive ion etching (RIE) using the SiO ₂ film (31) formed in the shape of the silicon substrate (32) as a mask. Form. Next, the substrate having the groove thus formed is immersed in hydrofluoric acid and ammonium fluoride buffer to remove the periphery of the opening of the groove (33) of the SiO ₂ film (31) (FIG. 3 (b)). . Thereafter, the substrate was accommodated in a vacuum vessel (11) of the CDE apparatus shown in FIG. 1, and etching was performed. The etching conditions were a CF ₄ flow rate of 50 atm cm ³ / min and an O ₂ flow rate of 150 atm cm ³ / min, and the processing condition was 1 minute. As shown in FIG. 3 (c), the shape of the groove after the above treatment is as follows: the upper corner (34) and the lower corner (35) of the groove (33).
It was confirmed that both had a radius of curvature of about 500 mm. Furthermore, before the rounding of the corner of the groove, the groove (3
Although fine irregularities were observed on the side wall of 3), it was also confirmed that the side wall was smoothed by the rounding processing of the corners.

These effects correspond to the fact that in FIG. _{2, a} film shape which does not increase the flow rate of O _{2 to be} added starts to be generated.
That is, the effect of rounding was obtained when the ratio of oxygen atoms to fluorine atoms was 1 or more, and no effect was obtained when the ratio was less than 1.

Next, as shown in FIG. 3, after a groove is formed in the silicon substrate by RIE using the SiO ₂ film as a mask, if a natural oxide film remains on the surface in hydrofluoric acid, the apparatus shown in FIG. 1 is used. FIG. 4 shows a cross-sectional view when CDE processing is performed.

FIG. 4 (a) shows a cross-sectional shape of the substrate (41) processed by the apparatus shown in FIG. 1 immediately after forming the groove (43) by RIE. (42) is a SiO ₂ film. As a result, the corner at the bottom of the groove (43) was rounded to some extent, but the roughness of the side wall of the groove (43) was further worse than before the treatment.

Next, after the grooves are formed by RIE, the substrate (41) on which the grooves (43) are formed is immersed in diluted hydrofluoric acid before CDE treatment to remove a natural oxide film on the inner wall surface of the grooves (43). I did it. As a result, the bottom and side walls of the groove (43) had no roughness, as shown in FIG. 4 (b). That is, this treatment can prevent the occurrence of roughness due to the CDE itself, and can also prevent RIE. It became clear that the minute roughness that existed immediately was also reduced. On the other hand, it became clear that only the vicinity of the opening of the groove (43) close to the SiO ₂ mask (42) was hardly etched and remained.

The above results are attributable to the fact that the enzymatic velocity due to F radicals rapidly decreases with oxygen concentration. That is, since the oxygen gas is released from the SiO ₂ mask, the etching rate locally decreases. A natural oxide film having many irregularities is present on the groove surface immediately after the RIE, and the periphery of the thick portion of the natural oxide film is not etched at all, whereas the thin portion is etched and becomes rough.

Next, the relationship between the etching shape of the substrate in each case where an organic photoresist is used and the case where an SiO ₂ film is used as the material of the etching mask will be described with reference to FIG. FIGS. 5A and 5B show a silicon substrate (5
1) The substrate (51) is etched using the above organic photoresist (52) as a mask. FIGS. 5C and 5B show the case where SiO (53) is used as a mask. First, in the case of a resist mask, SiO ₂
The groove (54) in contact with the mask is also etched at the opening (55), unlike the case of using a microphone. In other words, when the mask is not removed as shown in FIG. 5 (a) and the CDE treatment is performed with oxygen and fluorine, the corner of the bottom of the groove (54) is rounded, but the upper part of the groove (54) is an opening. (55) does not round. When the mask (52) is retracted as shown in FIG. 5 (b), a scuff (56) occurs immediately below the mask (52). Therefore, in the case of a resist mask, it is necessary to completely remove the mask (52) in order to round the opening (55) above the groove (51). In this case, portions other than the trench of the trench are also etched. On the other hand, when the SiO ₂ mask (53) is used, when the CDE processing as described above is performed without removing the mask as shown in FIG.
It is difficult to etch the groove (54) opening (57) just below the
It protrudes compared to the other side wall surfaces. On the other hand, when the end of the opening of the mask (53) is retracted from the side wall surface of the groove (54) (FIG. 5 (d)), the upper corner (58) of the groove can also be rounded. When a CDE process using oxygen and fluorine is performed after the opening end of the mask is once retracted using a mask such as SiO ₂ containing oxygen as described above, the trench other than the trench is not etched and the trench ( The upper and lower corners of 54) can be rounded.

Embodiment 1 As a first embodiment of the present invention, a method for manufacturing a trench MOS capacitor will be described. FIG. 6 shows a sectional view of the manufacturing process. First, as shown in FIG.
0) After forming a thick oxide film (62) for device isolation on a silicon wafer (61) with a specific resistance of 10 Ωcm, a 1000 酸化 thick oxide film (63), a 1000 シ リ コ ン silicon nitride film (64), and a 5000 酸化 oxidation The film (65) is sequentially deposited and processed by RIE to form an etching mask for the silicon wafer (61).

Next, as shown in FIG. 6B, a groove (66) having a depth of, for example, 3 μm was formed in a self-aligned manner with the etching mask by RIE using a chlorine gas or the like as an etching gas. Thereafter, the wafer (61) was treated with an ammonium hydrofluoride buffer for removing the mask and removing the natural oxide film on the inner wall of the groove (66).

As a result, as shown in FIG. 6 (c), the mask (65) of the upper oxide film is removed and at the same time, the Si in contact with the Si wafer (61) is removed.
The O ₂ film (63) receded by about 1000 °.

Next, using the CDE apparatus as shown in FIG. 1, CF ₄ 50
atm cm ³ / min, and a microwave of 400 [W] in the conditions of introducing O ₂ into a reaction vessel of 150 atm cm ³ / min before and after the device is applied to the discharge tube, and treated for 1 min, FIG. 6 (d ), The upper and lower corners (67a) and (67b) of the groove (66) were rounded. Further, as shown in FIG. 6 (e), arsenic was diffused into the inner wall of the groove (66) to form an n-type diffusion layer (68) having a concentration of 5 × 10 ²⁰ cm ⁻³ and a depth of about 2000 °.

Next, after removing the nitride film (64) and the oxide film (63) of the mask, as shown in FIG. 6 (f), the inner wall of the groove is oxidized on the n-type layer (68) to a thickness of 150 .ANG. An oxide film (69) is formed. Thereafter, as shown in FIG. 6 (g), phosphorus-added polycrystalline silicon (610) serving as an electrode is placed on the n-type diffusion layer (68).
And the trench MOS capacitor was formed. In the trench capacitor formed as described above, since the upper and lower corners (67a) and (67b) of the trench have a large radius of curvature, the gate oxide film (69) formed on the corner has a thickness of: It is possible to prevent a problem that the thickness of the oxide film is not reduced as compared with the other oxide film (69), so that the leak current increases and the dielectric strength of the oxide film decreases. Therefore, according to this embodiment, a highly reliable trench MOS
A capacitor can be manufactured. If a semiconductor device such as a MOS type dRAM is formed using the MOS capacitor formed as described above, its characteristics and reliability can be improved.

When the inventors applied a voltage of 5 V to both ends of the insulating film (69) for a capacitor having a total area of 0.1 cm ² and a peripheral length of 50 mm, the capacitor formed by a conventional method without rounding the corners of the groove. In this case, a leakage current of 10 ⁻⁶ A was flowing, whereas the leakage current could be reduced to 10 ⁻⁹ or less in the trench capacitor formed as in this example.

Embodiment 2 Next, as a second embodiment of the present invention, an example of forming an isolation region between elements will be described.

FIG. 7A is a cross-sectional view of the step. First, as shown in FIG. 7 (a), a pattern using an SiO ₂ film as a mask (72) is formed on a p-type silicon wafer substrate (71) having a specific resistance of 10Ωcm, for example. Next, a groove (73) having a width of 1.0 μm and a depth of 0.5 μm is formed in the silicon wafer (71) by RIE. Next, the wafer is immersed in a hydrofluoric acid-ammonium fluoride buffer to remove the mask around the opening of the groove (73) as shown in FIG. 7 (c), and a part (74) of the surface of the silicon wafer (71) is removed. Was exposed. Furthermore, as shown in FIG.
50 atm · cm ³ / min of CF ₄ into the apparatus, the O ₂ was introduced under the conditions of 150 atm · cm ³ / minutes, and 1 minute 30 seconds etching. As a result, as shown in FIG. 7D, the upper and lower corners (75
a) and (75b) were rounded. Next, on the inside of the groove (73) and on the wall
^Two ions of B ⁺ etc. were implanted at an acceleration voltage of 30 KeV and a dose of 5 × 10 ⁻¹³ cm ⁻² to form a p-type inversion prevention layer (76). Here, the amount of B ⁺ implanted is relatively larger in the rounded corners (77) than in the other groove portions, so that element isolation can be performed efficiently (FIG. 7 (e)). Furthermore, an SiO ₂ film (7
By embedding 8) by a CVD method or the like, an element isolation region (79) can be formed (FIG. 7 (f)). In the actual semiconductor device, for example, as shown in FIG. 7 (g), an n ⁻ layer (710) is formed on the surface of the substrate (71) on both sides of the formed element isolation region (79). Oxide film (7
11), MOS with polycrystalline silicon electrode (712) formed
A capacitor (720), an n ^- layer (713), a gate oxide film (715) formed on a substrate (71), and a polycrystalline silicon gate electrode (714) formed thereon, Silicon gate electrode (714) on the surface of the substrate (71)
Then, on the surface of the substrate (71) on both sides thereof, a MOS FET (73) composed of an n ⁻ layer (713) serving as a source and a drain is formed.

In this embodiment, since the corner (77) of the opening above the groove of the element isolation region (79) is rounded as described above, B ⁺ ions can be efficiently implanted into this portion, and p-
Reverse leakage current to the region where the n-junction is formed can be reduced. In addition, since the corners (77) and the side walls are suppressed from being roughened by RIE, the portions are smoothed, so that the surface state density is reduced, and the generation efficiency of decimal carriers can be reduced.

From these results, when the present invention is applied to a dynamic memory, the retention characteristics of the capacitor are greatly improved.

Embodiment 3 Next, as a third embodiment of the present invention, an example of forming a stacked capacitor element will be described with reference to the drawings.

FIG. 8 is a cross-sectional view of the process. First, as shown in FIG. 8A, a p-type (100) silicon substrate (81)
A thick oxide film (82) for element isolation is formed thereon, a gate oxide film (87) is formed on a silicon substrate (8), and a gate silicon electrode (83) is further provided thereon. 8
M with two n ^- layers (84) formed on the substrate surface on both sides of 3)
An element such as an OS FET is formed in advance. Further, after depositing an insulating film (88) on the entire surface, a contact hole connected to the n ^- layer is formed, and a phosphorous-doped polycrystalline silicon thin film (89) having a thickness of, for example, 4000 Å is formed on the n ^- layer and the insulating film (88). )
Deposit on top.

Next, as shown in FIG. 8 (b), when this phosphorus-doped polycrystalline silicon film (89) is etched by RIE, the etched polycrystalline silicon (89) has sharp edges (810). Have. Although not shown, a polycrystalline silicon film (a large number of grain boundaries existed on the surface of 89, and unevenness was generated.

Next, as shown in FIG. 8 (c), the substrate was treated with a 1/20 hydrofluoric acid diluent for 20 seconds to remove a native oxide film on the surface of the polycrystalline silicon film (89). example and CF ₄ 50atm cm ³ / min in the same manner, with O ₂ 120atm cm ³ / min conditions
The CDE treatment was performed for 45 seconds, and the polycrystalline silicon film (89) of about 500 ° was etched. As a result, as shown in the figure, the etched corners (810) of the polycrystalline silicon film (89) were rounded, and the surface irregularities were smoothed. Also oxide film (88)
The etched portion (811) immediately above was difficult to be etched, so that the side wall had a good tapered shape.

Further, after oxidizing the surface of the phosphorus-doped polycrystalline silicon film (810) to form an oxide film (812) having a thickness of 100 mm, a phosphorus-doped polycrystalline silicon electrode (813) is further laminated thereon. Then, a MOS capacitor was manufactured.

The so-called stacked MOS capacitor manufactured in this manner has a rounded corner of the polycrystalline silicon processed by etching, as compared with a conventional case where the polycrystalline silicon film is not rounded, and the surface thereof has Therefore, the breakdown voltage of the oxide film is improved, and the leak current is significantly reduced.

Fourth Embodiment An example of forming a multilayer wiring as a fourth embodiment according to the present invention will be described with reference to FIG.

As a comparative example, FIGS. 9A to 9D are cross-sectional views of a conventional multi-layer wiring forming process. First, FIG. 9 (a)
After depositing an insulating film such as SiO ₂ (92) on a semiconductor substrate (91) on the entire surface as shown in, deposited phosphorus-doped polycrystalline silicon or molybdenum silicide, the wiring layer such as tungsten (93).

Next, as shown in FIG. 9B, the wiring layer (93) is subjected to RIE.
To form a desired pattern. Thereafter, as shown in FIG. 9C, an oxide film (94) is formed on the surface of the wiring layer (93) by, for example, oxidation.

At this time, the oxide film pressure at the lower corner (95) on the lower side of the wiring layer is weakened, and scuffing occurs. When the second wiring (96) is deposited so as to cover the wiring layer thus formed, the wiring layer (97) on the side wall portion of the wiring layer (93) becomes thin, and disconnection easily occurs. Also, the wiring layer (96) penetrating into the recessed portion (95) of the SiO ₂ film (94)
It is difficult to remove when etching in the RIE process, which causes leakage between wirings.

On the other hand, an embodiment in which a multilayer wiring is formed by the method of the present invention is shown in FIGS. In FIG. 9, the same parts are denoted by the same reference numerals. First, the semiconductor substrate (9
1) Forming the wiring layer (93) on the upper insulating film (92) is exactly the same as in FIG. Then, as shown in FIG. 10 (a), in the same manner as in the above-described embodiment, using the apparatus shown in FIG. 1 under the conditions of CF ₄ 50 atm cm ³ / min and O ₂ 120 atm cm ³ / min, 1
Then, the surface of the wiring layer made of polycrystalline silicon of about 800 ° was etched. As in the previous embodiment, almost no etching proceeds on the interface with the etched wiring layer (93) immediately above the underlying SiO ₂ film (92), and the upper corner of the wiring layer is as shown in the figure. The sidewall becomes a tapered wiring layer (93a). Next, even if an oxide film (94a) is formed on the surface of the wiring layer (93a) by oxidation or the like, no scuffing of the interface occurs. Furthermore, even if the second wiring layer (96a) is deposited on the second wiring layer (96a), the reduction in the thickness of the side wall-shaped second wiring layer (96a) of the wiring layer (93a) is greatly reduced. .

By using the embodiment method according to the present invention as described above, even if a multilayer wiring structure is formed, disconnection and short circuit hardly occur, so that the reliability of the semiconductor device can be greatly improved.

Further, in this embodiment, an example in which polycrystalline silicon is used as the wiring layer to be rounded is described. However, other metals such as molybdenum and tungsten which react with fluorine to generate a bright compound, or metal silicide It was experimentally confirmed that even when a wiring material such as that described above was used, the corner could be rounded by CDE in which oxygen was added to an abundance ratio of 1 or more with fluorine.

As described above, the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be appropriately modified and applied without departing from the gist thereof.

〔The invention's effect〕

According to the present invention, a single crystal, a polycrystalline silicon substrate or a thin film, or a metal, a groove formed by etching a metal silicide thin film, or the like, a corner of a stepped portion has an excessive oxygen to fluorine ratio. By the action of the etching gas as described above, the corners are rounded to suppress problems such as a decrease in absolute withstand voltage that occur in the formation of a semiconductor element such as a trench capacitor and a dRAM formed through the above-described steps, and to improve the reliability of the element. Can be improved. Subtle irregularities on the surface of the substrate to be processed or the film are smoothed, the surface state density is reduced, and the efficiency of minority carrier generation can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a CDE device used in the present invention, FIG.
FIG. 3 is a characteristic diagram for explaining the operation of the present invention, and FIG.
5 to 5 are explanatory views for explaining the present invention, FIG. 6 is a process sectional view for explaining a first embodiment according to the present invention, and FIGS. 7 to 10 are other embodiments. It is a figure for explaining. 11 ... Vacuum container, 12 ... Sample stand, 13 ... Exhaust port, 14 ... Discharge tube, 15 ... Gas inlet, 16 ... Gas inlet, 17 ... Waveguide, 18 ... Microwave Oscillator, 31, 42, 53 ... SiO ₂ mask, 32, 14, 51 ... Silicon substrate.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-219759 (JP, A) JP-A-56-103424 (JP, A) JP-A-59-172235 (JP, A)

Claims (15)

(57) [Claims] A step of processing, by anisotropic etching, a substrate to be processed mainly containing a metal or a semiconductor material, or a substrate to be processed on which a film mainly containing a metal or a semiconductor material is formed; Without exposing the treated substrate to plasma, a thin film is formed on the surface of the treated substrate or the film mainly containing the metal or semiconductor material with a gas containing at least fluorine and oxygen and having a ratio of oxygen atoms to fluorine atoms of 1 or more. A method for manufacturing a semiconductor device, wherein dry etching is performed while depositing. 2. The method according to claim 1, wherein a material that reacts with fluorine atoms to form a volatile compound is used as said metal or semiconductor material. 3. The method according to claim 1, wherein silicon, metal silicide, tungsten or molybdenum is used as said metal or semiconductor material. 4. A patent characterized in that the substrate or film to be processed containing a metal or semiconductor material as a main component has silicon as a main component, and a film containing silicon, fluorine and oxygen is deposited as the thin film. A method for manufacturing a semiconductor device according to claim 1. 5. The method according to claim 1, further comprising a step of removing a natural oxide film formed on the surface of the substrate to be processed or the film, between the step of processing by the anisotropic etching and the step of dry etching. 2. The method of manufacturing a semiconductor device according to claim 1, wherein: 6. The method according to claim 1, further comprising, prior to the step of performing the dry etching, removing a mask material used in the anisotropic etching step at least around a region to be processed by the anisotropic etching. 3. The method for manufacturing a semiconductor device according to claim 1, wherein 7. A patent wherein the dry etching is performed by using a material containing oxygen as a mask material for the anisotropic etching and removing only a mask material around a region processed by the anisotropic etching. A method for manufacturing a semiconductor device according to claim 1. 8. The method for manufacturing a semiconductor device according to claim 1, wherein an impurity is added to said substrate to be processed or said film to show n-type or p-type conductivity. 9. A groove is formed in the substrate by processing the substrate by the anisotropic etching, and an insulating film is formed on a surface of the groove after the dry etching step. 2. The method according to claim 1, wherein an electrode is formed in the groove formed on the surface. 10. A substrate is processed by the anisotropic etching to form a groove in the substrate, and after the dry etching step, an insulating film is embedded in the groove to form an element isolation region. 3. The method for manufacturing a semiconductor device according to claim 1, wherein 11. An electrode or wiring layer is formed by processing said film by said anisotropic etching, and said electrode or wiring layer is covered with an insulating film after said dry etching step. 2. The method for manufacturing a semiconductor device according to claim 1. 12. A metal or semiconductor material as a main component,
Substrate to be processed with fine irregularities formed on the surface, or a metal or semiconductor material as a main component, without exposing the gas to be processed having a film with fine irregularities on the surface to plasma, at least fluorine and oxygen Dry etching is performed while depositing a thin film on a surface of a substrate or a film containing the metal or semiconductor material as a main component by using a gas containing and having a ratio of oxygen atoms to fluorine atoms of 1 or more. A method for manufacturing a semiconductor device. 13. The method for manufacturing a semiconductor device according to claim 12, wherein a material which reacts with fluorine atoms to form a volatile compound is used as said metal or semiconductor material. 14. The method according to claim 12, wherein silicon or metal silicide, or tungsten or molybdenum is used as said metal or semiconductor material. 15. A substrate or film to be processed containing a metal or a semiconductor material as a main component, wherein silicon is a main component, and a film containing silicon, fluorine and oxygen is deposited as the thin film. 13. The method for manufacturing a semiconductor device according to claim 12.