JPS6235140B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention converts N-bit data into bits (dots).
This relates to a method of shifting units and writing them into the display RAM. In graphic displays, such as video game devices, it is necessary to move the image pattern dot by dot. However, in the system in which N-bit data is read from the pattern ROM and transferred to the display RAM in parallel, it is not possible to perform a bit-by-bit shift. SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a data writing method that allows N-bit data to be shifted bit by bit and written into a display RAM. The present invention shifts the data output from the pattern ROM, divides the data into two according to the amount of shift, and displays the front and rear parts twice.
This is characterized by writing to RAM. Although the present invention has been described with reference to an embodiment using a CRT as a display section, it can also be used in a panel-like display in which liquid crystals or light emitters are arranged in dots. Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the outline of the present device. A video game program is written in ROM1. If this ROM 1 is provided on a separate board, separated from other circuits, and made detachable using a connector or the like, it is possible to play a different game simply by replacing the ROM board. RAM2 is for temporarily storing data. CPU3 sequentially executes programs written in ROM1, processes data,
Controls data exchange with the CRU decoding unit 4. One frame of the CRT (cathode ray tube) 5 consists of 256 scanning lines, and each scanning line includes 256 dots. Therefore, the display screen of the CRT 5 displays one frame with 256 dots in the X direction, which is the scanning line direction, and 256 dots in the Y direction, which is perpendicular to the scanning line direction, for a total of 65,536 dots. The data displayed on each of these dots is
It is written to RAM6. The display RAM 6 is provided with three sets of planes for color display. Each plane of display RAM 6 uses 8-bit dynamic RAM and has at least 8192 addresses. When considered on the display screen of a CRT 5, there are 32 addresses in the X direction and 256 addresses in the Y direction, and addressing is done for each divided block. In other words, it is displayed with 5 bits indicating the position in the X direction and 8 bits indicating the position in the Y direction.
The address of RAM6 is specified. The data written in the display RAM 6 is 1
Each byte is read out and sent to the parallel-to-serial conversion circuit 7. This parallel-to-serial conversion circuit 7 is composed of three sets of parallel latch circuits, each of which latches 1 byte (8 bits) of data transferred from the display RAM 6, and latches the 1 byte (8 bits) of data transferred from the display RAM 6. The signal A is sent out sequentially and converted into a serial signal. The signals output from each of the three parallel latch circuits are used for color conversion.
The 3-bit color code signal B input from the CRU decoder 4 is input to the PROM, and converted into a color video signal C of three colors: blue, green, and red. These three color video signals C
and the synchronizing signal D from the synchronizing circuit 9 are input to the CRT 5, and a color image is displayed on the display screen. In the pattern ROM 10, individual image patterns (for example, airplanes, cars, ping pong balls) to be displayed on the CRT are written in the order of transfer. This pattern ROM 10 uses an 8-bit EP-ROM, and each byte is addressed. In this pattern ROM 10, an address to be read is specified by an address signal E from a pattern ROM address counter 11. This address signal E is a 13-bit code signal. The read 8-bit data F is sent to the display designated by the display RAM address counter 13 via the shifter 12.
Written to RAM6 address. Since writing to the display RAM 6 is done in units of bytes (8 bits), the image pattern is written in units of bytes. Therefore, the shifter 1
2 is provided to change the position of data within a byte, and to write twice in the first half and second half according to the amount of shift, thereby making it possible to move the image pattern dot by dot. The pattern ROM address counter 11 receives a 13-bit pattern from the CRU decoder 4.
A ROM start address signal G, a 1-bit address fix signal H, and an initial value set signal I from the length counter 14 are input. This initial value set signal I is displayed as
Since the RAM 6 is written twice, it is used to reload the pattern ROM address counter 11 and display RAM address counter 13 with the latched initial values. Said pattern
The ROM start address signal G specifies the start address of the pattern ROM in which the image pattern to be written is recorded, is counted up by the clock signal (H4 clock signal) J from the length counter 14, and the data of the pattern ROM 10 is read out. . The pattern ROM address fix signal H stops the operation of the pattern ROM address counter 11 when it is "1", and performs a counting operation when it is "0". Therefore, when erasing the screen, specify the address of the blank pattern ROM 10 and set the pattern ROM address fix signal H to "1".
Keep it. The display RAM address counter 13 specifies the address of the display RAM 6 at the time of writing. This display
RAM address counter 13 is pattern ROM1
Displays the image pattern written in 0 RAM
6, specify the writing position (address). At the time of writing, the CRU decoding unit 4 displays an indication to specify the start address.
Since the RAM start address signal K is written twice, an initial value set signal I for setting the original address is also input. The display RAM start address signal K is supplied from CRU decoding units 4 to 16.
It is output in bits, of which 13 bits are used, and the remaining 3 bits are sent to shifter 12 and used for bit-by-bit movement. The length counter 14 specifies the size of each image pattern displayed on the CRT 5, and is composed of an X counter that counts the number of bytes and a Y counter that counts the number of scanning lines. This length counter 14 receives an 8-bit X length signal L from the CRU decoder 4,
An 8-bit Y length signal M is input. Also, a load signal N designating the start of writing is input from the CRU decoding unit 4. This length counter 14 outputs a BUSY signal O indicating completion of writing of a designated image pattern (for example, one car), and this signal O is displayed as the CRU decoding unit 4.
It is sent to RAM counter 15. The display RAM counter 15 receives the clock signal P of the timing module 8 and the plane select signal O from the CRU decoder 4, and generates a chip enable signal R, a write enable signal S, and a data set signal T. The chip enable signal R, write enable signal S, and data set signal T are as described in 10.
It is created by dividing 8MHz, 5.4MHz, H1, and H2 using a binary → octal decoder. The chip enable signal Q is
Although it is output to all three types of display RAM 6, in the write mode, it is output only to the display RAM 6 of the plane whose plane select is designated as "0". The write enable signal S is NANDed depending on the write mode and whether or not it is in the write state, and is output as. Note that the address of the display RAM 6 that can be accessed is ²¹³ , so when the ²¹⁴ bit of the display RAM address counter 13 becomes "1",
Stop write enable S to prohibit writing. The timing module 8 has a frequency of 10.8MHz,
5.4MHz, H1 (2.7MHz), H2, H4, H8, H16,
H32, H64, H128, V1, V2, V4, V8, V16,
Outputs V32, V64, and V128 clock signals.
These clock signals reduce the original 10.8MHz oscillation by
It is created by dividing the frequency by two. The display/write selector 16 switches between two modes, display and write, in response to a clock signal H4 from the timing module 8. In the display mode, the address of the display RAM 6 is specified by the address signal U specified by the timing module 8, and the data written therein is read out and displayed on the CRT 5. In the write mode, the display RAM 6 to be written is selected by the address signal V specified by the display RAM address counter 13.
Specify the address of and apply the pattern to this address.
Write data from ROM10. Therefore, during writing, the image pattern data is written to a desired address using the address signal V from the CRU decoding section 4, and during reading, all addresses of the display RAM 6 are written using the address signal U from the timing module 8. Addressing. With table-type video game machines, there are players on both sides of the table, so it is necessary to flip the TV screen. This uses the inversion signal W from the CRU decoding unit 4 to invert the address of the display RAM address counter 13, and for display, the reading in the parallel-to-direction conversion circuit 7 is reversed, that is, starting from the least significant bit. By reading it out, image inversion can be performed. FIG. 2 is a block diagram showing the main parts of the present invention. Data read from the pattern ROM 10 is input to eight shift registers 12a to 12h, and the data is shifted by selecting the input signal. The data shifted bit by bit is sent to three types of display RAM planes 6a, 6b, 6 selected by the chip enable signal R.
c. and display
The addresses of RAM planes 6a to 6c are displayed and
It is specified by the address signal V selected by the write selector 16. Note that the write enable signal S becomes "0" during writing, and becomes "1" during display. The display RAM start address signal K has 16 bits, of which 3 bits are used to move data bit by bit. That is, this 3-bit signal is sent to shifters 12a to 12h and ROM 20. The logic table for this ROM 20 is shown below.

[Table] This ROM 20 divides the data into the first half and the second half. That is, when the 3-bit signal of the display RAM start address signal K is "111", the data is written to the display RAM 6 as is without any bit-by-bit movement, and when it is "000", the movement is the largest and the display RAM
The first 1 bit of data is written to the start address 6, and the rest is written to an address shifted by 256. The output signal X of the 1/2 frequency divider 32, which will be described later, becomes "1" at the first writing, and becomes "0" at the second writing. The BUSY signal 0 becomes "1" during writing, and the H4 clock signal becomes "0" during writing. Therefore, when writing the last 3 bits of the 8 bits to an address shifted by 256 in the display RAM 6, the output terminals D1 to D5 of the ROM 20 are set to "1".
Since D6 to D8 become "0", the outputs of NOR gates 21a to 21e become "1" and the NOR
The outputs of the gates 21f to 21h become "0". Note that the NOR gates 21b to 21g are omitted in the drawing. As a result, among the display RAM planes selected by the chip enable signal R, for example, 6a, only the chips to which the NOR gates 21f to 21h are connected are initially enabled for writing. and,
At this time, the 8-bit data of the pattern ROM 10 is shifted by the shifters 12a to 12h as shown in FIG. 3 by selecting the fifth input terminal. That is, the output of the shifter 12a is "0", the shifter 12b is "0", the shifter 12c is "1", the shifter 12d is "0", the shifter 12e is "0", the shifter 12f is "0", and the shifter 12g is "1". ”, and the shifter 12h is set to “1”. Therefore, when writing for the first time, the shifter 12
The outputs of d to 12h are written to predetermined chips of the display RAM plane 6a. During the second write, the address of the display RAM plane 6a moves by "256" and at the same time the output signal X of the 1/2 frequency divider 32 becomes "0", so the NOR gate 21a
The output of shifters 12a to 12c becomes "0", and the outputs of shifters 12a to 12c are written only to the chips connected thereto. This allows the data stored in bytes to be shifted and displayed in bits.
Written to RAM6. The data written in each of the display RAM planes 6a-6c is read out during the read mode using the H4 clock signal, inputted to the parallel-to-serial conversion circuits 7a-7c, respectively, and then converted into a serial signal and output. This serial signal is the color conversion ROM2
2, where it is converted into a color video signal C. The code table for this color conversion ROM 22 is shown in Table 2.

[Table] Here, the colors displayed by color video signal B are as follows.

[Table] Since the color code signal B is latched by the CRU decoder 4, the hue is determined by the output of the display RAM 6, that is, which display RAM plane it is output from. When changing the hue of the screen, another color code signal B is output, so the same display RAM
Even if the output is from a plane, the hue changes.
Therefore, even if the images are the same, they will have different hues depending on the color code signal B. The color video signal output from the color conversion ROM 22 is latched in the register 23 and sent to the CRT 5 in synchronization with the dot signal. In table-type games, there are players on both sides of the table, so the screen needs to be flipped. Therefore, when writing, the data is written as is, and only when reading, the data is read in reverse to invert the screen. For this reason, an inversion circuit 24 using a plurality of exclusive OR gates is provided to invert the address during reading. Furthermore, parallel-to-direct conversion circuits 7a to 7
An inverted signal W is input to c, and the bits are sequentially read from the lower bits to the upper bits. As a result, dots are displayed at symmetrical positions shifted by 180 degrees on the screen. FIG. 4 is a block diagram of the length counter section. A Y length counter 30 that counts the number of scanning lines receives the Y length signal M from the CRU decoder 4 and subtracts it using the H4 clock signal M.
When the Y length counter 30 reaches zero, the initial value set signal (load signal) I delayed through the delay circuit 31 is input to the Y length counter 30, and the Y length signal M is set again. When the Y length counter 30 becomes zero, a subtraction signal is input to the 1/2 frequency divider 32. The output signal X of the 1/2 frequency divider 32 is input to a subtraction terminal of an X length counter 33 that counts the number of bytes. Therefore, when the Y length counter 30 becomes zero twice, the X length counter 33 is decremented by one. The X length counter 33 receives the X length signal L.
Enter. The load signal N which operates this X-length counter 33 is input to the flip-flop 34 and sets it to the set state. When the flip-flop 34 is set, a BUSY signal O indicating that writing is in progress is output from the output terminal Q. When the Y and X length counters 30 and 33 become zero and an image pattern, for example, one car, is written to a desired address in the display RAM 6,
Since the NAND gate 35 becomes "1", the flip-flop 34 is set. FIG. 5 is a block diagram of the display RAM address counter section. The display RAM start address signal K is input to the display RAM address counter 13 via the selector latch 40. This display RAM
Address counter 13 is decremented by the H4 clock signal. The full adder 41 receives the output signal X of the 1/2 frequency divider 32.
At the rising edge of , "256", which is the total number of scanning lines, is subtracted from the contents of the display RAM address counter 13. At times other than when signal X rises, the contents of the counter are input to selector latch 40. The display RAM address counter 13 receives the address of the selector latch 40 in response to the delayed load signal I from the delay circuit 31. In addition,
The selector latch 40 first passes the start address signal K from the CRU decoder 4, and then switches to pass the signal from the full adder 41. FIG. 6 is a block diagram of the pattern ROM address counter section. The pattern ROM start address signal G is input to the pattern ROM address counter 11 via the selector latch 50, and is subtracted by the H4 clock signal. Then, when the Y length is subtracted, the content becomes the gate circuit 51
The data is latched into the selector latch 50 via the ROM address counter 11 by the load signal I. The gate circuit 51 opens at the fall of the output signal X from the 1/2 frequency divider 32. On the other hand, the full adder 4
1 subtracts "256" at the rising edge of the output signal X. Therefore, display RAM address counter 13 and pattern ROM address counter 11
addresses a given address interval twice, but moves to the next address interval alternately. FIG. 7 shows a timing chart of the display RAM. When the H4 clock signal is "0", the data in the display RAM 6 specified by the clock signal of the timing module 8 is read out, and this 8-bit data is read out. data converted to serial signal
Sent to CRT5. FIG. 8 shows the word structure for writing. One word consists of 16 bits, these are
Stored in ROM1. At the time of writing, first the data combining the plane select Q shown in a and the pattern ROM start address G is output, then the data showing the display RAM start address K shown in b is output, and the address at which to start writing is determined. It is specified. Finally, display as shown in c.
The XY length indicating the size to be written to RAM6 is output. Figures 9 to 11 show the pattern ROM10.
Displays image pattern data stored in
This shows the case of writing to RAM6. 8th
As shown in the figure, when a pattern ROM start address signal G, display RAM start address signal K, and length signals L and M are applied,
The addresses of pattern ROM 10 and display RAM 6 are specified. Here, address N~ of pattern ROM10
A case will be described in which the 5 lines and 2 bytes of data stored up to N+9 are written with address M of the display RAM 6 as the start address and shifted by 5 bits. Note that the 5-line 2-byte data indicating the size of the image pattern is the length signal L, M.
specified by The 9th to 11th bits of the display RAM start address signal K are used as shift signals,
It is used for bit-by-bit movement at address M. This shift signal shifts the data at address N by 5 bits, and the upper 3 bits of data shown by solid lines are written into the lower 3 bits of address M in display RAM 6. When the display RAM address counter 13 and the pattern ROM address counter 11 count up in response to the H4 clock signal, the upper 3 bits of the N+1 data in the pattern ROM 10 are written to the lower 3 bits of address M+1 in the display RAM 6. And the address of pattern ROM10 is N+4
When it advances to this point, the Y length counter becomes zero. Since the gate circuit remains closed by the 1/2 frequency divider 32, the address latched in the selector latch is reloaded and the pattern ROM
Address counter 11 returns to address N. On the other hand, the display RAM address counter 13 is a 1/2 frequency divider 3
The full adder 41 is activated by the output from 2, subtracts the number of lines "256", and sets the address to "M-256". When writing for the second time, the Y length counter 30 is first reloaded. Next, since only the upper 5 bits of the display RAM 6 can be written, the data of the lower 5 bits of the address N indicated by the dotted line is written to the address "M-256" of the display RAM 6. Thereafter, writing is performed in the same manner up to the address "M-252" of the display RAM 6. By the second writing, pattern ROM10
When all data from N to N+4 is written,
The Y length counter 30 becomes zero again. This Y
When the length counter 30 becomes zero again, the 1/2 frequency divider 32 subtracts the value from the X length counter 33. At the same time, the gate circuit 51 is opened by the output signal
Data up to 9 is displayed M-256 to M- of RAM6
252, and M-512 to M-508. A large number of image patterns are written in the display RAM 6 as described above, and the written data is read out by addressing in the X direction and displayed on the CRT 5. Some of these image patterns are moved by handles, buttons, etc., and signals from these handles, buttons, etc. pass through the CRU decoding unit 4.
Input to CPU3. The present invention shifts the pattern ROM data, divides it into two parts, and displays it twice.
Since we write to RAM, we can perform bit-by-bit shifts.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a video game machine to which the present invention is applied, Figure 2 is a block diagram of the main parts, Figure 3 is an explanatory diagram showing data output from the pattern ROM and shifter, and Figure 4 is a length counter. 5 is a block diagram of the display RAM address counter section, FIG. 6 is a block diagram of the pattern ROM address counter section, FIG. 7 is a timing chart of the display RAM, and FIG. 8 is an explanation showing the word structure. 9 is an explanatory diagram showing data in the pattern ROM, FIG. 10 is an explanatory diagram showing the display RAM when writing is completed, and FIG. 11 is a timing chart showing data transfer between the pattern ROM and the display RAM.

Claims (1)

[Claims] 1 has M input terminals (an integer of 2 or more), and N
(an integer greater than or equal to 2) A display RAM whose address is specified by a bit address signal, and a pattern ROM that stores the data of M pixels lined up in the readout direction as M-bit pattern data are read out from the pattern ROM. When writing M bits of pattern data in parallel to the display RAM, the number of shift bits of the pattern data within M bits is m (m<
By combining the n-bit shift data representing M) and the N-bit address signal, (N+
n) Form the display RAM address signal with bits, and display this n-bit signal as pattern ROM.
The M-bit pattern data read from the pattern ROM is inputted to a shifter placed between the RAM and shifted in a ring shape by m bits, and the shifted data is decoded by a decoder. , of the M input terminals of the display RAM, the m-th to M-th are enabled for writing, and of the shifted M-bit pattern data output from the shifter, the m-bit and subsequent bits are written to the display RAM; During the second write, the address of the display RAM is shifted by one address in the read direction, and the output of the decoder is inverted, so that the address of the display RAM is shifted from the first to (m-1) of the M input terminals of the display RAM. A data writing method for a graphic display characterized in that the first bit to (m-1) bits of the output pattern data outputted from the shifter are written into the display RAM. 2. The data writing method in a graphic display according to claim 1, wherein said M is 8 and said n is 3.