JP2610200B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, particularly to an image processing apparatus used for a computer game machine.

[Prior Art] Conventionally, computer games have been enjoyed as entertainment for the general public. However, in recent years, computer game machines have become more sophisticated and complex in terms of both software and hardware in order to meet demands of consumers. .

In particular, computer games use color CRTs (eg,
In most cases, a user participates in a game while watching a color television screen), and how to make the game screen fun is an important theme for computer game machine developers.

For this purpose, research has been conducted on image processing apparatuses used in computer game machines.

In image processing of a computer game, a fade-in / out that changes the color and brightness of the entire screen may be performed.

To realize this fade-in / out, it is necessary to rewrite a color RAM (image data storage memory) storing image data of the game screen by a program. To do so, the CPU (microcomputer)
It is necessary to directly rewrite the data of the designated screen or the designated character stored in the color RAM, and to add or subtract the offset value.

In recent years, with the increase in the number of screens and characters in games,
The number of colors used for the game screen has also increased, depending on the program.
The number of rewrites of the CPU color RAM is one per rewrite
There have been cases where the number has exceeded 8000.

[Problem to be Solved by the Invention] In this case, the time occupied by the CPU for rewriting the color RAM for performing the fade-in / out cannot be ignored. From the perspective of the CPU, no other jobs can be performed while the fade-in / out processing is being performed, and from the perspective of the user, the time required for the fade-in / out becomes too long. was there.

Therefore, recently, in a computer game machine having an image processing apparatus using a color RAM, fade-in / out for changing a color tone and luminance has hardly been performed.

Further, in the conventional image processing apparatus, there is also a problem that the fade-in / out cannot be independently performed on the sprite surface or each background.

An object of the present invention is to provide a fade-in / out
It is an object of the present invention to provide an image processing apparatus that can complete processing in a short time without imposing a burden on U and can perform fade-in / out not only on the entire screen but also on a sprite surface or an individual background.

[Means for Solving the Problems] The object of the present invention is to provide a color RAM in which image data including color information is stored, and a digital RAM for converting image data read from the color RAM into a digital-to-analog signal and outputting it to an image display unit. An image processing apparatus having an analog converter, comprising: an offset register that inputs and holds an offset value; and an adder that receives the offset value of the offset register and the image data of the color RAM as they are, An image processing apparatus is characterized in that an image is changed without rewriting image data in the color RAM by adding the offset value to image data.

[Action] According to the present invention, when performing fade-in / out, the CP
Processing can be completed in a short time without putting a burden on U, and fade-in / out can be performed not only on the entire screen but also on the sprite surface and individual backgrounds.

Embodiment An image processing apparatus according to an embodiment of the present invention will be described with reference to FIG.

FIG. 1A is a block diagram of an image processing apparatus according to one embodiment of the present invention, and FIG. 1B is a block diagram of a color offset unit according to one embodiment of the present invention.

A CPU address for designating a data write address of the color RAM 22 and an image code for reading data from the color RAM 22 are input to the selector 20.

When the address of the color RAM 22 is specified from the CPU address by the selector 20, CPU data having image data is input to the color RAM 22. In the color RAM 22, image data for specifying the color of the sprite surface of the game and each background is written. By storing a large number of image data in the color RAM 22, a screen with a large number of colors can be created.

The image code of the color RAM 22 includes R (red), G
Information on the three primary colors of (green) and B (blue) light is stored as image data. An image code is sent from the CPU to the selector 2.
When input to 0, image data corresponding to the image code in the color RAM 22 is output to the CPU data bus. The output of the image data is R, G, and B as 5-bit information for each of R, G, and B.
It is input to the G and B color offset units 1.

On the other hand, offset data composed of 6 bits (sign + 5 bits) from the CPU is input to the offset register 4 in each color offset unit 1 and held as CPU data. The output of the offset register 4 is input to the adder 6.

The control signals 1 and 2 are input to the control logic 2 in each color offset unit 1. The control signals 1 and 2 include various video signals, the value of the control register of the CPU, and bits for determining the priority of the sprite surface and the like. By these control signals, the control logic 2 causes the image (full screen, sprite,
Background, etc.), and determine whether to output the offset value held by the offset register 4 to the adder 6.

Image data from the color RAM 22 input to the color offset unit 1 for each of RGB is input to the adder 6.

In the adder 6, the 5-bit image data from the color RAM 22 and the signed 5-bit offset value of the offset register 4 are added.

Since the image data is 5 bits, 0 to 31
It can take one of 32 levels of brightness. When the image data is 0, the luminance is 0. Therefore, when all the R, G, and B image data are 0, the image is black. By adding an offset value to this image data, without rewriting the data in the color RAM 22,
The brightness of the image can be changed.

For example, in the case of the R color offset unit 1, if a certain image data value is 7 (00111) and the offset value is 16 (10000), the operation result is 23 (10111), and the red luminance is increased. Become. By control logic 2,
When the offset value of the offset register 4 is not output to the adder 6, the value of the image data naturally does not change.

The result of the operation of the adder 6 is input to the overflow processing unit 8, and the overflow processing is performed. In the case of overflow, it is forcibly set to 31 (11111), and in the case of underflow, it is forcibly set to 0 (00000).

The output of the overflow processing unit 8 of each color offset unit is
Each is input to a 16-bit DAC (digital-to-analog converter) 24 as a 5-bit digital RGB signal. D
As for the input of AC24, 15 bits are allocated to the RGB signal, and the remaining 1 bit is input to SHADE. These digital RGB
The signal is converted to an analog RGB signal by the DAC 24, and the CRT 26
Is input to the image signal input terminal.

As described above, the image processing apparatus according to the present embodiment includes the RGB signal R, G, and B signals at the final stage of the image data digital processing unit.
An independent offset value corresponding to each is provided, and the offset value can be added or subtracted only from necessary image data.

Accordingly, hardware performs a series of addition and subtraction processing of the image data and the offset value, so that CPU processing can be reduced, and special effects such as fade-in / out can be easily obtained.

[Effects of the Invention] As described above, according to the present invention, when performing fade-in / out, processing can be completed in a short time without burdening the CPU, and not only the entire screen but also the sprite surface and individual backgrounds Thus, an image processing apparatus capable of fading in / out can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an image processing apparatus according to one embodiment of the present invention. In the figure, 1 ... color offset section 2 ... control logic 4 ... offset register 6 ... adder 8 ... digit overflow processing section 20 ... selector 22 ... color RAM 24 ... DAC 26 ... CRT

Claims (2)

(57) [Claims] 1. An image processing apparatus comprising: a color RAM in which image data including color information is stored; and a digital-to-analog converter for converting the image data read from the color RAM into a digital-to-analog signal and outputting it to an image display unit. An offset register that inputs and holds an offset value; and an adder that receives the offset value of the offset register and the image data of the color RAM as they are, and adds the offset value to the image data. An image processing device that changes an image without rewriting image data in the color RAM. 2. An image processing apparatus according to claim 1, wherein an addition result output from said adder is input, and when an overflow occurs, a maximum value is forcibly output, and when an underflow occurs, a minimum value is forcibly output. An image processing apparatus, comprising: a digit overflow processing unit that outputs an image.