KR100273786B1 - Image processing apparatus - Google Patents

Abstract

The present invention discloses a novel image processing apparatus that simply performs complex image processing on a plurality of input video data. For example, multi-stage data mixing, or multi translucent processing.

In the image processing apparatus of the present invention, a plurality of video data are processed by a predetermined time division operation in accordance with priority and superimposed on others. Based on the transparency information contained in the input video data, a transparency process is also performed. The image processing apparatus includes time selectors 65 and 72 for selecting input video data, priority chroma key control circuit 96 for executing the data selectors according to a predetermined priority, and output data of the data selector. A process register 75 for determining a coefficient used for the calculation by the specific image process calculating element with a specific image for executing a predetermined operation in relation to the output data of the data latch 74; And a pixel image data latch 76 or the like for holding the output data of the specific image process calculation element 75 last.

Description

Image processing device

1 is a perspective view showing a video game machine including an image processing apparatus embodying the present invention;

2 is a block diagram showing the internal configuration of a video game machine,

3 is a block diagram showing the internal structure of a video encoder unit constituting the image processing apparatus of the embodiment of the present invention;

4 is a block diagram showing the internal configuration of the interface of the video encoder unit,

5 is a timing chart showing input timing of video data;

6 is an explanatory diagram showing the configuration of a pallet address;

7 is an explanatory diagram illustrating the configuration of data in a color palette;

8 is a block diagram showing a video editing device 50b;

9 is a timing chart showing the operation of the video editing element,

10 is an explanatory diagram showing a conventional overlapping process, and

11 is a block diagram showing the structure of a conventional image processing apparatus.

<Explanation of symbols for main parts of drawing>

50a: interface element 50b: video editing element

50c: DAC element 50d: control element

62: VDP unit I / F 63: Video signal control unit I / F

64: video data release unit I / F 86: synchronization signal generating circuit

73: third data selector 74: time division data latch

75: specific image process calculation element 76: pixel image data latch

101: first data buffer 102: first signal regulator

103: second signal regulator 104: first selector

105: second data buffer 106: first process coordinator

107: second process regulator 108: second selector

109: third data buffer 110: first control buffer

111: first selector control element 112: second control buffer

113: second selector control element 114: third control buffer

130: count register 140: fixed color register

250: first external unit 260: second external unit

TECHNICAL FIELD The present invention relates to an image processing apparatus and a method thereof, and more particularly, to an image processing technique for processing a plurality of input image data.

The configuration of the present invention is applicable to various devices and units for processing a plurality of image data at the same time, such as a video game machine.

In an image processing apparatus such as a video game machine, a plurality of image data are overlapped on one another and displayed on the screen. Such processing is generally known to prioritize a plurality of image data in advance or to specify a transparent region in the image data. The preferred sequence of image data represents the relative position of the image data on a screen or other display device. Conventional superposing processes have been described on the basis of an example showing an image comprising a background in which a plurality of image data are visible inside a train and through a train window. As shown in FIG. 10, one set of image data F shows an object such as a window frame in a train when another image data B shows a background viewed through a window.

The image data F showing inside the train is located in front of the image data representing the background on the display screen. The specific part of the image data F corresponding to the window pane PANE is transparent. In the process of superimposing two images F and B, the image data F having a high priority is selected while a portion of the image data B showing the background is selected, while the specific portion corresponding to the window pane is selected. Is selected. This creates an image with the background visible through the train window.

11 shows a conventional image processing apparatus that executes the above process. The conventional image processing apparatus includes first and second external units 250 and 260 for generating image data. The first external unit 250 is pixel-by-pixel and has priority information showing relative positions of the image data 290 and the image data 290 with respect to the image data 320 of the second external unit 260. 300 and first characteristic information 310 showing whether each pixel is transparent or blurred. The second external unit 260 transmits the image data 320 and the second characteristic information 330 showing whether each pixel is transparent or opaque in pixels.

Priority sequence information and first and second characteristic information are input to the display image determination circuit 280 to determine which image data is selected for each pixel. The selector 270 then selects the image data based on the result of the determination and outputs the image data to form an actual video image.

Conventional image processing apparatuses are only used to superimpose two images, and it is not possible to superimpose three or more image data without an auxiliary apparatus. Thus, a plurality of complex high-speed processing apparatuses are required to process three or more image data. This is a factor that makes the image processing apparatus expensive, bulky, and complicated. Changing the priority of the image data requires changing all signals from the plurality of processing units.

The conventional image processing apparatus cannot perform multiple semi-transparent superposition, for example, editing an image in which an object is seen through a transparent water tank. So-called conventional systems have not been able to perform complex image processing such as MULTI-STAGE DATA MIXING of some input image data that is often needed in video games.

Known image processing apparatuses, for example, those disclosed in Japanese Patent Laid-Open No. 62-264096, process only one type of image data, and apply other types of image data such as superposition of other types of image data. Could not.

It is an object of the present invention to provide a new image processing apparatus which simply handles complex conversion processes in connection with freely overlapping a plurality of image data on a plurality of input image data, for example, other data.

In the first image processing apparatus of the present invention, the input unit inputs image data in pixels, and the pixel processing unit divides the input time period corresponding to one pixel into a plurality of divisions, and the pixels in one division of the input time period. A predetermined process is executed in relation to the specific image data corresponding to the device input. The predetermined process includes other processing such as overlapping processing and filter processing, in which specific image data is superimposed on the processed image, stored in the divided processing data storage unit.

The division processing data storage unit latches specific image data processed by the pixel processing unit for a process defined in another division of the input time period divided by the pixel processing unit. More specifically, the input time period corresponding to one pixel is divided into n time segments (N is an integer). Image data processed in the K-th (K is an integer less than 1 but less than n) time segments are latched for a predetermined process in the L-th time segment (L is an integer greater than K and less than or equal to n). The auxiliary register allows the image data processed in the Kth time segment to be latched for a predetermined process in the K + 1th time segment as well as the K + 2th or later time segment.

At the end of the input time period corresponding to the pixel, the output unit outputs the contents of the divided processing data storage unit as image data of the processed pixel. Thus two or more image data are processed to produce one resultant image. This structure is applicable to both still and action pictures because the process already established at the input time period of the pixel.

According to the image processing method of the present invention, image data is input in each division of an input time period corresponding to one pixel, processed according to a predetermined process, and latched for processing already determined in another division of the input time period. do. At the end of the input time period corresponding to the pixel, the latched image data is output as processed pixel image data.

In the second image processing apparatus of the present invention, the signal input unit inputs a plurality of signals corresponding to an image, and the image confirmation signal output unit performs a first image signal or a predetermined conversion in which each input signal directly represents an image. It is determined whether or not including a second image signal representing the image through, and outputs a confirmation signal based on the determination. The confirmation signal may be predetermined for output based on each signal representing an image or an image shape signal included in a plurality of signals.

The image signal adjustment unit performs predetermined conversion on each input signal determined as the second image signal in accordance with the confirmation signal, and adjusts the plurality of signals in some form to allow the predetermined image processing. The image processing apparatus performs predetermined image processing on a plurality of signals representing color images.

The third image processing apparatus of the present invention can execute a time division process of the first image processing apparatus in association with a plurality of signals adjusted in a specific form by the second image processing apparatus.

These and other objects, advantages and features of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.

1 is a perspective view of a video game machine 20 having an image processing apparatus embodying the present invention, and FIG. 2 is a block diagram showing the internal configuration of the video game machine 20. As shown in FIG.

As shown in FIG. 1, the video game machine 20 includes a main unit 22 detachably mounted with a compact disc read only memory (CD-ROM) 21, and a pair of games connected to the main unit. Pads 24 and 26, a video signal cable 30 for outputting the video signal to the color television 28, and a speaker 34 for outputting audio sound. The main unit 22 has a cover 31 which is naturally openable and opened for setting the CD-ROM 21 to the CD-ROM drive 32 of the main unit. The cover 31 is a turntable of the CD-ROM drive 32 starts to rotate, and the microprocessor of the main unit 22 reads the game program and the necessary audio and video information stored in the CD-ROM to start the game. Closed continuously. The user can enjoy the game by operating the pads 24 and 26 provided with the switch 24a and the cursor stick 24b, respectively.

As clearly shown in the block diagram of FIG. 2, the main unit 22 is for reproducing and displaying the activity picture based on the data registered on the CD-ROM 21 and the data generated by the game machine 20. FIG. It includes several types of circuits. The video game machine 20 is a CD-ROM drive 32 connected to a SCSI-BUS, and a microprocessor unit 40 (hereinafter referred to as MPU) which is connected to a BUS to generally execute image processing and perform other related processing. And a main memory unit 41 (hereinafter referred to as M-RAM) directly connected to the MPU 40 and a ROM directly connected to the MPU 40 for storing a Basic Input Out System (BIOS) program. ROM) 42. The video game machine 20 further includes several types of units connected to the M-BUS of the MPU 40, which are a video signal control unit 45, a video data decompression unit 47, VDP unit 49 for outputting a specific video signal, video encoder unit 50 for editing the video signal and outputting the edited video signal, and audio data output unit 52 for outputting the audio signal And so on.

The video game machine 20 also has a memory (K-RAM) 55 connected to a local bus (K-BUS) 54 of the video signal control unit 45 and a local of the video data release unit 47. The normal video signal from the other memory (R-RAM) 57 connected to the bus, the video memory (V-RAM) 59 connected to the local bus of the VDP unit 49, and the video encoder unit 50 ( NTSC signal) and an NTSC converter 60 for converting the output signal to the color television 28 and outputting the NTSC signal.

The MPU 40 is a high speed data processing unit having an operation element 40a and a dynamic memory control element 40b for executing an operation logic operation including a floating point operation. The MPU 40 transfers data to and from the game pads 24 and 26 and the CD-ROM 21 according to a program of the M-RAM 41 using a BIOS program previously stored in the ROM 42. It receives and outputs, and controls a variety of units for displaying audio sound and activity photos for the progress of the game.

Each video signal control unit 45, video data release unit 47, video encoder unit 50, and audio data output unit 52 are composed of arithmetic and logic operation units. The configuration and operation of each unit will be briefly described.

Video signal control unit 45:

The video signal control unit 45 is connected to M-BUS and K-BUS, inputs data from the CD-ROM drive 32, and performs data output to each unit described later. That is, MPUI / F (MPU interface) 45a for receiving and outputting data from / to MPU 40 via M-BUS 43 and from / to CD-ROM drive 32 via SCSI-BUS. Controlling the output of video data received from a CD-ROM, the SCSI controller 45b for receiving and outputting data, the AFFINE transformation unit 45c for executing AFFINE transformation of video data input from a CD-ROM Graphics controller 45d, sound controller 45e for controlling the output of audio data, and the like. The video signal control unit 45 extracts video data and audio data from all input data from the CD-ROM, and temporarily stores the audio video data (AV data) in the K-RAM. Under the control of the MPU 40, the AV data stored in the K-RAM is passed through the video data release unit 47 and the audio data output unit 52 through the graphic controller 45d and the sound controller 45e at a predetermined timing. Is output to When the MPU 40 instructs the predetermined AFFINE modification of the video data, the AFFINE transformation unit 45c executes a predetermined affine transformation of the video data and performs linear transformation of the video data or correction of the image.

Video data release unit (47):

The video data release unit 47 inputs data from the video signal control unit 45 and outputs the signal processed data to the video encoder unit 50 so that the video signal control unit 45 and the video encoder unit ( 50) are connected to perform data input and output. The video data release unit 47 is connected to the Huffman decoding unit for Huffman decoding of input video data, and the Huffman decoding unit, so that the inverse separation cosine transform of the decoded Huffman decoded data is performed. An IDCT unit for executing Discrete Cosine Transform (IDCT), a run length unit 47c for executing run length release of input video data, and a release controller 47d for controlling 47a through 47c. It includes. The release unit 47 releases the compressed video data input from the video signal control unit 45 or the MPU 40 based on the appropriate algorithm.

VDP unit (49):

The VDP unit 49 is connected to the V-RAM 59 and the video encoder unit 50 described later to perform input / output of data. The VDP unit has two equivalent chips mounted thereon. The two chips produce background images and block-unit images, commonly referred to as sprites, both of which have specific patterns and colors. The sprite is not only a moving character used in a game or the like, but also a specific image for simple display of a specific block that is frequently created or deleted. A plurality of sprites corresponding to the block unit video signal is output simultaneously with the background image according to the control signal from the MPU 40. Sprite images containing the necessary characters are stored in the V-RAM 59 connected to the VDP unit 49. When the MPU 40 outputs a command “move this character from one place to another”, the VDP unit 49 analyzes the command and stores it in the V-RAM 59 along the movement path. Create or delete a sprite to perform the movement corresponding to that command.

Video encoder unit 50:

The video encoder unit 50 is connected between the VDP unit 49, the M-BUS 43, and the NTSC converter 60, inputs data through the interface element 50a, and receives the signal processed data. The digital-to-analog converter 50c to be described later is used to output to the NTSC converter 60. The unit 50 determines the color of each video data, the interface element 50a which receives video data from the video signal control unit 45, the video data release unit 47, and the VDP unit 49. A video editing element 50b for setting a priority table of a plurality of video data and a priority table for a plurality of video data according to the priority, and digital / analog for converting complex video data into an analog signal. A converter element (hereinafter DAC element) 50c and a control element 50d for controlling the video editing element 50b are included. Detailed description of each device will be described later. The video encoder unit 50 includes a set of video signals in the video signal control unit 45, a set of video signals in the video data release unit 47, and a background image and sprites in the VDT unit 49. Two sets of video signals are received and the images corresponding to these video signals are edited according to the priorities already established. The relationship between the two created images varies with different grades, where the high priority image (image on top of another) changes from transparent to opaque with respect to the low priority image (image on top of others).

Audio data output unit 52:

The audio data output unit 52 for outputting sound and music from the speaker 34 is connected to input data via the M-BUS and output data to the speaker 34 described later. That is, the unit 52 allows simultaneous generation of an ADPCM element 52a for executing sound composition by an adaptive differential pulse coding modulation (ADPCM) and a plurality of predetermined sound sources. A sound source generator (hereinafter referred to as PSG) and a mixer 50c for manipulating sound from a plurality of sound sources or synthesized sound by the ADPCM element 52a. The audio data output unit 52 operates one or a plurality of sound sources for manipulating sound based on data in the video signal control unit 40 or the MPU 40, or for outputting synthesized sound or music to the speaker 34. You can also play music using. Although one speaker 34 is installed in the main unit 22 to produce a mono sound, an external speaker, for example, a speaker of a color television, may be used to generate stereo sound.

The detailed description of the video encoder unit 50 embodying the image processing apparatus of the present invention will now be described with reference to FIGS. 3 and 5. In FIG. 3, the dark line represents the flow of YUV data, the dark dotted line represents the flow of palette data, the thin dotted line represents the flow of register information, the dotted line represents the flow of control signals, and the thin line represents the synchronous ( synchronous) video signal.

Each YUN data is a 24-bit signal consisting of 8-bit Y data, 8-bit U data, and 8-bit V data, where Y data is luminance information and U data is a color difference between blue and yellow. The information and the V data are color difference information of red and green. In the embodiment, YUV data is input from the video signal control unit 45 and the video data release unit 7. 8-bit Y data shows black at the value '00' and white at the 'FF'. In natural color display mode using 1677 million colors, all 8 bits of U data or V data are effective. On the other hand, in another display mode using 65,536 colors, the lower 4 bits are equivalent to zero, and only the higher 4 bits are effective. U data or V data, each representing a positive or negative value, respectively, is colorless at a value of '80' in natural color display mode and 65,536 color display mode.

Palette data displays video data generated as YUV data after executing a color palette. In the embodiment, palette data is input from the VDP unit 49, the video signal control unit 45, and the video data release unit 47. According to the palette data, the color of the represented video image is changed by specifying a different address in the color palette. Palette data as a whole represents 65,536 colors. In an embodiment, the color palette has a 512 address showing 512 execution colors drawn from 65,536 colors.

The register information defines the operation of the video editing device 50b and is output from the control device 50d to the video editing device 50b for processing in the video editing device 50b. The control element 50d includes a plurality of registers for storing data written or read by the MPU 40. The video editing element 50b executes various processes in accordance with the values written in the registers. The control signal controls the uptime of each device.

As shown in FIG. 3, the interface element 50a of the video encoder unit 50 includes a VDP unit interface 62 (hereinafter referred to as the first I / F) that receives two sets of video data from the VDP unit 49. As shown in FIG. 1) from the video signal control unit interface 63 (hereinafter referred to as the second I / F) and the video data release unit 47, which receive a set of video data from the video signal control unit 45. And a video data release unit interface 64 (hereinafter referred to as third I / F) for receiving video data. The internal configuration of the first to third interfaces 62, 63, and 64 will be described later.

The video editing device 50b includes various circuits described in the following:

A first data selector 65 for selecting a particular type of video signal to be sent to the color palette from signals from the first to third interfaces 62, 63 and 64; An adder 67 for adding an off-set value necessary for the output at the first data selector 65; A color palette 68 which receives the output from the adder 67 and outputs the corresponding YUV data in 16-bit format; A second data selector 72 for selecting one of the YUV data at each color palette 68, second interface 63, third interface 64, respectively; A third data selector 73 for selecting output data in the second data selector 72 or a specific image process calculation unit (to be described later); A time division data latch 74 for latching the output at the third data selector 73; A specific image process calculation unit 75 for executing a specific image superimposition operation (described later) for the data in the time division data latch 74 and the output data at the second data selector 72; A pixel image data latch 76 for dividing the output from the time division data latch into Y, U and V signals and holding the divided signal after completing the overlap operation for one pixel; A digital / analog converter (hereinafter D / A converter) for converting the output at the pixel image data latch 76 into an analog signal; A MOD setting element 84 for determining which output signal from the D / A converters 81 to 83 is a composite signal or a component signal; And a synchronization signal generation circuit 86 for generating a dot clock and a horizontal vertical synchronization signal in response to the system clock CLOCK and an external synchronization signal.

The synchronizing signal generation circuit 86 outputs a synchronizing signal to the time division data latch 74 and the MOD setting element 84 as well as the pixel image data latch 76 (not shown by lines).

The control element 50d includes an MPU interface for controlling data input and output like the MPU 40; System control logic (90) having a plurality of registers for storing data written by the MPU (40) and for outputting register information and control signals for controlling the entire video encoder unit (5); Priority chroma key control circuitry 96 for controlling the priority and chroma key information of the video data.

The priority chroma key control circuit 96 receives control signals from the first I / F 62, the second I / F 63, and the WP 3 I / F 64, and registers the register information to the system control logic. From 90. The control circuit 96 is configured to control the first data selector 65 and the third data selector based on the chroma key setting and the priority of the video data input via the first I / F to the third I / F 62 to 64. (73) and controls the operation of the time division data latch 74. Register information from the system control logic 90 is input to an adder 67 and a specific image process computing element 75. The register information input to the adder 67 determines the processing address off-set value of the color palette 68. The register information input to the specific image process calculation element 75 determines the extent of the image superposition process executed therein.

The first to third I / Fs 62, 63, and 64 of the interface element 50a have substantially the same functions and structures. 4 shows the internal structure of each I / F 62, 62 or 64 to adjust the difference of the video signal output to the outside. Each I / F 62, 63 or 64 receives three different video signals, 16.7 million color video data, 65,536 color video data and palette data generated by entrusting the color palette 68. This video signal is edited into an 8-bit parallel signal in time order and adjusted by the interface element 50a.

As shown in FIG. 4, each of the I / Fs 62, 63 or 64 is temporarily stored in the first data buffer 101 and the data buffer 101 which receives the externally output video data. First and second signal regulators 102 and 103 for executing other processes with respect to the existing data, and a first signal for selecting one output signal at the first signal regulator 102 or the second signal regulator 103. A selector 104. The first and second I / Fs perform different processes with respect to data stored in the second data buffer 105 and the second data buffer 105 for storing the output signal from the first selector 104. A process selector 106, a second selector 108 for selecting one output signal from the first process regulator 106 or one from the second process regulator 107, and a signal from the second selector 108 And a third data buffer 109 for storing the data. In addition, the I / F controls selection of the first selector 104 by referring to the first control buffer 110 and the data stored in the first control buffer 11 for receiving control data input together with the image data. The second selector 108 with reference to the first selector control element 111 for storing, the second control buffer 112 for storing control data for subsequent processes, and the data stored in the second control buffer 112. A second selector control element (113) for controlling selection of the &lt; RTI ID = 0.0 &gt;), &lt; / RTI &gt;

The first data buffer 101 continuously stores three types of different types of video data inputted by a predetermined time sequence. For example, since the bus used for input of video data in the VDP unit 49 is only applicable to 8-bit data, natural color video such as 16-bit video data of 655,536 colors or 24-bit video data of 1677 million colors. Data cannot be input to the video encoder unit 50 at one time. The first data buffer 101 receives the video data sent by the partition and stores the partition of the video data for subsequent processing.

The first and second signal conditioners 102 and 103 respectively adjust the alignment of such video data. 5 is a timing chart showing the input of various types of video data. Each video data has feature information formed as control data, which includes a 'plane number' indicating priority and a 'color number' indicating the number of colors used for display. In the case where 16.7 million colors are specified, the video data input into the interface element 50a includes 8-bit Y1 data, 8-bit Y2 data, 8-bit U data, and 8-bit V data. This shows the first dot of video data as 'Y1, U, V' and the second dot of video data as 'Y2, U, V'. The first signal conditioner 102 stores the input video data in the first data buffer 101 and adjusts the input video data to 24-bit YUV data by two bits. For example, the first signal conditioner 102 consists of a data selector and an 8-bit X 3 X 2 step register, where the data selector is defined by successively selecting the input video data and storing the necessary video data in each register. By chronological order, video data inputs are adjusted to complete 24-bit color digital data.

Video data of 65,536 colors includes 8-bit Y data, upper 4-bit U data, and lower 4-bit V data. The first signal conditioner 102 checks the video data of 65,536 colors according to the control data, converts the video data input by 8 bits into 8 bits of Y data, 8 bits of U data having a '0' value in the lower 4 bits, and Adjust to 24-bit color data including 8-bit V data having a value of '0' in the lower 4 bits.

The second signal conditioner 103 determines whether the palette data after all inactive data is a 256-color display or a 16-color display, as shown in FIG. 5, and in the former case unprocessed 8-bits. The palette data is output, and in the latter case, the 8-bit palette data is adjusted in consideration of the palette bank number.

The first and second process coordinators 106, 107 perform a particular process on the image, such as the preparation of video data indicating transparency, for example. The first process coordinator 106 checks YUV data, such as 65,536 colors or 1677 million colors, indicating transparency, and sets the Y data equal to '0'. In a similar manner, the second process regulator 107 checks the palette data indicative of the transparency and sets the palette data itself or the palette number P to zero.

The video data thus adjusted (digital color data or palette data) is output to the video editing device 50b. The palette data is input to the color palette via the first data selector 65 and the adder 67. The adder also receives address off-set values of color palette 68 as register information from system control logic 90. The address off-set value is multiplied by two and added to the palette data. As shown in Figure 6, adding the pallet data by doubling the address off-set value and shifting it one bit to the left results in a 9-bit color palette address. The size of the color palette 68 is defined as 9 bits (512 addresses) in the address dimension and 16 bits in the data dimension, as shown in FIG.

The color palette 68 consists of 8-bit Y data, 4-bit U data, and 4-bit V data, and allows for an 512 color of bits that are extracted from all 65,536 colors. The output of the data in the color palette contains three sets of 8-bit video data, which are 8-bit Y data, 8-bit U data with '0000' in the lower 4 bits, and separate and lower in U data. 8-bit V data with '0000' in 4 bits. All 16.77 million color video data, 65,536 color video data and palette data color are adjusted to three sets of 8-bit colors before being input to the second data selector 72. As mentioned above, U data and V data represent data with a positive or negative type in binary coded decimal notation, where '80' represents zero, respectively.

The operation of the specific image process calculation element 75, which is superimposed on the video data and coordinated with others, is explained according to the block diagram of FIG. Of the plurality of registers of the system control logic 90, the coefficient register 130 is for setting the degree of image overlap, and the fixed color register 140 assigns a specific color to the overlapping of a specific color on a lower ranked image plane or Further overlap in the previously superimposed image plane is confirmed. The video data in the video signal control unit 45, the video data release unit 47, and the VDP unit 49 may be YUV data or palette data. In the latter case, the palette data is converted into 24-bit YUV data (hereinafter referred to as digital video data) as described above. In the block diagram of FIG. 8, the first data selector 65 and the second data selector 72 (see FIG. 3) are shown as one data selector 65 + 72. Although video data in each unit includes control data indicating transparency information and the like, the flow of data determined by the MPU 40 is omitted in FIG.

In each unit, the video data moves in a period of 200 nS in the embodiment. The four types of input signals are transmitted simultaneously and synchronously with the dot clock DCT (see FIG. 5). Digital video data includes one bit of transparency information as control data. The data selector 65 + 72 is a 24-bit selector with four inputs and one output, which selects one of the input video data and the output 24-bit digital video data. The priority chroma key control circuit 96 counts the coefficients according to the priority determined by the MPU 40 at a period of every 50 nS in synchronization with the system clock SCK having a frequency four times the dot clock DCK. The select signal is output to the register 130 and the data selector 65 + 72.

The coefficient register 130 determines coefficients of a specific operation executed in the specific image process calculating element 75 (to be described later). In an embodiment, three effective coefficient registers 130 with register numbers 1 to 3 are used depending on the number of overlapping digital video data. Although not shown, there is one more effective count register with an additional register number zero that does not count. If register number 0 is selected in the effective coefficient register, it creates video data transparency. The priority chroma key control circuit 96 outputs a selection signal to the data selector 65 + 72 which is synchronous with the system clock SCK, and selects one of the coefficient register elements 130. If the transparency information is set corresponding to 1, the coefficient register with the register number 0 is selected, and the third data selector is transferred from the data selector 65 + 72 to the time division data latch 74, where it is output. Switched to allow output from the specific image process computing element 75.

The time division data latch 74 latches the output data from the third data selector 73 in accordance with the system clock SCK. As shown in FIG. 9, the time period for one pixel is divided into four equal time segments, which are the first to fourth time segments, and the time division data latch 74 has a third data selector (&quot; &quot; Latch the output from 73). The output from the time division data latch 74 is input to the pixel image data latch 76 as well as the specific image computing element 75. The pixel image data latch 76 above latches the output from the time division data latch 74 in accordance with the dot clock DCK. As shown in FIG. 9, the pixel image data latch 76 is based on the pixel data latch signal output from the system control logic 90 after the time division data latch 74 latches the output data in the fourth time segment. To latch the input signal. The output of pixel image data latch 76 is updated every hour period for one pixel.

The specific image process calculation element 75 performs a hardware operation for editing the output at the data selector 65 + 72 and the output at the time division data latch 74 by a predetermined operator. The specific image process calculator 75 mixes 24-bit color digital video data by the coefficient or ratio determined by the coefficient register 130. Basically, the specific image process calculating element 75 multiplies the two input data by each coefficient determined by the coefficient register, and determines the sum of the results. The output from a particular image process computing element can be displayed as follows;

c = m x a + n x b. … … … … … … … … … … … … … … … … … (One)

Where a is the name of the data selector 65 + 72, b is the latch data of the time division data latch 74, and m and n are the coefficients determined by the coefficient register 130, respectively.

Since the YUV data is processed in the actual operation, Equation (1) above can be represented again as follows for Y, U and V data;

Yc = my x Ya + n x Yb... … … … … … … … … … … … … … … … (2)

Uc = mu x (Ua-80h) + nu x (Ub-80h) + 80h... … … … … … … … (3)

Vc = mv x (Va-80h) + nv x (Yb-80h) + 80h... … … … … … … … (4)

Where a, b, and c are the same as a, b, c in Equation (1), and y, u, and v represent Y, U, and V data, respectively. Each coefficient my, mu, mv, ny, nu, or nv is determined by dividing the value (0-8) in the value of the effective coefficient register 130 by the value '8'.

In equations (3) and (4), 80h of binary coded decimal notation is subtracted from each U data and V data before being multiplied by the corresponding coefficient, and 80h is added after the operation. This is because the U data and the V data represent respective data with 80h having a positive or negative type equal to zero. The result of the calculation by the specific image process calculation element 75 is latched by the time division data latch 74 via the third data selector 73.

The operation of the video editing device 50b is described according to the block diagram of FIG. 8 and the timing chart of FIG. As a first step, MPU 40 sets priority for video data input from units 45, 47 and 49 in priority chroma key control circuit 96 via system control logic 90. For example, video data in the VDP unit 49, video data in the video data release unit 47, and video data in the video signal control unit 45 have priority in this order. The highest priority video data is placed on top of the other, and the lower rank video data is placed on top of the other. The priority set by the MPU 40 is maintained until a new priority is determined.

The image processing apparatus according to the present embodiment divides a time period corresponding to one pixel into a plurality of phases (e.g., first to fourth phases) that are larger than or equal to the number of video data, Process video data according to time division process. The cycle of the system clock SCK is determined by dividing the transfer rate of the input digital video data or the dot clock DCK by a value equal to or greater than the number of input video data. In the embodiment, the data transfer rate is equivalent to 200 nS, and the number of input video data is equal to 4 (two sets of video data are transferred from the VDP unit 49), so that the value 50 nS (= 200 nS / 4) is obtained. It is set in cycles of the system clock ASC. The priority chroma key control circuit 96 detects the timing of the first phase in accordance with the dot clock DCK and the system clock SCK, and causes the data selector 65 + 72 to find the lowest ranked video data. [Video Data from Video Signal Control Unit 45 in Embodiment]

The video data selected by the data selector 65 + 72 is immediately input to the specific image process computing element 75. The third data selector 73 selects the output at the data selector 64 + 72 instead of the output at the specific image process calculation element 75, and the time division data latch 74 is the lowest order without the above-described operation. By latching the video data with priority, at the time of the first phase, the number 0 effective coefficient register 130 is selected. In the embodiment, even if the third data selector 73 is switched along with the output from the coefficient register 130, the system control logic 90 outputs the operation suppression signal so that the specific image process calculation element 75 is activated. And therefore the output signal at data selector 65 + 72 is latched by time division data latch 74 directly through a particular image process computing element.

In any case, time division data latch 74 latches the lowest order digital video data in the first phase. In the second phase, the data selector 65 + 72 selects the second lower order digital video data, which is input to the specific image process computing element 75. The specific image process calculator 75 also receives the output from the time division data latch 74, which is the lowest order digital video data. The specific image process calculating element 75 successively executes the calculation of equation (4) in equation (2). Basically, after multiplying the Y, U and V data by their respective coefficients (an integer between 0 and 8), the computing element 75 divides the two data by 8 plus each other for all colors. [3-bit right Shift to]

As a result of the operation, the two digital video data may be 0/8: 8/8, 1/8: 7/8, 2/8: 6/8, ..., 7/8: 1/8, or They overlap each other with a mixing ratio of 8/8: 0/8. The MPU 40 assigns independent coefficients to all video data in the coefficient register 130. The priority chroma key control circuit 96 outputs a selection signal indicative of the selection of the video data, selects a coefficient corresponding to the selected video data to set the coefficients of the coefficient register 130, and selects the coefficients into a specific image. Output to process calculation element 75. The coefficient is an 8-bit value, the upper four bits represent the coefficient for digital video data a, and the lower four bits represent the same value for digital video data b. Integers selected from 9 to 0 are set in the upper 4 bits and the lower 4 bits, respectively.

Transparency processing is also performed during the operation. The specific image process calculation element 75 checks the transparency information contained in the control data. When the transparency information is set to 1, the specific image process calculation element 75 returns the digital video data previously outputted from the time division data latch 74 to the time division latch 74 without any operation, without any operation. Output through). At this moment, the digital video data output from the data selector 65 + 72 does not affect the output of the specific image calculating element 75, so that the output data remains completely transparent. Transparency processing may be realized by preventing the latch pulse from being output to the time division data latch 74. In such a case, the digital video data does not pass through the specific image calculating element 75 or the third data selector 73 to simplify the calculation and simplify the switching of the specific image processing calculating element.

The output of the specific image process calculation element 75 is latched in a cycle of 50 nS corresponding to the rising edge of the system clock SCK by the time division data latch 74. In the third or fourth phase, the digital video data having the corresponding priority proceeds in a similar manner. At the end of the fourth phase, the time division data latch 74 latches the last data latched again at the end of the next first phase by the pixel image data latch 76. The latch pulse of the pixel image data latch 76 is generated by delaying the dot clock DCK in one cycle of the system clock SCK in the display circuit (not shown).

If the time period corresponding to one pixel is divided into a plurality of phases larger than the number of video data, further processing proceeds, for example, colors stored in the fixed color register 140 overlap the resulting image of the previous overlapping process. May be One particular color may be superimposed on the lowest order video data by setting any color specified by the fixed color register 140 in the time division data latch 74 prior to the selection of the lowest order video data.

The processing of digital video data of one dot is thus completed. After the mixing and transparency processing described above, digital video data is output from the pixel image data latch 76 for subsequent processing such as a D / A converter. The configuration of this embodiment continuously and continuously advances the image data to realize a real time process of both still pictures or active pictures.

Although 8-bit Y, U and V digital video data has been advanced in the above embodiment, the same structure of an image processing apparatus of digital video data of three primary colors such as RGB may be applicable.

In the video game machine 20 of the embodiment, it is possible to freely overlap the video data stored in the CD-RAM 21 or generated by the VDP unit 49 in combination with another one or the other. Certain parts of the screen image will be able to display lighter or darker than other parts to give a special spot-light or shading effect. This provides excellent three dimensional effects for video game machines. Independent determination of the coefficients allows for smooth image switching by already known fade-out and fade-in techniques, which have a special effect on the execution of the scene.

The image processing apparatus installed in the video game machine 20 of this embodiment performs multi-stage data mixing, for example, a multi-transparent process in which mountains are seen through a train window viewed through an aquarium. In the system of the embodiment, since the coefficients can be changed for each video data by the coefficient register, the degree of transparency can be set in each window according to the required value.

Such image superposition process is realized by repeated execution of the specific image process calculation element 75. The basic design of the system, which includes a particular image process calculator 75, time division data latch 74, and pixel image data latch 76, is applicable to a large number of video data. One particular image process calculation element 75, which executes several operations for each dot, makes it possible to design the entire image processing apparatus compactly and effectively.

The image processing apparatus of this embodiment is applicable to superimposing not only 256 color, 16 color, 4 color palette data but also 16.7 million color or 65,536 color video data. Since the palette data is converted into 24-bit video data by executing the color palette 68 before the execution of the specific image process calculating element 75, the specific image processing calculating element 75 is the same as other 24-bit video data. The palette data can be processed in this way.

As many modifications, variations and variations are possible within the basic elements and scope of the invention, the above embodiments are illustrative only and are not to be construed as limiting in any sense, but the gist and scope of the invention are appended. It may be limited only by the claims.

Claims (18)

An image processing apparatus for receiving and processing a plurality of image data, the apparatus comprising: input means for sequentially inputting a plurality of image data for each pixel; Pixel processing means for dividing an input time period for inputting one pixel into a plurality of division periods and performing a predetermined process with respect to specific image data corresponding to pixel elements input in one of the division periods; Division processing data storage means for latching specific image data processed by the pixel processing means for the predetermined process in another division period of the input time period divided by the pixel processing means; And output means for outputting, at the end of the input time period, the contents of the divided processing data storage means as processed image data corresponding to the pixel; An image processing apparatus composed of. 2. The apparatus according to claim 1, wherein the apparatus further comprises selection means for selecting image data input from a plurality of external units through an input means, in accordance with division of an input time period by the pixel processing means. Processing unit. 2. The image processing according to claim 1, wherein said pixel processing means further comprises means for overlapping specific image data input from said input means, such as latched image data stored in said division processing data storage means. Device. The apparatus of claim 1, wherein the apparatus further comprises first parameterization means for determining a parameter required for image processing, the pixel processing means further comprising means for performing a process determined by the parameter. And an image processing apparatus. The image processing apparatus according to claim 4, wherein the first parameter determining means further comprises parameter setting means for setting the parameter by specifying a color component constituting a pixel. The image processing apparatus according to claim 4, wherein the first parameter determining means further comprises division parameter setting means for setting the parameter in each division period of an input time period. 4. The apparatus of claim 3, wherein the apparatus further comprises second parameter determining means for determining a parameter required to overlap two or more images with another; The said pixel processing means is further comprised by means for determining the mixing ratio for mixing the specific image data input from the said input means with the latched image stored in the division process data storage means according to the said parameter. . 8. An image processing apparatus according to claim 7, wherein said second parameter determining means further comprises parameter setting means for setting said parameter by specifying a color component constituting a pixel. 8. An image processing apparatus according to claim 7, wherein said second parameter determining means further comprises division parameter setting means for setting said parameter at each division period of an input time period. 8. The apparatus of claim 7, wherein the apparatus further comprises: transparency parameter determining means for determining whether a parameter determined by the parameter determining means indicates a transparency; Image processing further comprising transparency processing means for causing the division processing data storage means to output the contents stored therein when the transparency parameter determining means determines that the parametric transparency is displayed. Device. 3. An image processing apparatus according to claim 2, wherein said selection means selects image data in cycles equal to or less than a time segment determined by dividing an input time period for inputting pixels by a plurality of external units to some extent. In the method of receiving and processing a plurality of image data: (a) sequentially inputting a plurality of image data for each pixel; (b) dividing an input time period for inputting one pixel into a plurality of division periods; (c) execute a predetermined process for specific image data corresponding to pixel elements input in one division period of the input time period; (d) latching specific image data processed in step (c) for a predetermined process in another division period of the input time period; (e) outputting the latched image data as processed image data of the pixel at the end of the input time period; Image processing method consisting of a process. An apparatus for receiving a plurality of signals representing color images and executing a predetermined process for color images corresponding to the plurality of signals, the apparatus comprising: signal input means for inputting the plurality of signals; An image identification signal for determining whether each of the input signals consists of a first image signal directly displaying an image or a second image displaying an image only after a predetermined conversion, and outputting an identification signal based on the determination Output means; Image signal adjusting means for adjusting the plurality of signals in a specific form allowing the predetermined process by performing the predetermined conversion on each of the input signals determined as the second image signal by the image identification signal output means ; An image processing apparatus composed of. The image processing apparatus according to claim 13, wherein the predetermined process consists of overlapping a plurality of images. The image processing apparatus according to claim 13, wherein said predetermined conversion consists of a process of performing a color palette on output image data. The image processing apparatus according to claim 13, wherein said image identification signal output means comprises means for outputting a predetermined identification signal for each of a plurality of signals. The method of claim 13; The plurality of signals comprises an image signal corresponding to an image and an image shape signal indicating a shape of the image; And said image identification signal output means outputs said identification signal based on image shape signals contained in a plurality of signals. An apparatus for receiving a plurality of signals representing color images and executing a predetermined process for the color images corresponding to the plurality of signals, comprising: signal input means for inputting the plurality of signals into pixels; An image identification signal for determining whether each of the input signals consists of a first image signal directly displaying an image or a second image displaying an image only after a predetermined conversion, and outputting an identification signal based on the determination Output means; Image signal adjusting means for adjusting the plurality of signals in a specific form allowing the predetermined process by performing the predetermined conversion on each of the input signals determined as the second image signal by the image identification signal output means and; Pixel processing means for dividing an input time period for inputting one pixel into a plurality of division periods, and performing a predetermined process with respect to specific image data corresponding to pixel elements input in one of the division periods; Partition processing data storage means for latching a specific image processed by the pixel processing means for the predetermined process in another division period of the input time period; And output means for outputting the contents of the divided processing data storage means to the processed image data corresponding to the pixel at the end of the input time period; An image processing apparatus composed of.