JPS6234397A - Dynamic memory device - Google Patents

Abstract

PURPOSE:To improve the reliability of a device by providing capacity between the first and the second polysilicon, increasing the capacity between a cell plate and ground or power source by the capacity and stabilizing the potential of the cell plate. CONSTITUTION:An access MOS transistor TR20 consists of a bit line electrode 1, a work line electrode 2, a memory cell plate electrode 3, a diffusion layer 4, 5 and an oxide film 6 on the substrate 8 of a dynamic memory device, and a MOS capacity 9 consists of the plate electrode 3, the oxide film 6 and a storage node 7 on the substrate. The plate electrode 3 is formed with the first polysilicon layer and on the plate electrode 3, the second layer polysilicon 14 is formed through an oxide film 13. With grounding the polysilicon 14, a decoupling capacitor 15 of cell plate potential is constituted. On the plate electrode 3, voltage recorded to the half with resistors 11 and 12 is impressed, voltage being the half of writing voltage to the memory cell, and the potential of the plate electrode 3 is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION The invention relates in particular to memory cell plate and substrate potentials.

[Conventional technology]

Conventionally, dynamic MO3RAMs have frequently used one-transistor/one-transistor/one-capacitor type memory cells that can be highly integrated. FIG. 3 shows a cross-sectional view of a typical cell of this type.

In the figure, 1 is a bit line electrode, 2 is a word line electrode, 3 is a cell plate electrode, 4 and 5 are diffusion layers, 6 is an oxide film, 7 is a storage node, and 8 is a substrate. The bit line electrode 1, the word line electrode 2, the diffusion layers 4 and 5, and the oxide film 6 form the access MO3) run disk 20, which is connected to the cell plate electrode 3.
, an oxide film 6, and a storage node 7 constitute an MO3 capacitor 9.

This equivalent circuit is shown in Figure 4. In Figure 4, 9 is M
The O3 capacitance, 10, is the junction capacitance between the substrate 8 and the storage node 7. Normally, the cell plate electrode 3 is at the power supply voltage ■
Connected to CC1 or ground. Now Dynamic R
As the capacity of AM increases, the cell area decreases, resulting in
it9. lo decreases, but in order to ensure this M product capacity, a method is used to increase the MO3 capacity by thinning the oxide film 6. However, in this case, since the electric field applied to the oxide film increases, G) When the failure rate of the oxide film increases
Reliability problems arise. As a countermeasure to this problem, there is a method of reducing the voltage at the cell plate electrode to half the write voltage, and by doing so, the maximum electric field applied to the oxide film can be halved and reliability can be ensured.

In the case of a dynamic RAM with a single power supply voltage of 5 µm, as a means to achieve half the write voltage mentioned above, divide the resistor by 11°12 as shown in Figure 5, or divide the resistor into 12° as shown in Figure 6. MOS) There are 23 run raster divisions,
In either case, the output resistance inevitably becomes high due to the standby current limit of the dynamic RAM and the transistor size limit.

Furthermore, in normal dynamic RAM, a reverse bias voltage is applied to the diffusion layer to the substrate in order to prevent injection of electrons from peripheral circuits into the memory cell due to negative spike voltages and negative input voltages. Dynamic RAMs, which are equipped with a mechanism for generating voltage inside a chip, have become mainstream in recent years.

However, this type of dynamic RAM has the disadvantage that memory cell information is lost if the cell plate has high electrical resistance with respect to the ground or power source. This drawback will be explained below.

Normally, the substrate voltage is generated by the charge pump circuit shown in FIG. 7. In the figure, 14 is a MOS transistor, 15 is a capacitor, 16 is an oscillator, and VBB is the substrate voltage. The voltage VBB generated by this circuit is electrically floating, unlike the voltage applied by an external power supply, and is therefore susceptible to fluctuations due to capacitive coupling, etc.
Figure 6 shows typical waveforms of the substrate potential during dynamic RAM operation.
WL indicates a word line signal, SE a sense signal, and VBB a substrate voltage. After the external RAS signal ext and RAS fall, the word line signal WL rises and the information of the memory cell is transmitted to the bit line. After this, the sense signal SE rises and senses the bit line. At this time, in a normal dynamic RAM, all the bit lines are sensed at once, so the charge in the large junction capacitance il (junction capacitance 11 between the diffusion layer 4 and the substrate 8 in FIG. 3) is discharged. ．． Due to the capacitive coupling, the substrate potential VBB undergoes fluctuation in the direction of negative potential.

Next, when the external RAS signals ext and RAS rise, all the bit lines are precharged in preparation for the next memory cycle after the word line signal WL falls. At this time, the substrate potential also fluctuates toward a positive potential due to the coupling of the junction capacitance between the N+ diffusion region of the bit line and the substrate.

FIG. 9 shows the influence of such fluctuations in substrate potential on memory cells. In FIG. 9, SN represents a storage node, WL represents a word line, and BL represents a bit line.

The electron potential level is also shown upwards.

First, the state before the change will be explained. The lower part of the figure shows the case when a low-level potential is written, and the H shows the case when a high-level potential is written, and both represent a state in which electrons are packed up to the level indicated by the line. The difference in H state corresponds to the amount of charge stored in the memory cell. Here, when the word line WL becomes a high level (VCC level), the potential of the transfer gate to which the word line WL signal is applied is M higher than the high level (V CC) of the word line WL.
OS) transistor threshold voltage VTI (as low as VC
It becomes the level of C-VTH, and when the information is high, this level is written into the memory cell. Then, when the word line WL becomes low level, the potential of the transfer gate to which the signal of the word line WL is applied becomes higher than the ground level by the threshold voltage VTII, and the storage node and the bit line are cut off.

Now, the bit line is sensed and low or high level information is transmitted to the storage node, and after the word line is closed and the information is stored in the memory cell, the potential changes to positive potential, so the potential of the storage node also changes. , the potential changes to a positive level by the amount that the fluctuation voltage of the substrate is divided by the capacitance between the junction capacitance shown in FIG. 4 and Mo5g1t. In this state, as shown after the fluctuation in FIG. 9, both the low and high level potentials decrease. Then, in the next cycle, when the ↑ blue report of the memo 1 cell is not read, the potential of the word line is higher than ■CC-
Because it only drops to the VTI+ level, it changes at h
(7) The amount of continuous charge decreases as shown by hatching in the figure. This decrease increases by about 1 because the fluctuation of the substrate potential is large.

Incidentally, the magnitude of the fluctuation in the substrate potential depends on the junction capacitance that causes capacitive coupling and the stray capacitance between grounds and power supplies of the substrate itself. That is, the larger the stray capacitance, the smaller the fluctuation in the substrate potential. The stray capacitance of the board itself is the sum of the junction capacitance between the ground line and the diffusion layer of the power supply line, the capacitance between grounds via the junction capacitance of the bit line, and the capacitance between grounds via the junction capacitance 9 of the storage node. Among these, for large-capacity memory, the capacity via the storage node's junction capacity accounts for about half of the total capacity.

As shown in the memory cell equivalent circuit in Fig. 4, the capacitance per memory cell between the substrate and the ground via the junction capacitance lO of the storage node is the junction capacitance 10 and MO38'ff.
Since the junction capacitance 10 is usually about 20% of the MO3 capacitance 9, the capacitance between the substrate and GND is approximately equal to the junction capacitance 10. However, as mentioned above, when applying about half of the write voltage to the cell plate,
Since the cell plate has a high electrical resistance with respect to the ground, the magnitude of the MO3 $19 with respect to the ground is effectively reduced, and the MO3 capacitance 9 can no longer be ignored. As a result, the capacitance per memory cell between the substrate and the ground via the junction capacitance 10 of the storage node decreases more than the junction capacitance IO. As a result, the stray capacitance of the substrate itself decreases, and the fluctuation of the substrate potential due to charging and discharging of the via 1-line increases, causing a fluctuation that is 2 to 3 times as much as when normal ground or power supply voltage is applied to the cell plate. In some cases.

[Problem that the invention seeks to solve]

Due to the above reasons, if a device has a built-in substrate potential generation circuit and applies half the write voltage to the cell plate L-, there is a risk that the amount of stored charge will be lost and the operating margin of the dynamic RAM will decrease. Ta.

This invention was made to solve the above-mentioned problems, and it is possible to apply half the write voltage to the cell plate without losing the M product charge, and to reduce the electric field applied to the gate oxide film. The purpose of the present invention is to provide a dynamic memory device that can reduce the storage capacity by half and dramatically improve its reliability.

[Failure to solve the problem]

In the dynamic memory device according to the present invention, after an insulating film is stacked on top of a cell plate made of first layer polysilicon, an electrode having the same shape as the cell plate is formed from second rfl polysilicon, and this is grounded or A decoupling capacitance is provided between the cell plates by connecting to the power supply voltage.

[Effect]

In this invention, a capacitance is provided between the first layer polysilicon and the second layer polysilicon, and this capacitance increases the capacitance between the cell layer and the ground or power supply.
The potential of the cell plate is kept stable, and the stray capacitance of the substrate is prevented from decreasing due to the high resistance of the cell plate to the ground or power supply.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a dynamic memory device according to an embodiment of the present invention. In the figure, 1 to 8 are similar to those in FIG. 3, and in order to apply half the write voltage to the cell plate 3, A resistor 11.12 division similar to that shown is used.

In addition, 13 is a cell plate 3 made of the first layer polysilicon.
The oxide film 14 stacked on top is a decoupling capacitance electrode made of second layer polysilicon, which is grounded.

In addition, in FIG. 2, 15 in FIG. 0 shows the equivalent circuit of FIG. 1, cell play 1-3. This is the decoupling capacitance formed by the oxidized M'A 13° electrode 14. By creating a capacitance using the first polysilicon layer and the second polysilicon layer in this manner, a large decoupled capacitance having an area approximately equal to the entire cell plate can be formed over the entire memory cell array.

Next, the effects will be explained. This embodiment has the decoupling capacitor 15 configured as described above, and by providing the capacitor 15, even if the potential of the substrate 8 changes, the potential of the cell plate electrode 3 hardly changes. Conversely, the decoupling capacitance 15 causes the cell plate 3 to have high resistance to the ground and power supply
Since the disadvantage of an effective reduction in S $tft 9 can be eliminated, it is possible to suppress potential fluctuations of the substrate 8 to a small level.

Therefore, in this embodiment, when applying a voltage that is half the write voltage to the cell plate to ensure reliability, reducing the amount of accumulated charge and suppressing large fluctuations in the substrate potential due to applying the half voltage. becomes possible.

In the above embodiment, the case where the substrate battery is used with a 5Vffi-power source has been described, but the counter electrode may be connected to the power supply voltage, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the second polysilicon layer is formed on the cell plate via the insulating film, and the decoupled capacitance is formed by grounding the polysilicon layer or connecting it to the power supply voltage. This has the effect of making it possible to obtain an Inamifuku memory device with a large decoupling capacitance and with small potential fluctuations of the cell plate and, by extension, the substrate.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a Guinaminok memory device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is a diagram showing a typical configuration of a conventional dynamic MOS memory. 4 is an equivalent circuit diagram of FIG. 3, FIGS. 5 and 6 are diagrams showing conventional examples of resistor division and MOS) transistor division to obtain half the write voltage, and FIG. The figure shows an example of a charge pump circuit conventionally used to generate substrate voltage inside a chip. Figure 8 is a waveform diagram illustrating fluctuations in substrate potential during dynamic RAM operation. Figure 9 is , when there is a fluctuation in the substrate potential, in the accumulation diagram, 13 is the oxide film, 14 is the second layer polysilicon, 3 is the cell plate salt i, 11.12 is the resistance, 23 is the MOS)
It is a rangister.

Claims (2)

[Claims] (1) In a dynamic memory device having one transistor/one capacitor type memory cell, a memory cell plate is formed of a first polysilicon layer, and a second polysilicon layer is formed on the cell plate with an insulating film interposed therebetween. form,
A dynamic memory device characterized in that the second polysilicon layer is grounded or connected to a power supply voltage to constitute a decoupling capacitor for a cell plate potential. (2) The dynamic memory device according to claim 1, characterized in that a voltage that is half the write voltage to the memory cell is applied to the cell plate.