JPS61174669A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To vary potential on the inversion layer side of memory capacitance constituted of an inversion layer and a common electrode for memory cells intentionally, and to prevent a leakage to a bit line of charges stored in the memory capacitance of the memory cells by giving the potential of the common electrode by a clock. CONSTITUTION:A common electrode 2 is connected to a power supply terminal 7 by clock pulses CP1 on reading and writing, and stable potential is obtained. When reading and writing cycles are completed, the clock pulses CP1 are brought to a low level and a transistor 10 is interrupted while clock pulses CP2 are brought to a high level and the potential of the common electrode 2 is made higher than supply voltage by a capacitance 11. The potential of an inversion layer 4 is also elevated by the operation, and a transfer transistor TG is not conducted, thus resulting in no leakage to a bit line 5 of electrons in the inversion layer 4 in a memory cell. Accordingly, the lowering of the SN ratio of a reading signal can be obviated, thus realizing high performance of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory devices, in particular dynamic random access memories.
) memory cell has one MOS transistor and one M
The mainstream is one composed of OS capacitors.

An example of a conventional memory cell is shown in FIGS. 3 to 61. FIG. 3 is a plan view showing a part of the memory cell play, FIG. 4 is a sectional view taken along the line AA' in FIG. 3, and FIG. 6 is an equivalent circuit of this part. The storage capacitance C8 of the memory cell fabricated in the silicon substrate 1 is connected to the common electrode 2. It is formed by a thin dosing film 3 and an inversion layer 4 and K formed therebelow. The common electrode 2 is common to a plurality of memory cells and is connected to either a power supply terminal or a ground terminal. Incidentally, the diffusion region 6 forming the bit line is located near the inversion layer 4, and the transagate 6 is further arranged so as to straddle the inversion layer 4, thereby forming the transfer transistor TG. Further, the common electrode 2 is connected to a power supply terminal 7, and the transfer 1 gate 6 is connected to a word line 8. In the mesori cell configured in this way, the contents stored in the inversion layer 4, whether it is filled with electrons or a depletion layer @O'',
'1n corresponds. In the following explanation, the state in which the inversion layer 4 is filled with electrons is assumed to be 10". FIG.
．． 6 are connected, one side is at the ground voltage during the read/write cycle, and when the cycle ends, it is charged to the power supply voltage.

Problems to be Solved by the Invention In the conventional DRAM memory cell, as shown in FIGS. 3 to 6, the bit line 6 and word line 8 are formed by a diffusion region for forming a bit line, an insulating film between the eyebrows, and a word line. Capacitive coupling due to the parasitic capacitance formed by the metal layer, such as the Al film, forming the line 8, and the parasitic capacitance formed by the diffusion region 6, transformer 7, agate 6, and the insulating film between them, forming the bit line. are doing. Further, as shown in FIG. 6, one word line intersects with 266 bit lines/(6 or 5), and this capacitive coupling is not small. Therefore, the word line is affected by potential fluctuations of the bit line. In particular, unselected word lines are below ground voltage during read/write cycles, while floating above ground voltage when charging bit lines. In addition, as shown in FIG. 4, the common electrode 2 of the memory cell is fixed to the power supply voltage and has a constant value, so if the memory content of the memory cell whose gate is the unselected word line is '0'' , when charging the bit line, the potential difference between the transformer 7 agate 6 and the inversion layer 4 exceeds the threshold voltage of the transfer gate 6. Therefore, electrons in the inversion layer 4 leak toward the bit line 6. This causes the inconvenience that the readout signal of 'Q' becomes small.

Means to Solve the Problem The present invention adopts a configuration in which the potential of the common electrode of the memory cell is given by a clock, thereby intentionally varying the potential on the inversion layer side of the storage capacitor constituted by the inversion layer and the common electrode. This prevents charges accumulated in the storage capacitors of memory cells connected to unselected word lines from leaking to the bit lines.

If such consideration is taken, the potential of the common electrode of the memory cells will be raised by the clock in synchronization with this timing, although some floating will occur in the non-selected word lines when the bit lines are charged.

Therefore, the memory content "0" connected to the non-selected word line
The inversion layer of the memory cell is also lifted, and the potential difference between the gate and lease of the transfer transistor TG does not exceed the threshold voltage of this transfer transistor, which prevents electrons in the inversion layer from leaking to the bit line. .

EXAMPLES Below, the semiconductor memory device of the present invention will be explained in detail with reference to FIGS. 1 and 2.

FIG. 2 is an equivalent circuit diagram showing the configuration of the semiconductor memory device according to the present invention, in which the basic component in which the memory cell is composed of a storage capacitor C8 and a transfer transistor TG is the same as that of the conventional device. , the common electrode 2 is connected to the power supply terminal 7 via the transistor 10 to which the first clock pulse CP1 is applied to the gate, and the common electrode 2
A second clock pulse Cp? is applied via the capacitor 11 to Cp? Therefore, when the first clock pulse Cp1 becomes high level, the transistor 1
o becomes conductive, and the potential of the common electrode 2 becomes the power supply potential. On the other hand, the potential of the common electrode 2 is raised to a potential higher than the power supply voltage by the first clock pulse Cp1 being at the low level and the second clock pulse Cp2 being at the high level.

In FIG. 2, the first and second clock pulses Cp1°C
Clock pulse suit for p2p-word selection and clock pulse φ for bit line precharge
Indicates the timing of During reading and writing, the common electrode 2 is connected to the power supply terminal 7 by the clock pulse Cp1 and has a stable potential. When the read/write cycle ends, the clock pulse Cp1 becomes low level and the transistor 1o is cut off. On the other hand, as the clock pulse Cp2 becomes high level, the potential of the common electrode 2 is changed to β from the power supply voltage by the capacitor 11. only becomes higher.

This operation also increases the potential of the inversion layer 4 by γ. γ
is determined by the capacitance C8 formed by the inversion layer 4 and the common electrode 2 and the capacitance Cs formed between the inversion layer 4 and the silicon substrate 1, and is given by the following equation.

Even if the unselected word line floats from the ground voltage by δ due to coupling during precharging of the bit line, γ+vTH〉δ ・・・・・・・・・・・・・・・
...@) (vTH is the threshold voltage of the transfer transistor), the transfer transistor TG will not conduct. Therefore, memory content “O”
Electrons in the inversion layer 4 of the memory cell do not leak to the bit line.

It goes without saying that the configuration of the present invention described above also applies to a dynamic random access memory of the folded bit line type.
It is possible to eliminate a decrease in the S/N ratio of the TQn read signal, and the performance of the semiconductor memory device can be improved.

[Brief explanation of the drawing]

The timing charts of FIGS. 3 to 5 are schematic diagrams of conventional Mori cell arrays. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Common electrode, 3...Oxide film, 4...Inversion layer, 6...
...Diffusion area (bit line), 6...
Transfer gate electrode, 7... Power supply, 8...
...Word line, 9...Sense amplifier,
1o...Switch transistor, 11...
...Capacitor, C8...Cell capacity, TG...
...transfer transistor. Name of agent: Patent attorney Toshio Nakao and one other person - ω Figure 6 9-m- 〉Mataan 7゜5J--- Pissiline Genkuuna

Claims (1)

[Claims] A memory cell is constituted by a MOS transistor and a MOS capacitor fabricated in a single semiconductor substrate, the MOS capacitors of the plurality of memory cells have a common electrode, and further a potential supply means for the common electrode is provided. What is claimed is: 1. A semiconductor memory device comprising: an equal potential supply means coupled to a clock signal application terminal.