JPS6137707B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic semiconductor memory device using a MOS capacitor as a storage element, and particularly to stabilizing the amount of cell information against fluctuations in power supply voltage.

A dynamic semiconductor memory device using a MOS capacitor as a storage element is generally constructed as shown in FIG. In this figure, SA is a sense amplifier, BL,
PRE is a pre-charge circuit consisting of MOS transistors _Q1 to _Q3 , MC is a memory cell consisting of MOS transistor _Q5 and MOS capacitor _Cs , and DMC is a bit line pair extending left and right from sense-up SA.
is a dummy cell consisting of MOS transistors Q ₆ and Q ₇ and MOS capacitor C _D , WL is a transistor
DWL is the word line that turns on _Q5 and connects the cell MC to the bit line BL.DWL is the dummy word line that turns on the transistor _Q6 and connects the dummy cell DMC to the bit line.DWL turns on the transistor _Q7 and connects the dummy cell DMC to the bit line _BL. In other words, BC is a signal that sets node _N2 to the low potential side voltage _Vss (usually 0V) of the memory power supply.BC turns on transistors _Q1 to _Q3 , shorts the bit line pair BL, and This is a signal to precharge the potential side voltage _Vcc (generally 5V), and C _B indicates the bit line capacitance. Note that _Vcc is applied to the opposing electrodes of the MOS capacitors C _S and C _D.

FIG. 2 is an operational waveform diagram when reading information "0" from the cell MC of FIG. 1. After writing or refreshing is completed and the word line WL is lowered to _Vss , the signal BC is raised to precharge the bit line BL to _Vcc , and the node _N2 of the dummy cell DMC is set to _Vss . Move to standby state. This type of memory device generally has a reference power supply of _Vcc = 5V, but this is allowed to fluctuate by ±10%, so in reality, _Vcc may vary between 4.5 and 5.5V. There is. Figure 2 shows that when _Vcc = 4.5V, "0" is written to the cell MC ( _N1 point is set to _Vss ) and while it is read out at time _t2 , _t0 during the standby period. This is an example of a waveform when _Vcc rises from 4.5V to 5.5V at ~ _t1 . Generally dummy cell
Since the capacitance C _D of DMC is set to C _D = 1/2 C _{S with respect to the capacitance C S of} the memory cell MC, V _cc remains at 4.5 V even at time t ₂ , unlike in Fig. 2. Then, when WL rises, current flows from bit line BL to cell node N ₁ and dummy cell node N ₂ , and the voltage of BL drops, and the voltage drop is approximately V _cc C for each of BL. Since _D /C _B and V _cc C _S /C _B , the bit line BL
The potential _V BL of the bit _line and the potential V _BL of the bit line are V _BL = V _cc - V _{cc CD} / _CB = 4.5-4.5 _CD / _CB = 4.5-4.5/2 _CS
/C _B ... (2) V _BL = V _cc - V _cc C _S /C _B = 4.5-4.5 _{C S} /C _B ... (3) Therefore, the differential voltage ΔV _BL of the bit line BL is ΔV _BL = |V _BL -V _BL | =2.25C _S /C _B (V)...(4). However, as shown in Figure 2, from t ₀ to t ₁ , V _cc =
If it fluctuates to 5.5V and maintains this value thereafter, V _cc
When the voltage rises to 5.5V, the potential of the node _N1 is pushed up by the capacitor C _S and rises by 1V corresponding to the change in _Vcc ,
The bit line potential is as follows.

V _BL =V _cc -V _{cc CD} /C _B =5.5-5.5C _D /C _B =5.5-5.5/2 C _S
/C _B ......(5) V _BL = V _cc - (V _cc -N ₁ ) C _S /C _B = V _cc - (V _cc -1.0) C _S /C _B = 5.5-4.5 C _S /C _B ...(6) Therefore, the differential voltage at the read time _t2 decreases to ΔV _BL =|V _BL -V _BL |=1.75C _S /C _B ...(7). In this circuit, the above-mentioned problem does not occur when reading "1". In other words, writing "1" to the memory cell MC means setting the node N ₁ to V _cc in this example, so the potential of the node N ₁ is 4.5V when the writing is completed, and then the power supply is set to 5.5V. When there is a fluctuation, the node N ₁ is pushed up by the capacitor C _S to 5.5V, and when it enters the takeover state, it is similar to the “1” lead when there is no fluctuation in the power supply voltage.
No charge is extracted from the bit line BL, and a charge corresponding to 1/2 C _S is extracted from the bit line, which is precharged to 5.5V on one side, and these are exactly the same as in normal times.

In the memory circuit shown in Figure 1, the “0” lead is affected by power supply voltage fluctuations as described above, and this is due to the MOS
This is due to the fact that _Vcc is applied to the opposing electrodes of the capacitances C _S and C _D. Opposite electrode potential of MOS capacitor C _S
If an impurity opposite to the substrate is implanted under the MOS capacitor using techniques such as ion implantation, V
You can use V _SS instead of _cc . If V _SS is used, it seems possible to avoid potential fluctuations at node N ₁ due to voltage fluctuations in V _cc . The circuit shown in FIG. 3 is based on this point of view, and the potential of the opposing electrode of the MOS capacitor is set to V _SS . However, although the circuit shown in FIG. 3 has no problem with "0" leads, it is affected by power supply fluctuations with "1" leads. Figure 4 shows the operating waveform of the "1" lead in Figure 3, and the cell MC also has a "1" at _Vcc = 4.5V.
In this example, _Vcc is changed to 5.5V from _t2 to _t1 . Unlike Fig. 4, if _Vcc maintains 4.5V until _t2 during reading, _VBL = _Vcc - _{Vcc CD} / _CB = 4.5-4.5/2 _CS / _CB ......(8) , and if the information of cell MC is “1”, N ₁ =
Since the voltage is 4.5V, even if the word line WL rises, no charge flows from the bit line BL to the _N1 point, so V _BL =V _cc =4.5V (9). Therefore, ΔV _BL =|V _BL −V _BL |=2.25C _S /C _B ...(10), which is the same as equation (4). However, as shown in Figure 4, if the power supply V _cc rises to 5.5V during the standby period, V _BL = V _cc - V _{cc CD} / _CB = 5.5-5.5 _CD / _CB = 5.5-5 .5/2 C _S
/CD...(11 ), and even if _Vcc rises to 5.5V, the _N1 point does not rise and remains at 4.5V, so the charge flowing into cell MC is _VBL = _Vcc - (V _cc -N ₁ ) _CS / _CB =5.5-(5.5-4.5) _CS / _CB =5.5- _CS /C
_B ...(12) Therefore, the differential voltage at read time _t2 decreases to ΔV _BL = |V _BL -V _BL |=1.75C _S /C _B ...(13), similar to equation (7). .

Figure ₅ shows an example of _a circuit that improves these points _.
Generates a voltage V _c =V _cc /2 corresponding to 1/2 of _cc ,
This is applied to the opposing electrodes of the MOS capacitors C _S and C _D . FIG. 6 is an operational waveform diagram of this circuit when reading "0", and FIG. 7 is an operational waveform diagram when reading "1". In this circuit, _Vcc = 4.5V for both “0” write and “0” read
If it is constant, the differential voltage at the time of reading is ΔV _BL =2.25C _S /C _B (14), and as shown in Figure 6, when V _cc is between t ₀ and t ₁ ,
Even if it fluctuates from 4.5V to 5.5V, if the readout time _t2 is slow enough _{, Vc and N1 will change as shown, so VBL = Vcc - Vcc CD / C B = 5.5-5.5C D /} C _B =5.5-5.5/2 C _S /C _B =5.5-2.75 C _S
/C _B ......(15) V _BL =V _cc - (V _cc -N ₁ )C _S /C _B =5.5-(5.5-0.5)C _S /C _B =5.5-5C _S /C
_B ...(16) Therefore, the differential voltage at _t2 is ΔV _BL =|V _BL -V _BL |=2.25C _S /C _B ...(17), which is the same as equation (14). Similar thing is “1”
This also applies when leading. In other words, if V _cc = 4.5V constant, the differential voltage during reading is ΔV _BL = 2.25C _S /C _B (18), and as shown in Figure 1, when V _cc is between t ₀ and _{t 1} in
Even if it fluctuates from 4.5V to 5.5V, if the readout time _t2 is slow enough, V _BL = V _cc - V _cc C _D /C _B =5.5-5.5/2 C _S /C _B ......(19) V _BL =V _cc -(V _cc -N ₁ )C _S /C _B =5.5-(5.5-5)C _S /C _B =5.5-0.5C _S /C
_B ...(20) Therefore, the differential voltage at _t2 is ΔV _BL =|V _BL -V _BL |=2.25C _S /C _B ...(21), which is the same as equation (18).

However, in this memory circuit, the value of resistor R ₁ is made large in order to reduce power consumption, so the quick response of V _c to fluctuations in V _c is poor, and if the read time t ₂ is earlier, ΔV _BL becomes smaller. For example, in a 64K-bit RAM, the capacitance C connected to the _Vc point of the voltage divider PS ₁ , which is used in common for all cells, is
1000 _pF , and the current I _R1 flowing through the resistor _R1
If 2R ₁ =50KΩ is set in order to suppress the voltage to 0.1 mA or less, the change that appears in V _c when V _cc fluctuates has a time constant of 2R ₁ ·C = 50 μm. Therefore, if reading is performed at t ₁ immediately after V _cc changes to 5.5V in Figure 7, the differential voltage will be ΔV _BL = 1.75C _S /C _B ... (22), which is the same as equation (13). .

The present invention further improves this point and provides a circuit configuration that has the advantage that the amount of information in the cell (the amount of charge extracted from the bit line) does not change even when the power supply changes in any frequency component, and there is no need for dummy cells. This is what we are trying to provide. It has a plurality of word lines and bit lines, memory cells are arranged at their intersections, the memory cells use a capacitor connected to the bit line via a transfer gate as a storage element, and the bit line is used as a bridge charger. charge to voltage,
In a dynamic type semiconductor memory device in which the bit line is set to a high potential or a low potential depending on the amount of charge in the capacitor, the bridging voltage and a counter electrode of the capacitor opposite to the transfer gate are provided. The circuit is characterized in that it is provided with a circuit for setting both side voltages to the median value of the high potential voltage and the low potential voltage of the bit line, and this will be explained in detail below with reference to the illustrated embodiment. .

Fig. 8 is a circuit diagram showing an embodiment of the present invention, Fig. 9 is an operation waveform diagram when reading "0", and Fig. 10 is a circuit diagram showing an embodiment of the present invention.
The figure is an operation waveform diagram when reading "1". There are two points in which Fig. 8 differs from Fig. 5. The first is that the power supply V _cc
The output V _c of the voltage divider circuit PS ₂ , which generates a voltage equivalent to 1/2 of (V _cc - V _SS )/2, is applied not only to the counter electrode of the MOS capacitor C _S but also to the bricharge circuit.
The point is that it is applied to PRE as well. Second
In this case, the standby potential of the bit line BL, which is charged up by the precharge circuit PRE, is _Vcc /2, so the potential of the bit line itself can be used to determine cell information, and therefore the dummy cell DMC is omitted. It is a point. Accordingly, in this memory circuit, the dynamic pull-up circuit DPU is connected to the bit line.

When writing or refreshing the cell MC at V _cc = 4.5V and lowering the word line WL to V _SS , the bit line on the high potential side is 4.5 V and the bit line BL on the low potential side is 0 V. , after this, increasing the signal BC turns on transistors Q ₁ to Q ₃ ,
The charge on the bit line side is distributed to the bit line BL side through transistor _Q3 , and both are at their intermediate value.
Balance at 2.25V (time t ₀ ). The bit line BL is now in standby mode, and the potential of the bit line BL, which fluctuates due to juncture leaks, is compensated by the voltage divider _PS2 and maintained at 2.25V. When reading, when the word line WL is raised, a minute potential difference ΔV _BL is generated on the bit line BL depending on the cell information. Then, the sense amplifier SA is driven, and the potential of the bit line on the low level side is dropped to V _SS by the transistor of the sense amplifier, and the bit line on the high level side is pulled up to V _CC by the dynamic pull-up circuit DPU, and BL , the potential difference between them increases significantly. This enlarged potential difference on the bit line BL is led to the read/write amplifier through a column line (not shown).

Next, operations in various states will be explained with reference to FIGS. 9 and 10. If _Vcc remains at 4.5V when reading “0”, there is no change in the potential of the bit line because there is no dummy cell, _VBL = _Vc = 2.25V (23), and the potential of the bit line BL is _VBL = _Vc - _{VcCS /CB =} 2.25V- _2.25CS / _CB ...(24). Therefore, ΔV _BL =|V _BL −V _BL |=2.25C _S /C _B (25). When reading "0", _Vcc changes from 4.5V to 5.5V during the standby period, and when reading immediately after that at _t1 , _Vc remains at 2.25V due to the time constant mentioned above, and when _N1 = 0V. Therefore, the result is the same as above. When reading “0”, V _cc fluctuates from 4.5V to 5.5V during the standby period, and when reading after a sufficient time t ₂ , V _BL = V _C = 5.5/2. =2.75V ……(26) V _BL =V _C −(V _C −N ₁ )C _S /C _B =2.75−(2.75−0.5) C _S /C _B =2.75−2.25C _S /C _B … (27) Therefore, ΔV _BL = |V _BL −V _BL |=2.25C _S /C _B ...(28). If V _cc = 4.5V when reading “1”, V _BL = V _C = 2.25 V … (29) V _BL = V _C + (V _cc −V _C ) C _S /C _B = 2.25 + ( 4.5-2.25) Since C _S / C _B = 2.25 + 2.25 _{C S} / C _B ... (30), ΔV _BL = | V _BL - V _BL | = 2.25 C _S / C _B ... (31) . Immediately after the power supply _Vcc changes from 4.5V to 5.5V during the standby period when reading “1”, _t1 is _Vc
= 5.25V, N ₁ = 4.5V, so the result is the same as above. When reading “1”, a sufficient amount of time has elapsed since the above power fluctuation during the standby period t ₂
From now on, V _BL = V _C = 5.5/2 = 2.75V ... (32) V _BL = V _C + (V _cc +0.5-V _C ) C _S /C _B = 2.75 + (4.5 + 0. 5-2.75) Since C _S / C _B = 2.75 + 2.25 _{C S} / C _B ... (33), ΔV _BL = | V _BL - V _BL | = 2.25 C _S / C _B ... (34) Become. The above,,, is the circuit shown in Fig. 8, and V
This assumes all cases in which information "0" or "1" is written to _cell MC at cc = 4.5V, and then read after V _cc = 5.5V.
The results (formulas 28 and 34) are the same as when reading with _Vcc = 4.5V (formulas 25 and 31). Therefore, the amount of information in the cell MC can always be kept constant regardless of power supply fluctuations, and in particular, stable reading can be performed immediately after fluctuations in _Vcc , which increases the reading speed and also improves the voltage divider circuit. This is effective in increasing the values of resistors R ₂ and R ₂ of PS ₂ and reducing the current flowing there. Also,
Since reading is possible without requiring a dummy cell DMC, the configuration is simplified.

In the present invention, the bit line to which the precharge voltage is applied and the opposing electrode of the memory cell are both set at approximately the midpoint between the high potential and the low potential using a voltage divider circuit. The line and the opposing electrode of the cell are made to fluctuate in the same way and by the minimum amount of fluctuation, thereby making it possible to prevent a decrease in read sensitivity. That is, in the case of a one-transistor cell type as in the present invention, reading is performed by relative comparison of the potential of the intra-cell node _N1 and the potential of the bit line BL. For example, when “0” is stored, node N ₁ in the cell
The potential of is 0V, and the amount of voltage change of the bit line is determined by how much charge is drawn from the bit line to the capacitor in the cell depending on the difference with the bit line precharge level, and this amount is read out by the sense amplifier. -ing Therefore, even if power supply voltage fluctuations occur, the nodes in the cell that are relatively compared
If the potential of _N1 and the bit line precharge potential fluctuate in the same way or in the same direction, there will be no effect on read sensitivity. Since the potential of the node N in the cell changes due to capacitive coupling with the counter electrode of the cell, in the present invention, the counter electrode of the cell and the bit line precharge voltage are connected to the output terminal of the 1/2 V _cc (median value) generation circuit. They are trying to connect and keep the relative potential difference between them constant. In this regard, when the counter electrode of the cell shown in the conventional example is V _cc (high potential) (Figures 1 and 2), the counter electrode of the cell is V _SS (low potential).
As mentioned above, the effect of the present invention cannot be obtained in the case of (Figures 3 and 4) and when only the opposite electrode of the cell is set to 1/2V _cc (median value) (Figures 5 and 6). It is.

As described above, the present invention has the advantage that in a one-transistor, one-capacitor type semiconductor memory device, the amount of cell information can be stabilized against fluctuations in the power supply voltage, and the structure can be simplified.

[Brief explanation of the drawing]

Figures 1 and 3 are circuit diagrams of a typical one-transistor, one-capacitor type semiconductor memory, Figures 2 and 4 are their operating waveform diagrams, and Figure 5 is a conventional one that takes measures against power fluctuations. A circuit diagram of a capacitor type semiconductor memory with one transistor, FIGS. 6 and 7 are its operating waveform diagrams, FIG. 8 is a circuit diagram showing an embodiment of the present invention, and FIGS. 9 and 10 are its operating waveform diagrams. It is. In the figure, MC is the memory cell, C _S is its MOS capacitor, BL is the bit line, PRE is the precharge circuit, PS ₂ is the voltage divider circuit, V _cc is the high potential side voltage of the memory power supply, and V _SS is the same low potential. side voltage.

Claims (1)

[Claims] 1 In a semiconductor memory device in which a large number of dynamic memory cells having MOS capacitors as storage elements are arranged in a matrix, the bit line precharge voltage and the counter electrode voltage of the MOS capacitor are both the high potential side voltage and the low potential side voltage of the memory power supply. 1. A semiconductor memory device comprising a circuit for setting a median value between .