JPS595994B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (IG-F
The present invention relates to semiconductor memory devices using ET (also referred to as MOS transistors), and particularly to improvements in the memory cell portion thereof.

MOS type semiconductor storage device (referred to as MOS memory) is
Broadly divided into dynamic memory and static memory, the former has developed as a highly integrated memory, and the latter as an easy-to-use memory with fewer timing constraints.In recent years, however, a type of memory that is a fusion of the two or an intermediate form between the two has developed. The field of memory is emerging.

In other words, by using dynamic operation memory cells to increase the degree of integration and by devising peripheral circuits, we can reduce timing constraints.
The most complicated timing constraint for dynamic RAM, which is a RAM whose performance is apparently close to that of static RAM, is related to refresh.

Rib V-tubing refers to an operation for periodically recharging the charge stored in the capacitance within the memory cell, which is discharged due to leakage. The most common rib V-tush method is a method in which the information read out from the memory cell for each column is amplified by a sense amplifier, and then rewritten is repeated several times for the bits in the row direction. During the above-mentioned refresh period, normal operation must be halted, and there is a problem in that the timing design of the entire system is more complicated than in a static RAM that does not require refresh. One method to improve this problem is to refresh the memory cells at the same time.

Figure 1 is an example of a simple refresh type memory cell considered from this point of view. Tl, T2, T in the figure
, are N-channel MOS transistors, w is a signal line for write control, R is a signal line for reading and refreshing, Ar is an address line, DL
is a data line, E is a power supply line, and Ba is a MOS varactor. This MOS element Ba has a storage charge of 2. This is a capacity for storing , but here it is used as a switching capacity. That is, in a state in which a positive charge is charged to the node N1 and an inversion layer is formed directly under the gate of FLsBa, that is, in the "1-memory state," Ba is connected between the node N1 and the line R through the above three inversion layers. , in a state in which positive charges are not charged at node N1, that is, in a 00° storage state, Ba is connected to node N1 and the substrate (P-
(well layer). Capacity that functions in this way is called switching capacity. FIG. 2 shows internal waveforms of the memory cell shown in FIG. 1 during refresh operation.

In the waveforms of nodes N1 and N2 in the diagram, the solid line is the waveform when the force 1'' is stored, and the dashed line is the waveform when the force ``0'' is stored. The signals supplied to line R and line W are in opposite phase to each other, R is in read mode at 11'', and w is in write mode at 617. First, time T. During -t1, write mode is entered. When 601 is written, both nodes Nl and N2 are at the power supply Vss level, as shown by the dashed line, and 601 is written.
During 1n writing, both nodes N2 and N2 are powered by the reverse gate bias effect of transistors Tl and T2. It is charged up to a level slightly lower than the o level. R is 61
1 and changes to the read mode, when 607 is stored, the capacitor Ba is connected between the node N1 and the P-Well board, and nodes N1 and N2 remain at the Ss level, but when 611 is stored, the capacitor Ba is connected to the node N1. and the line R, so the node N1 has 10
The potential increases by 0-Vssl, so node N2 becomes V due to transistor T3. It is charged up to O level. During the time period T2 to t1, the voltage level of the node N1 gradually decreases due to leakage current, but the voltage level of the node N2 is as long as the transistor T3 is conductive. Maintain D level. After time T2 is a writing period for refreshing, R returns to the "01 level," and when 81 is stored, the node N1 falls to the potential obtained by subtracting the potential drop due to leakage from the potential during the TO-t1 period. At the same time, the voltage becomes 1'' level and the transistor T2 becomes conductive, so the charge accumulated in the node N2 during the period T, ~T2 is transferred to the node N1 (charge division), the potential of the node N2 decreases, and the potential of the node N1 The potential at nodes N1 and N2 is restored toward the "11 level" and refresh is performed. In the above-mentioned refreshing operation, a back gate bias was applied to the transistor T2, so that the potential at nodes N1 and N2 after the charge division is are not completely equal and stop at 6 potential of node N2>potential 6 of node N1, and the refresh effect is not very good.

Further, when 80'' is stored, one end of the switching capacitor Ba is connected to the substrate, so the potential of the node N1 remains at the ``01'' level during the entire period from TO-T2 onwards. 60
Regarding the 1st level refresh, it is considered that there is no particular need for it.

In other words, when the 101 level stored at node N1 shifts to the 61'' state due to leakage current, the amount of off-leakage (leakage current in a non-conducting state) of transistors T3 and T2 increases When the amount of reverse leakage is greater than the reverse leakage of the PN junction formed between the drain end of transistor T2 and the substrate, and conversely, if the off-leakage of transistors T3 and T2 is always less than the reverse leakage of the PN junction, the memory 607 is It is held static above.
The above memory cell uses this method to eliminate the need for refreshing the 601 memory. As mentioned above, the memory cell shown in FIG. 1 has the advantage of being able to perform simple refresh, but on the other hand, the number of cell components is two compared to the well-known one-transistor type dynamic memory cell.
In other words, the number of elements in a one-transistor type cell is 1 transistor + 1 capacitor 7, whereas the one in FIG. 1 has 63 transistors + 1 capacitor 1, which is significantly inferior in terms of integration.

Furthermore, the device shown in FIG. 1 has a problem in that the refresh effect is poor due to the back gate bias effect of the transistor T2 as described above. The present invention has been made in view of the above-mentioned circumstances, and aims to provide a semiconductor memory device in which the degree of integration is increased and good refresh is possible by performing refresh using diodes.

An embodiment of the present invention will be described below with reference to the drawings.

Since the embodiment shown in FIG. 3 corresponds to the embodiment shown in FIG. 1, the same reference numerals are used for corresponding parts. As shown in FIG. 3, a switching capacitor Ba is provided between the signal line R and the node N3, an N-channel MOS transistor T1 is provided between the node N3 and the data line DL, and the gate of this transistor T1 is Address line Ar! Connect the IC. Node N3 and Node N
A Schottky diode D is provided between the node N4 and the supply line E of the power supply VDD, and an N-channel MOS transistor T3 is provided between the node N4 and the supply line E of the power supply VDD.
The gate of is connected to node N3. FIG. 4 shows internal waveforms of the memory cell shown in FIG. 3 during refresh operation. In the waveforms of nodes N3 and N4 in the diagram, the solid line is the waveform when 611 is stored, and the dashed line is the waveform when 601 is stored, which corresponds to the case in FIG. In the circuit shown in FIG. 3, the transistor T3 is in an off state during FfOl storage, and the capacitor Ba is connected to the substrate, so the stored contents are held at the S8 level regardless of the signal level of the line R. On the other hand, when 61'' is stored, the transistor T3 is on and the capacitor Ba is connected to the signal line R.
When becomes 611 level, node N3 becomes IVOO-Ssl
The potential increases. Then, the transistor T3 becomes almost completely conductive, so that the node N4 becomes. Charge up to o level. At this time, diode D is in a reverse bias state and is therefore in an off state. Next, when the line R reaches the 60'' level, the potential of the node N3 decreases by VOO-Ssl, but this causes the diode D to conduct, so that the charge at the o level is stored at the node N3. By the way, in order to form a diode element in the manufacturing process of a MOS transistor, it is not possible to make both ends of a PN junction independent potential in the normal process, so a special Although it is necessary to add a step, and therefore the process becomes complicated, the above-mentioned difficulty can be solved by using a shotgun type diode.

That is, a Schottky diode can be formed by bringing aluminum constituting the electrode wiring into contact with a relatively thin N-diffusion layer (which may of course be formed by ion implantation). - Since ion bluntation is normally used to raise the threshold voltage of a parasitic MOS transistor, there is no need to add a special process. FIG. 5 is a sectional view of an integrated circuit in which the memory cell of FIG. 3 is constructed using the above method, and the dotted line portion constitutes a shot key diode D. As can be seen from this cross section, the area occupied by the Schottky diode D can be made much smaller than the area occupied by the MOS transistor (about 15 (:!) less), and therefore the degree of integration can be increased. becomes. Furthermore, in this circuit, the recovery level of the 11 memory during refresh is higher than in the case of FIG. 1, and the refresh effect is improved. That is, in FIG. 1, the charge at node N2 is difficult to be supplied to node N1 due to the back gate bias effect of transistor T2, but in the circuit of FIG. The loss is suppressed by voltage F (approximately 0.6 to 0.7 V for P+N+ diode and approximately 0.3 to 0.4 for Schottky diode), as shown in the waveform at node N3 in Figure 4. As such, the recovery level during refresh is increased. FIG. 6 shows another embodiment of the invention.

The memory cell shown in FIG. 3 is similar to the one shown in FIG. 1 in terms of the mechanism for retaining 60" memory, but in FIG.
By connecting the V-in end of the transistor T5 to the signal line R' whose phase is delayed by inverters 11 and 12, there is no route for leakage positive charges to accumulate in the capacitor B8. There are no changes to the reflex or other operating principles. Note that the phase of the line R' is delayed with respect to the line R. When R returns to the 601 level after reaching the 11 level, 11CR' occurs before the positive charge on the node N4 transfers to the node N3 via the diode D.
This is to prevent the transistor T3 from being discharged, and if such a measure is not necessary, the drain end of the transistor T3 may be connected to the line R as shown in FIG.

It should be noted that the present invention is not limited to the above embodiment, and for example, the Schottky diode D may be replaced with a normal diode.

Moreover, the channel type of each MOS element can also be configured as a P channel type. As described above, according to the present invention, a diode is used as an element required during a refresh operation, so that a semiconductor memory device that is excellent in terms of degree of integration, refresh effect, etc. can be provided.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional MOS memory, Fig. 2 is a waveform diagram showing a refresh operation of the same circuit, Fig. 3 is a circuit diagram of an embodiment of the present invention, and Fig. 4 is a refresh operation of the same circuit. Figure 5 is a cross-sectional view of the integrated circuit of the same circuit.
6 and 7 are circuit diagrams of other embodiments of the present invention. Tl, T3...MOS transistor, D...
...Shotkey diode, B1...Switching capacitance, N3-N4...Node, E...
...Power line, DL...Data line, A
r... Address line, R,, W......
Control signal line, 11, 12... Inverter.

Claims (1)

[Claims] 1. A switching capacitor is provided between a control signal line and a first node, a first MOS transistor is provided between the first node and the data line, and a gate electrode of the transistor is provided. a diode electrically connected to the address line and between the first node and the second node;
A semiconductor memory device characterized in that a second MOS transistor is provided between the second node and a power supply potential supply line, and a gate electrode of the transistor is electrically connected to the first node. 2. The semiconductor memory device according to claim 1, wherein the diode is a short key diode. 3. A switching capacitor is provided between the control signal line and the first node, a first MOS transistor is provided between the first node and the data line, and the gate electrode of the transistor is electrically connected to the address line. connected, and providing a diode between the first node and the second node,
A semiconductor memory device characterized in that a second MOS transistor is provided between the second node and the control signal line, and a gate electrode of the transistor is electrically connected to the first node. 4. The semiconductor memory device according to claim 3, wherein the diode is a Schottky diode. 5. A switching capacitor is provided between the first control signal line and the first node, a first MOS transistor is provided between the first node and the data line, and the gate electrode of the transistor is connected to the address line. electrically connected,
A diode is provided between the first node and the second node, a second MOS transistor is provided between the second node and the second control signal line, and the gate electrode of the transistor is connected to the second node. 1. A semiconductor memory device comprising: a signal delay means electrically connected to one node of the first control signal line and between the first control signal line and the second control signal line. 6. The semiconductor memory device according to claim 5, wherein the diode is a Schottky diode.