JPS6234223A - Display control circuit - Google Patents

Abstract

PURPOSE:To attain both the display and key input processes without using an interruption input terminal by adding a means to detect the final display cycle, a means to control an additional cycle and a means to produce the interruption signal synchronous with the additional cycle. CONSTITUTION:A decoding circuit DEC detects a cycle D7 is equal to the final digit and delivers the display synchronizing signal SYN. This signal SYN is kept at '1' just for a single period of the clock CL. Thus, a specific address 08 is designated for a display memory DM for said single period together with the storage data on the address 08 of the memory DM delivered to segment terminals S0-S7. While the signal SYN is applied to an interruption control circuit of a microcomputer and therefore it is known that the data on the address 08 are delivered from terminals S0-S7 respectively.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is built in a microcomputer, outputs a segment signal and a digit signal from a segment terminal and a digit terminal, respectively, according to predetermined timing,
The present invention relates to a display control circuit that performs multi-digit display in a time-division manner and inputs segment signals to a key matrix.

[Conventional technology]

The main application of a microcomputer with a built-in display control circuit of this type is to display the keys input by an operator and the results of arithmetic processing of key data. Display processing is an essential process.

In such an application, the display must not stop even if the microcomputer is processing keys manually or processing arithmetic operations, so the display control circuit stores the display data that the microcomputer has written into the display memory 52. Segment signals and digit signals are generated by sequential reading regardless of the execution of instructions by the microcomputer, and automatic≦:time-division display is performed.

[Problem that the invention seeks to solve]

Therefore, the conventional display control circuit described above has a different operation than the display control circuit. The display is not synchronized with the microcomputer's instruction execution, and the microcomputer is configured so that it cannot know what kind of data is being output from the digit terminals and segment terminals that are the output of the display control circuit. The output data (2) made it impossible to perform key manual processing.

For this reason, in a conventional microcomputer with a built-in display control circuit, as shown in FIG. 6, (2) display processing and key manual processing are performed using independent terminals.

In Fig. 6, S is a segment signal, D is a digit signal, MC is a microcomputer, DISP is a display control circuit, K is a key scan signal, So and S7 are segment terminals, Do-D7 is a digit terminal, and F is a display element. , KQ, 7 is a key scan terminal, M is a key matrix, RO to R3 are key return terminals, and R is a key return signal. In the following explanation, the display capacity is 8 segments and 8 digits, and the key matrix M is 8 x 4.
In other words, it is assumed that 32 keys are arranged.

In the application shown in Figure 6, the key human power and display require a total of 28
In particular, one-chip microcomputers with a limited number of input/output terminals have the disadvantage that they lack terminals for other controls, narrowing the field of application. Since many terminals are taken up by manual processing, there are fewer terminals for other controls, which has the disadvantage that the microcomputer's performance cannot be fully demonstrated.

In addition, as shown in FIG. 7 (2), the digit terminal D7 is connected to the interrupt input terminal INT (I is the interrupt control circuit) of the microcomputer MC, and the period when the digit terminal D7 is active (= segment terminal SO to S7). It can also be used as a key scan signal that is segment data that is output synchronously.

In the key manual processing shown in FIG. 7, if an interrupt is generated by the digit signal of the dilet terminal D7 and the microcomputer MC is notified that the key scan signal is being output, a part of the time-division display can be performed. This period can be used for key processing, and manual key processing can be performed using the segment signal S.

The fss diagram is a time chart showing the above key manual processing. In this case, display processing and manual key processing can be performed using 21 terminals, but the display capacity is reduced to 8 segments and 7 digits, which is one digit less, and there is a serious drawback that the desired display cannot be performed. The disadvantage is that other interrupt signals cannot be input because the micro combinator's interrupt input is used, and the digit terminal D7 and interrupt input terminal IN
T is only connected externally, so these two
This has the disadvantage that terminals are wasted.

[Means for solving problems]

, the display control circuit of the present invention includes a detection means for detecting that a segment signal and a digit signal are output at a predetermined timing over one display cycle of time-division display, and a detection output of the detection means. and then for a predetermined period of time,
Additional cycle control means generates an additional cycle for outputting predetermined data written in advance in the memory from the segment terminal, and the computer outputs predetermined data from the segment terminal in response to an interrupt signal generated from the display control circuit. It is possible to know that an input has been made to the key matrix, and manual key processing can be performed by inputting a key return signal from the key return terminal in interrupt processing.

Therefore, without reducing the number of display digits and without using interrupt input terminals, display processing and key manual processing can be realized with a minimum of 20 terminals, which is 8 terminals less than conventional terminals. Therefore, a one-chip microcomputer with a limited number of terminals can control many external circuits in addition to the display and manual key processing.

〔Example〕

Next, two embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the display control circuit of the present invention, a block diagram of the digit number generation circuit which is the main part, and FIG. 2 a block diagram of the display memory. FIGS. J3 and 4 are time charts showing the operation of the digit signal generation circuit of FIG. 1, and FIG. 5 is a block diagram showing the display control circuit (key manual processing by two keys) of this embodiment.

The digit output printer CNT is a 3-bit binary input printer that performs binary output output using the clock CL as a count signal.
r), DCl, DC2). The digit decoder DD receives the count signal DC, decodes the digit signal, and outputs the digit signal to the digit terminals DO to D7. Note that in FIG. 1, a description of a cut signal for preventing erroneous light emission between digits will be omitted. The decoding circuit DEC is a detection circuit that detects that the last digit in the time-division display cycle is being displayed.
In this embodiment, since the 7th digit is the last digit, it is only necessary to detect that the count signals DCO, DCI, and DC2 are all 1. Therefore, the 7th digit When the decode signal DEN is displayed
A logical value 1 is output to D, and O is output when other digits are displayed. The latch circuit uses the decode signal DEND as a data input, uses the clock CL as a data input latte clock, delays the decode signal DEND by one cycle of the clock signal CL, and outputs a display synchronization signal SYN. Therefore, after the seventh digit is displayed, the display synchronization signal SYN becomes @1'' for a period of one cycle of the clock CL, and becomes @0# at other times.

The display synchronization signal SYN is also input to the clear input of the digit kakunta DC, and when the display synchronization signal SYN is "1", the C
, the digit input voltage DC is initialized to O to prepare for the next display cycle.

The display synchronization signal SYN is also input to the inhibit input of the digit decoder DD, and in order to prevent erroneous display when the display synchronization signal SYN is @11, the gauge decoder DD inputs the input to the digit terminals DO to D7. The active level (in this embodiment, the Roku level) is output. moreover,
The display synchronization signal SYN is manually inputted to the microcomputer MCt: a built-in interrupt control circuit through wiring inside the microcomputer.

Selector SEL selects count signal DC and specific address FA
When the display synchronization signal SYN is @0'', the count signal DC is selected, and when the display synchronization signal SYN is @1m, the specific address FA is selected and the display memory atos DA is output.Display memory DM is 9 addresses (00-08
Address) x 8 bits (b7 to bo) memory circuit, segment terminal 5o according to display memory address DA.
- Outputs the data stored in the memory to 87. In this embodiment, since the memory address is normally designated by the count signal DC, the digit terminal rb (f&=Q~7) is active.

Next, the operation of this embodiment will be explained with reference to FIGS.

The display control circuit of this embodiment operates in the same way as a conventional display control circuit from the DOf cycle to the D7 cycle, and displays 8 digits in a time-division manner. However, in the final D74) cycle, the decoding circuit Since the DEC detects that it is the last digit, the display synchronization signal SYN becomes °°1° for a period corresponding to one cycle of the clock CL, so during this period, the display memo 9 DM is a specific address 08 The address is specified, and the stored data at address 08 of display memo 9 DM is output to segment terminals SO to S7. By writing the data for key scanning in advance in address 08 of the display memory DM in this way and connecting the display element F and the key matrix M as shown in FIG. Since the display generated by DISP can be synchronized, manual key processing can be performed by inputting the key return signal R from the key return terminals RO to R3 during interrupt processing.

In this embodiment, the additional cycle is provided after the last digit cycle, but it may be at the beginning or in the middle.Also, although the key scan data is provided in the display memory, it does not need to be in the display memory.

〔Effect of the invention〕

As explained above, the present invention has a detection means for detecting the final display cycle in the conventional display control circuit, a control means for controlling the additional cycle, and a means for generating an interrupt signal synchronized with the additional cycle. Just add the circuit,
Without reducing the number of display digits and without using interrupt input terminals, display processing and key manual processing can be realized with a minimum of 20 terminals, which is 1 to 8 terminals less than the conventional one. Therefore, in a one-deep microcomputer with a limited number of terminals, it is possible to control many other external circuits in addition to the display and key manual processing, expanding the field of application of the microcomputer, and creating systems that apply the microcomputer. This has a great effect on improving the performance of

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digit signal generation circuit, FIG. 2 is a block diagram of a display memory, and FIGS. 3 and 4 are representations of the embodiment of the display control circuit of the present invention. A time chart showing the operation of the control circuit, Figure 5 is the display control circuit of Figure 1! Figures 6 and 7 are block diagrams showing key manual processing based on the conventional display control circuit. Figure 8 is a time chart showing the operation of the conventional display control circuit. be. CL ・・・・・・・・・・・・ ・ri
Rotary CNT・・・・・・・・・・・・・・・
・・Digit Kakunta DC・・・・・・・・・・・・・
...Count signal DCO~DC3...
Count signal DEC・・・・・・・・・・・・・・・Decode circuit DEND・・・・・・・・・・・・Decode signal L・・・・・・・・・・・・・・・・・・・・・・Latte circuit SYN・・・・・・・・・・・・Display synchronization signal SEL・・・・・・・・・・・・・・・Se
Data FA・・・・・・・・・・・・Specific address DA-・・・・・・・・・・・・・・・Display memory address DM・・・・・・・・・......Display memory S...Segment signal 5o-87...Segment terminal D...・・・・・・・・・・・・・・・Digital signal Do~D7 ・・・・・・・・・Digit terminal M
C・・・・・・・・・・・・・・・Microcomputer DISP・・・・・・・・・Display control circuit R・
・・・・・・・・・・・・・・・・Key return signal R
O~R3・・・・・・・・・Kiritan human power M・
・・・・・・・・・・・・・・・・Key matrix K
・・・・・・・・・・・・・・・Key scan signal KO～3 ・・・・・・・・・Key scan terminal I
NT・・・・・・・・・・・・Interrupt input terminal F
・・・・・・・・・・・・・・・Display element check...
・・・・・・・・・・・・・・・Interrupt control circuit DD
・・・・・・・・・・・・・・・Digital decoder.

Claims (1)

[Claims] Display control in which a segment signal and a digit signal are output from a segment terminal and a digit terminal, respectively, according to predetermined timing, multi-digit display is performed in a time-division manner, and the segment signal is input into a key matrix. The circuit includes a detection means for detecting that the segment signal and the digit signal are output according to a predetermined timing over one display cycle of the time-division display, and a detection means for detecting that the segment signal and the digit signal are output according to a predetermined timing over one display cycle of the time division display, and a predetermined period of time stored in the memory in advance based on the detection output of the detection means. Additional cycle control means for generating an additional cycle for outputting written predetermined data from a segment terminal; and display synchronization interrupt signal generation means for generating an interrupt signal in synchronization with the additional cycle. display control circuit.