JPS599314Y2 - Key code generation circuit - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a key code generation circuit in a key manual section of an electronic computer system.

Conventionally, the key code generation circuit for a keyboard in an electronic computer system has been completely separated from other blocks.
The system created and prepared a unique code for each key pressed, and once it was ready, it would interrupt the CPU (Central Processing Unit) to notify that a key had been pressed, and then transfer the key code to the CPU.

This method requires an independent key code generation circuit to generate the code, but since it is independent, a dedicated circuit such as a counter or key code ROM (read only memory) is required.

However, as electronic computers become smaller, it is extremely unreasonable to have circuits dedicated to specific blocks, and it is necessary to share one circuit with as many blocks as possible to simplify the circuit structure. .

This invention was made in view of the above points, and its purpose is to provide a key code generation circuit that can utilize circuits used in other than the key block and reduce the number of circuits used only for the key block as much as possible.

An embodiment of this invention will be described below with reference to the drawings.

In Fig. 1, DB is a bidirectional data bus connected to a CPU (central processing unit) (not shown), and 3-bit data DBQ sent from the CPU via this data path DB. ~DB2 is input to the buffer 12 in synchronization with the strobe signal from the decoder 11.

Address data is input to the coder 11 from the CPU via the address bus AB, and read/write data is input from the CPU via the address bus AB.
A write signal R/W is input.

This coder 11 is located at a specific address K in the memory of the CPU.
The AND signal KAD-W of AD and the write signal W is output from the output line 11a and inputted to the buffer 12 as a strobe signal, and the AND signal KAD-W of the specific address KAD of the memory of the CPU and the read signal R is outputted from the output line 11a. R is outputted from the output line 11b and inputted to the 3-state buffers 13-20 as gate signals, respectively.

Then, the output signals KiO to Ki from the buffer 12 are
2 is input to the decoder 21, and is also input to the 3-state buffers 13-20, respectively.

The decoder 21 receives the input 3-bit data K.
Coder iQ~K2 and output lines KIO~KI7
The signal is outputted from the key matrix circuit 22 and input as a key manual timing signal to the key matrix circuit 22.

This key matrix circuit 22 has seven output lines KCO.
-KC6, and when a key is operated, the key manual timing signal from the decoder 21 is selected and output to the output line to which the key is connected.

Output lines KCO to KC of the key matrix circuit 22
The signal output from 6 is sent to the encoder 23, converted into 3-bit key code signals KEO-KE2, and input to the 3-state buffers 16-18.

Also, other 3-state buffers 19. 20, the human power end is V through the resistor R.

0 power supply and is grounded via shift keys 24a and 24b.

And the above 3-state buffer 19. 20 outputs data in response to the read signal from the decoder 11, and the data DBO to DB7 are sent to the CP via the data path DB.
Sent to U.

Next, the operation of the present invention constructed as described above will be explained.

When reading key manual data, the memory address K specifies the key manual section from the CPU via the address bus AB.
AD, for example address 1000, is sent, and 3-bit data DBO to DB2 are sent from data bus DB.

The data DBO to DB2 are initially rooo and are sequentially incremented, and are written to the buffer 12 in response to a strobe signal from the coder 11.

The data written to this buffer 12 is sent to the decoder 21
The signal is decoded and input to the key matrix circuit 22 as a key manual timing signal.

The output signals KiQ to Ki2 of the buffer 12 are rooo. In this case, a “1” signal is output from the output line KIO of the decoder 21.

At this time, in the key matrix circuit 22, if a key connected to the output line KIO is operated, a "1" signal is output to any of the output lines KCO-KC6 and input to the encoder 23.

The encoder 23 encodes the signal from the key matrix circuit 22 and generates 3-bit key code signals KEO to KE.
2 and input to 3-state buffers 16-18.

Also, 3-state buffer 19. 20 is set to "O" or "1" according to the specifications of shift keys 24a and 24b.
"Signal is being input.

Furthermore, data KiO-Ki2 held in the buffer 12 is input to the 3-state buffers 13-15.

Therefore, as described above, the memory address write signal W and data DB O - DB 2 are sent from the CPU to the key manual section.
is given, and a key code signal KEO-KE2 corresponding to the key operation at that time is sent from the encoder 23 to the 3-state buffers 16 to 18. Next, a read signal R is given from the CPU along with the specified address of the key manual section. It will be done.

As a result, a key manual readout signal KAD-R is outputted from the output line 11b of the decoder 11, and is inputted as a gate signal to the 3-state buffers 13-20.

As a result, the input signals are read from 3-state buffers 13-20, and output data DBO-DB7 are sent to the CPU via data bus DB.

The data format at this time has the structure shown in FIG.

That is, the data is an 8-bit structure, and the key manual timing code Ki Q - Ki 2, 3 to 5 is the 0th to 2nd bits.
It consists of a key person code KEQ-KE2 for the bit, and shift codes Sh1 and Sh2 for the 6th and 7th bits.

The CPU determines from the above-mentioned 8-bit data DBO to DB7 whether or not there is a key force corresponding to the current keep/movement timing code, and if there is a key force, determines the content of the key force.

Furthermore, the CPU has key human timing codes KiO~K
The data with "+1" added to i2 is sent to the key manual section in FIG. 1 along with the key manual section designated address and the write signal W.

Similarly, the CPU sets the key manual timing code Ki.
Q to Ki 2 are sequentially incremented by 1 and sent to the key human power section, and the key human power data from the key human power section at that time is read to determine the content of the operated key.

As described above, according to this invention, a buffer is provided which is directly connected to the data bus line and assigned a specific address, and the buffer is addressed by the CPU,
Since the contents are sequentially incremented to obtain a key timing signal for the key input unit and the key input data is read, there is no need for a special code control circuit in the key input unit, and normal read/write operations to the memory can be performed. The key can be read manually by the code.

Moreover, the circuit structure can be simplified, and a separate pattern called a keyboard is not required, and can be incorporated into the main logic.

Furthermore, since the shift key is directly connected to the bus line, the shift state can be determined by reading the key code once.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a data format in a key input section. 11...Tecoder, 12...Buffer, 13-20...3-state buffer, 2
1...Decoder, 22...Key matrix circuit, 23...Encoder, 24a, 24
b...Shift key

Claims (1)

[Scope of utility model registration request] In an electronic computer that exchanges information between a central processing unit and peripheral devices via address bus lines and data bus lines, there is a buffer that is directly connected to the data bus line and is assigned a specific address, and It has means for incrementing the content of the specific address, a decoder for decoding the output signal of the buffer to generate sequential pulses, and a plurality of key switches, and for using the sequential pulses output from the decoder as timing signals for key scanning. key matrix circuit,
An encoder that encodes a key operation signal output from the key matrix circuit, and a shift key directly connected to the bus line, and the operation signal of the shift key, the code output from the encoder, and the buffer A key code generation circuit characterized in that a key code is generated by combining a timing signal outputted from a key code.